CN213583123U - Comparison circuit and memory chip - Google Patents
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- CN213583123U CN213583123U CN202023043317.3U CN202023043317U CN213583123U CN 213583123 U CN213583123 U CN 213583123U CN 202023043317 U CN202023043317 U CN 202023043317U CN 213583123 U CN213583123 U CN 213583123U
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Abstract
The present disclosure provides a comparison circuit and a memory chip. The comparison circuit includes: the first input end of the comparison module is connected with the voltage to be measured, and the second input end of the comparison module is connected with the reference voltage; the first input end of the state judgment module is connected with the first output end of the comparison module, and the second input end of the state judgment module is connected with the second output end of the comparison module; and the input end of the state storage module is connected with the first output end of the comparison module, and the enabling end of the state storage module is connected with the output end of the state judgment module. The embodiment of the disclosure can improve the processing efficiency of the comparison circuit.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a comparison circuit capable of rapidly comparing a varying voltage and a memory chip using the same.
Background
In a DRAM (Dynamic Random Access Memory), due to the sensitive characteristic of a low voltage, it is often necessary to perform a fast comparison on the low voltage and output a low voltage identification result to ensure that the low voltage is output normally. In the related art, an error amplifier working in a high voltage domain is generally adopted to build a comparison circuit to realize the function, but because high voltage in the DRAM is generated by a charge pump, the efficiency is low, and an error comparator usually needs to be additionally provided with a bias circuit, the comparison circuit has high power consumption, the output speed of a comparison result is low, and the requirements of the DRAM chip on high speed and low power consumption of low voltage comparison are difficult to meet.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
SUMMERY OF THE UTILITY MODEL
The present disclosure is directed to a comparison circuit and a memory chip, which overcome, at least to some extent, the problems of insufficient comparison speed, large power consumption, and the like of a low-voltage comparison circuit due to the limitations and drawbacks of the related art.
According to a first aspect of the present disclosure, there is provided a comparison circuit comprising: the first input end of the comparison module is connected with the voltage to be measured, and the second input end of the comparison module is connected with the reference voltage; the first input end of the state judgment module is connected with the first output end of the comparison module, and the second input end of the state judgment module is connected with the second output end of the comparison module; and the input end of the state storage module is connected with the first output end of the comparison module, and the enabling end of the state storage module is connected with the output end of the state judgment module.
In one exemplary embodiment of the present disclosure, the comparison circuit further includes: and the output end of the pulse generating circuit is connected with the enabling end of the comparison module.
In an exemplary embodiment of the present disclosure, the input terminal of the pulse generation circuit receives a pulse enable signal, and the control terminal of the state storage module receives a storage control signal.
In an exemplary embodiment of the present disclosure, the comparison module includes: a first transistor, a grid of which is used as a first input end of the comparison module; a second transistor, a grid of which is used as a second input end of the comparison module; a third transistor, a source of which is connected to a drain of the first transistor; a fourth transistor, a source of which is connected to a drain of the second transistor; a fifth transistor, a drain of which is used as a first output end of the comparison module, a drain of which is also connected with the drain of the third transistor and the grid of the fourth transistor, and a source of which is connected with a power supply end; a sixth transistor having a drain thereof serving as the second output terminal of the comparison module, a drain thereof further connected to the drain of the fourth transistor and the gate of the third transistor, and a source thereof connected to the power supply terminal; and a seventh transistor, a gate of which is an enable terminal of the comparison module, a drain of which is connected to the source of the first transistor and the source of the second transistor, and a drain of which is grounded.
In an exemplary embodiment of the present disclosure, the comparing module further includes: a first switch tube, a first end of which is connected with the power supply end, a second end of which is connected with the first output end of the comparison module, and a control end of which is connected with the enable end of the comparison module; and the first end of the second switching tube is connected with the power supply end, the second end of the second switching tube is connected with the second output end of the comparison module, and the control end of the second switching tube is connected with the enabling end of the comparison module.
In an exemplary embodiment of the present disclosure, the comparing module further includes: a third switching tube, wherein a first end of the third switching tube is connected with the power supply end, a second end of the third switching tube is connected with the drain electrode of the first transistor, and a control end of the third switching tube is connected with the enabling end of the comparison module; and a first end of the fourth switching tube is connected with the power supply end, a second end of the fourth switching tube is connected with the drain electrode of the second transistor, and a control end of the fourth switching tube is connected with the enabling end of the comparison module.
In an exemplary embodiment of the present disclosure, the first switching tube, the second switching tube, the third switching tube and the fourth switching tube are all P-type transistors.
In one exemplary embodiment of the present disclosure, the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor are all N-type transistors.
In one exemplary embodiment of the present disclosure, the fifth transistor and the sixth transistor are both P-type transistors.
In an exemplary embodiment of the present disclosure, the state storage module is a flip-flop or a register.
In an exemplary embodiment of the present disclosure, the state determination module includes an exclusive or gate.
In an exemplary embodiment of the present disclosure, the voltage to be measured is changed from a first voltage to a second voltage within a time T.
In one exemplary embodiment of the present disclosure, the reference voltage is greater than the first voltage and less than the second voltage.
According to a second aspect of the present disclosure, there is provided a memory chip comprising: a comparison circuit as claimed in any one of the above; the voltage to be detected is taken as the first power supply, and the second power supply supplies power for the comparison circuit.
In one exemplary embodiment of the present disclosure, the memory chip further includes: and the reference voltage generating circuit is used for generating the reference voltage.
According to the embodiment of the disclosure, the output value of the comparator is stored by using the state storage module, and the storage of the state storage module is controlled by using the control signal related to the two output results of the comparison module, so that the interval time of outputting the comparison result twice by the comparator can be shortened, the output rate of the voltage comparison result is greatly improved, and the output rate of the low-voltage comparison result in the DRAM can be improved under low power consumption without setting a bias circuit and using high-voltage power supply.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic structural diagram of a comparison circuit in an exemplary embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a comparison circuit according to another embodiment of the disclosure.
Fig. 3 is a circuit schematic of a comparison circuit in an exemplary embodiment of the disclosure.
Fig. 4 is a schematic structural diagram of a comparison module in an exemplary embodiment of the present disclosure.
Fig. 5 is a schematic structural diagram of a comparison module in another embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of a comparison module in yet another embodiment of the present disclosure.
Fig. 7 is a memory chip provided by an exemplary embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a comparison circuit in an exemplary embodiment of the present disclosure.
Referring to fig. 1, the comparison circuit 100 may include:
a first input end IN11 of the comparison module 11 is connected with the voltage to be measured Vddq, and a second input end IN12 of the comparison module is connected with a reference voltage Vref;
a state judging module 12 having a first input terminal IN21 connected to the first output terminal OUT11 of the comparing module 11 and a second input terminal IN22 connected to the second output terminal OUT12 of the comparing module 11;
the state storage module 13 has an input terminal IN3 connected to the first output terminal OUT11 of the comparison module 11, and an enable terminal EN3 connected to the output terminal OUT2 of the state determination module 12.
In the embodiment shown in fig. 1, the voltage to be measured Vddq is changed from the first voltage V1 to the second voltage V2 within the time T, and the reference voltage Vref is greater than the first voltage V1 and less than the second voltage V2. The time T varies depending on the kind of voltage to be measured.
The first output terminal OUT11 of the comparing block 11 is used for outputting the voltage detection result stored in the state storage block 13, and the second output terminal OUT12 is used for outputting a level opposite to the state of OUT12, for example, when the output level of OUT11 is high, the output level of OUT12 is low; when the output level of OUT11 is low, the output level of OUT12 is high. In the embodiment of the present disclosure, the high level and the low level are relative, and the specific voltage value of the level may be different according to the circuit setting.
The output signal of the state determining module 12 may be used to control the storage time of the state storage module 13, that is, the storage time of the state storage module 13 is controlled according to the output time of the comparing module 11, so as to accurately store the output signal of the comparing module 11, when the comparing module 11 needs to implement fast comparison, the time length that the output signal of the comparing module 11 is read by a subsequent circuit may be maintained through the state storage module 13, and power consumption of an output end of the comparing circuit for maintaining a sufficient reading time length is avoided. In addition, the state storage module 13 does not need additional clock driving, and the wiring space of the layout is saved.
Fig. 2 is a schematic diagram of a comparison circuit according to another embodiment of the disclosure.
Referring to fig. 2, the comparison circuit 100 may further include:
the output terminal OUT4 of the pulse generating circuit 14 is connected to the enable terminal EN1 of the comparing module 11.
IN an exemplary embodiment of the present disclosure, the input terminal IN4 of the pulse generating circuit 14 is used for receiving the pulse enable signal PulseEn, and the control terminal CON of the state storage module 13 is used for receiving the storage control signal Crtl.
In the embodiment shown in fig. 2, the enable terminal of the comparison module 11 is controlled by the pulse signal output by the pulse generation circuit 14, so that the input signal of the input terminal can be read only when the pulse level is the enable level, the operation of the comparison module 11 does not need to be maintained at any time, the comparison module 11 is turned off after the comparison of the comparison module 11 is finished, and the power consumption of the comparison module 11 is effectively reduced. In addition, since the enable state of the comparing module 11 is controlled by using the pulse signal, the reading timing of the comparing module 11 can be accurately controlled, and since the output signal of the comparing module 11 is stored by the signal storage module 13, the time interval between two comparisons of the comparing module 11 can be shortened, and the power consumption of the comparing module 11 can be effectively reduced. The state storage module 13 and the pulse generation circuit 14 are both controlled by corresponding enable signals, so that the flexibility of circuit arrangement can be improved, and the working state of the circuit can be changed without changing the circuit form when the state storage module 13 and/or the pulse generation circuit 14 are not needed to operate.
Fig. 3 is a circuit schematic of a comparison circuit in an exemplary embodiment of the disclosure.
Referring to fig. 3, in one embodiment, the comparing module 311 is a comparator, the state storing module 313 is a flip-flop or a register (e.g., a D flip-flop is illustrated in fig. 3 and the following description), and the state determining module 312 includes an exclusive or gate. An output signal of the exclusive or gate 312 is connected to a clock terminal of the D flip-flop 313, and a first output terminal of the comparator 311 is connected to an input terminal of the D flip-flop 313.
In the embodiment shown in fig. 3, the inverting input terminal of the comparator 311 is connected to the voltage to be measured Vddq, the inverting input terminal is connected to the reference voltage Vref, and both output terminals are connected to the xor gate 312. When the comparator 311 is not enabled, both output terminals of the comparator 311 are at a low level 0 or at a high level 1, and the output of the xor gate 312 is at a low level 0; when the comparator 311 is enabled, the output of the two output terminals of the comparator 311 is a high level 1 and a low level 0, so that the output signal of the xor gate 312 becomes a high level 1 after the comparator 311 is enabled. Since the output signal of the xor gate 312 is connected to the clock terminal of the D flip-flop 313, when the comparator 311 is enabled, the clock terminal CK of the D flip-flop 313 changes from 0 to 1, and the D flip-flop 313 stores the data of the data port D. Even if the comparator 311 is turned off again thereafter, the data held by the D flip-flop 313 is not lost. Since the comparator 311 operates only in the state where the pulse level is high and does not operate in the state where the pulse level is low, power consumption of the comparator 311 is saved. Further, the D flip-flop 313 operates only at an edge at which the output level of the exclusive or gate changes, and does not generate power consumption during a period in which the output level of the exclusive or gate does not change. The circuit of fig. 3 therefore has a lower power consumption than the prior art.
In the embodiment shown in fig. 3, the enable terminal of the comparator 311 is connected to the pulse generating circuit 14. Since the control terminal of the D flip-flop 313 is controlled by the output signal of the xor gate 312, the output signal of the comparator 311 can be latched by the D flip-flop 313 in time, so that the enable level of the pulse generating circuit 14 can be maintained for a short period of time, that is, as long as the period of time of each time of the enable level allows the comparator 311 to read the input signal and output the comparison result, the comparator 311 does not need to operate at any time, and power consumption is further reduced.
It is to be understood that the embodiments of the modules in the embodiment shown in fig. 3 are examples, and in practical applications, a person skilled in the art may implement the functions of the modules through other circuits according to the principles shown in fig. 1 and fig. 2, and the disclosure is not limited thereto.
Fig. 4 is a schematic structural diagram of a comparison module in an exemplary embodiment of the present disclosure.
Referring to fig. 4, the comparison module 11 may include:
a first transistor M1 having a gate terminal as a first input terminal of the comparison module 11;
a second transistor M2, the gate of which is the second input terminal of the comparison module 11;
a third transistor M3 having a source connected to the drain of the first transistor M1;
a fourth transistor M4 having a source connected to the drain of the second transistor M2;
a fifth transistor M5 having a drain terminal as the first output terminal of the comparison module 11, a drain terminal connected to the drain terminal of the third transistor M3 and the gate terminal of the fourth transistor M4, and a source terminal connected to the power supply terminal VDD;
a sixth transistor M6 having a drain terminal as the second output terminal of the comparison module 11, a drain terminal connected to the drain terminal of the fourth transistor M4 and the gate terminal of the third transistor M3, and a source terminal connected to the power supply terminal VDD;
the seventh transistor M7 has a gate serving as an enable terminal of the comparison module 11, a drain connected to the source of the first transistor M1 and the source of the second transistor M2, and a drain connected to ground.
In one exemplary embodiment of the present disclosure, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the seventh transistor M7 are all N-type transistors, and the fifth transistor M5 and the sixth transistor M6 are all P-type transistors.
Referring to fig. 4, in addition to improving the circuit externally connected to the comparison module 11 to reduce power consumption and increase comparison speed, the embodiment of the present disclosure also improves the circuit of the comparison module 11 itself. In the embodiment shown in fig. 4, a strongARM structure dynamic comparator is formed by using the first transistor M1 to the seventh transistor M7. In the dynamic comparator, the gates of the two transistors of the left arm (composed of the third transistor M3 and the fifth transistor M5) are connected to the drain connection point (the first node N1) of the two transistors of the right arm (composed of the fourth transistor M4 and the sixth transistor M6), and the first node N1 is used as one output end of the dynamic comparator; the gates of the two transistors of the right arm are connected to the connection point of the drains of the two transistors of the left arm (the second node N2), the second node N2 is used as the other output end of the dynamic comparator, when the enable signal En is at a low level, the seventh transistor M7 is turned off, the M5-M3-M1 path and the M6-M4-M2 path have no low potential, the first node N1 of the drain of the fifth transistor M5 and the second node N2 of the drain of the sixth transistor M6 are both pulled to a high level VDD, and the drains of the two transistors from the power supply VDD to the seventh transistor are at a high level; when the enable signal is at a high level, the seventh transistor M7 is turned on, the first transistor M1 and the second transistor M2 are turned on under the influence of the input voltages Vin1 and Vin2, and when Vin1 and Vin2 are not equal, the on-resistances of the first transistor M1 and the second transistor M2 are not equal, that is, the speed of discharging the first node N1 or the second node N2 to a low level is not equal. If Vin1 is greater than Vin2, the discharging rate of the first node N1 is greater than the discharging rate of the second node N2, the voltage of the first node N1 reaches the low level GND more quickly, the fourth transistor M4 is turned off, the sixth transistor M6 is turned on, the drain of the fourth transistor M4 is equal to the high level VDD, the voltage of the second node N2 is greater than the voltage GND of the first node N1, and the voltage comparison result is output; similarly, if Vin1 is smaller than Vin2, the voltage of the second node N2 reaches the low level GND more quickly, the third transistor M3 is turned off, the fifth transistor M5 is turned on, the voltage of the drain of the third transistor M3 at the first node N1 is equal to the high level VDD and is greater than the voltage GND at the second node N2, and the voltage comparison result is output. Since the discharging speed is greater than the charging speed, the circuit of the embodiment shown in fig. 4 can output the voltage comparison result faster than the related art, thereby increasing the speed of the comparator.
Fig. 5 is a schematic structural diagram of a comparison module in another embodiment of the present disclosure.
Referring to fig. 5, the comparison module 11 may further include:
a first switch tube S1, having a first end connected to the power supply terminal VDD, a second end connected to the first output terminal of the comparison module 11, and a control end connected to the enable terminal of the comparison module 11;
the first end of the second switch tube S2 is connected to the power source end, the second end thereof is connected to the second output end of the comparing module 11, and the control end thereof is connected to the enable end of the comparing module 11.
In the embodiment shown in fig. 5, a parallel first switch tube S1 is added to the fifth switch tube M5, and the control terminal of the first switch tube S1 is connected to the enable terminal of the comparator; the sixth switch tube M6 is added with the second switch tube S2 connected in parallel, and the control end of the second switch tube S2 is connected to the enable end of the comparator. Thus, when the first switch tube S1 and the second switch tube S2 are both turned on under the control of the low level of the enable terminal connection (in some embodiments, the low level exists in the pulse signal and is generated by the pulse generation circuit 14), the seventh transistor M7 is turned off, the first node N1 and the second node N2 are both pulled to the high level VDD, and when the first switch tube S1 and the second switch tube S2 are both turned off under the control of the high level of the enable terminal connection (which may be the high level in the pulse signal), the seventh transistor M7 is turned on, and one of the first node N1 and the second node N2 is discharged to the low level GND more quickly, so that one of the first node N1 and the second node N2 is the high level GND and the other is the low level GND (see the description of the embodiment shown in fig. 4). Since the arrangement of the first switch tube S1 and the second switch tube S2 directly sets the voltages of the first node N1 and the second node N2 to VDD, rather than charging the voltages of the first node N1 and the second node N2 to VDD through the junction capacitance of the sixth transistor M6 and the junction capacitance of the fifth transistor M5 in the embodiment shown in fig. 4, the arrangement of the first switch tube S1 and the second switch tube S2 speeds up the comparison speed of the comparator.
Fig. 6 is a schematic structural diagram of a comparison module in yet another embodiment of the present disclosure.
Referring to fig. 6, the comparison module 11 may further include:
a third switch tube S3, having a first end connected to the power source terminal VDD, a second end connected to the drain of the first transistor M1, and a control end connected to the enable end of the comparison module 11;
the fourth switch transistor S4 has a first terminal connected to the power source terminal VDD, a second terminal connected to the drain of the second transistor M2, and a control terminal connected to the enable terminal of the comparison module 11.
In an exemplary embodiment of the present disclosure, the first switching tube S1, the second switching tube S2, the third switching tube S3 and the fourth switching tube S4 are all P-type transistors.
In the embodiment shown in fig. 6, the third switching transistor S3 is provided between the drain of the first transistor M1 and the power supply VDD, the fourth switching transistor S4 is provided between the drain of the second transistor M2 and the power supply VDD, and the third switching transistor S3 and the fourth switching transistor S4 are controlled using the enable signal, so that the source of the third transistor M3 and the source of the fourth transistor M4 are directly set to the high level VDD when both the third switching transistor S3 and the fourth switching transistor S4 are turned on by being controlled by the low level of the enable terminal connection (in some embodiments, the low level exists in the pulse signal and is generated by the pulse generation circuit 14). As can be seen from the above analysis, the seventh transistor M7 is turned off, and the first node N1 and the second node N2 are both at the high level VDD. When the third switch tube S3 and the fourth switch tube S4 are both controlled by the high level of the connection of the enable terminals to be turned on, the seventh transistor M7 is turned on, the first transistor M1 and the second transistor M2 provide a discharge path, and the magnitude of Vin1 and Vin2 affects which of the first node N1 and the second node N2 reaches the low level GND first, so that the level of the other node is changed to the high level VDD, and the comparison result is output.
Since the third switch transistor S3 directly sets the drain of the first transistor M1 to VDD, it is avoided that the charging of the junction capacitor of the turned-on first transistor M1 via the turned-on third transistor M3 or the charging of the junction capacitor of the turned-on second transistor M2 via the turned-on fourth transistor M4 after the first node N1 and the second node N2 are set to high level VDD affects the time when the first node N1 and the second node N2 reach the stable high level VDD. Meanwhile, it is avoided that the voltage of the first node N1 is not completely equal to the voltage of the second node N2 (also affected by the divided voltage of the resistance of the turned-on second transistor M2) due to the divided voltage of the resistance of the turned-on first transistor M1. Therefore, the arrangement of the third switch tube S3 and the fourth switch tube S4 can further improve the comparison speed of the comparator.
Since the first to fourth switching tubes S1 to S4 and the seventh transistor M7 are controlled by the enable signal En of the comparison module 11, only one enable signal in the form of a pulse signal can be used to implement the conversion of the enable level, thereby increasing the comparison speed of the comparator.
Therefore, the dynamic comparator shown in fig. 4 to 6 can greatly improve the output speed of the comparison result.
The present disclosure also provides a memory chip applying the comparison circuit provided in any of the above-described embodiments.
Fig. 7 is a memory chip provided by an exemplary embodiment of the present disclosure.
Referring to fig. 7, a memory chip 700 may include:
the comparison circuit 71 as in any of the above;
a first power supply 72 and a second power supply 73, the first power supply 72 being the voltage to be measured, the second power supply 73 supplying power to the comparison circuit.
In one exemplary embodiment of the present disclosure, the memory chip further includes: and a reference voltage generating circuit 74 for generating the reference voltage Vref in the comparing circuit 71.
In the embodiment shown in fig. 7, the second power supply 73 corresponds to the power supply VDD in the embodiment shown in fig. 4 to 6. The memory chip 700 can realize higher memory speed and lower power consumption due to the use of the low power consumption, high comparison speed comparison circuit 71.
In summary, in the embodiment of the present disclosure, the storage timing of the state storage module 13 is controlled by using the two output signals of the comparison module 11, so that the state storage module 13 stores the output signal of the comparator 11, which can effectively improve the comparison rate and reduce power consumption; by controlling the comparison module 11 using the pulse signal generated by the pulse generation module 14, the power consumption of the comparison circuit can be reduced; by improving the use of dynamic comparators for the internal circuitry of the comparison module 11, the comparison rate of the comparison module 11 itself may be increased. After the superposition effect, the comparison circuit provided by the embodiment of the disclosure can have higher comparison speed and lower power consumption.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (15)
1. A comparison circuit, comprising:
the first input end of the comparison module is connected with the voltage to be measured, and the second input end of the comparison module is connected with the reference voltage;
the first input end of the state judgment module is connected with the first output end of the comparison module, and the second input end of the state judgment module is connected with the second output end of the comparison module;
and the input end of the state storage module is connected with the first output end of the comparison module, and the enabling end of the state storage module is connected with the output end of the state judgment module.
2. The comparison circuit of claim 1, further comprising:
and the output end of the pulse generating circuit is connected with the enabling end of the comparison module.
3. The comparison circuit of claim 2 wherein the input of the pulse generation circuit receives a pulse enable signal and the control of the state storage module receives a storage control signal.
4. The comparison circuit of claim 3, wherein the comparison module comprises:
a first transistor, a grid of which is used as a first input end of the comparison module;
a second transistor, a grid of which is used as a second input end of the comparison module;
a third transistor, a source of which is connected to a drain of the first transistor;
a fourth transistor, a source of which is connected to a drain of the second transistor;
a fifth transistor, a drain of which is used as a first output end of the comparison module, a drain of which is also connected with the drain of the third transistor and the grid of the fourth transistor, and a source of which is connected with a power supply end;
a sixth transistor having a drain thereof serving as the second output terminal of the comparison module, a drain thereof further connected to the drain of the fourth transistor and the gate of the third transistor, and a source thereof connected to the power supply terminal;
and a seventh transistor, a gate of which is an enable terminal of the comparison module, a drain of which is connected to the source of the first transistor and the source of the second transistor, and a drain of which is grounded.
5. The comparison circuit of claim 4, wherein the comparison module further comprises:
a first switch tube, a first end of which is connected with the power supply end, a second end of which is connected with the first output end of the comparison module, and a control end of which is connected with the enable end of the comparison module;
and the first end of the second switching tube is connected with the power supply end, the second end of the second switching tube is connected with the second output end of the comparison module, and the control end of the second switching tube is connected with the enabling end of the comparison module.
6. The comparison circuit of claim 5, wherein the comparison module further comprises:
a third switching tube, wherein a first end of the third switching tube is connected with the power supply end, a second end of the third switching tube is connected with the drain electrode of the first transistor, and a control end of the third switching tube is connected with the enabling end of the comparison module;
and a first end of the fourth switching tube is connected with the power supply end, a second end of the fourth switching tube is connected with the drain electrode of the second transistor, and a control end of the fourth switching tube is connected with the enabling end of the comparison module.
7. The comparison circuit as claimed in claim 6, wherein said first switch tube, said second switch tube, said third switch tube and said fourth switch tube are all P-type transistors.
8. The comparison circuit according to claim 6, wherein the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor are all N-type transistors.
9. The comparison circuit according to claim 6, wherein the fifth transistor and the sixth transistor are both P-type transistors.
10. The comparison circuit of claim 1 wherein said state storage module is a flip-flop or a register.
11. The comparison circuit of claim 1 wherein said state decision module comprises an exclusive or gate.
12. The comparison circuit according to claim 1, wherein the voltage to be measured changes from a first voltage to a second voltage within a time T.
13. The comparison circuit of claim 12, wherein the reference voltage is greater than the first voltage and less than the second voltage.
14. A memory chip, comprising:
a comparison circuit as claimed in any one of claims 1 to 13;
the voltage to be detected is taken as the first power supply, and the second power supply supplies power for the comparison circuit.
15. The memory chip of claim 14, further comprising:
and the reference voltage generating circuit is used for generating the reference voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202023043317.3U CN213583123U (en) | 2020-12-16 | 2020-12-16 | Comparison circuit and memory chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202023043317.3U CN213583123U (en) | 2020-12-16 | 2020-12-16 | Comparison circuit and memory chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114639422A (en) * | 2020-12-16 | 2022-06-17 | 长鑫存储技术(上海)有限公司 | Comparison circuit and memory chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114639422A (en) * | 2020-12-16 | 2022-06-17 | 长鑫存储技术(上海)有限公司 | Comparison circuit and memory chip |
| WO2022127161A1 (en) * | 2020-12-16 | 2022-06-23 | 长鑫存储技术有限公司 | Comparison circuit and memory chip |
| US12119067B2 (en) | 2020-12-16 | 2024-10-15 | Changxin Memory Technologies, Inc. | Comparison circuit and memory chip |
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