CN213519272U

CN213519272U - Reading circuit of memory

Info

Publication number: CN213519272U
Application number: CN202021778988.1U
Authority: CN
Inventors: 赵立新; 乔劲轩; 魏经纬; 黄诗剑
Original assignee: Geke Microelectronics Shanghai Co Ltd
Current assignee: Geke Microelectronics Shanghai Co Ltd; Galaxycore Shanghai Ltd Corp
Priority date: 2020-08-24
Filing date: 2020-08-24
Publication date: 2021-06-22
Anticipated expiration: 2030-08-24

Abstract

The utility model provides a reading circuit of memory. The reading circuit includes: the device comprises a pre-charging module, a storage unit and an amplifier module; in the pre-charging module or the amplifier module, the data reading process of the current reading period is controlled through the reading result of at least one reading period, so that the accuracy of data reading is improved. The utility model discloses an at least one reading cycle's reading result before utilizing adjusts the current relevant parameter who reads the cycle, can improve the degree of accuracy that data read.

Description

Reading circuit of memory

Technical Field

The utility model relates to an integrated circuit technical field especially relates to a reading circuit of memory.

Background

At present, the amount of data stored in a chip is larger and larger, and the speed requirement of data reading is higher and higher. At high speed reading, the error rate of data can increase, limiting the accuracy of data reading. The speed and accuracy of data read in memory is becoming increasingly a bottleneck limiting the operating speed and overall performance of the chip.

In current data sensing circuits, data in a memory cell is sensed via differential bit lines. The reading of data mainly comprises three steps: firstly, a pre-charge module charges a bit line; secondly, the storage unit is connected with the bit lines and controls the bit lines to discharge, and after the discharge, a voltage difference value exists between the two bit lines; finally, the amplifier module detects and amplifies the voltage difference between the two bit lines, so as to read data in the memory cell (refer to the related description of fig. 1 in particular). Since the number of memory cells connected to the bit line is large, the bit line itself is long, and when data is read at a high frequency, the voltage drop on the bit line is limited and cannot reach the operating range of the amplifier, so that the bit error rate of the read data is increased, and the data cannot be accurately read. Thus, the speed and accuracy of data read in memory is increasingly becoming a bottleneck limiting the speed of chip operation and overall performance.

The existing methods for improving the data reading speed of a memory cell in a memory and further improving the accuracy of data reading under high-speed reading mainly comprise the following two methods: (1) starting from the structure of the memory cell, increasing the reading current and increasing the voltage difference of a group of bit lines in the same reading time; (2) from the structure of the bit lines, the number of the memory cells connected to one bit line is reduced or the length of the bit line is shortened through reasonable grouping and splitting, so that the parasitic capacitance and the resistance of the bit line are reduced, and the voltage difference of a group of bit lines during reading can be increased. However, the above two methods have the following problems: (1) the space structure of the memory cell circuit or the bit line is optimized, the design needs to be carried out according to specific requirements, the method is complex, and the universality is relatively poor; (2) when the data reading limit frequency is improved, the power consumption and the noise of a circuit during low-frequency data reading are not reduced, the problems of high power consumption and high noise still exist, and the overall performance of a chip is further influenced.

SUMMERY OF THE UTILITY MODEL

In view of the above problems in the prior art, it is an object of the present invention to provide a reading circuit of a memory.

In a first aspect, the present invention provides a reading circuit for a memory. The reading circuit includes: the device comprises a pre-charging module, a storage unit and an amplifier module; in the pre-charging module or the amplifier module, the data reading process of the current reading period is controlled through the reading result of at least one reading period, so that the accuracy of data reading is improved.

Optionally, in the precharge module, the bit line charging and discharging process is controlled according to the read result of at least one previous read cycle, so as to control the data read process of the current cycle.

Optionally, the bit line is connected to a pull-up branch controlled by a read result of at least one previous read cycle, and is used for charging the bit line to adjust a charging speed of the bit line in a current read cycle.

Optionally, the bit lines are further connected to a charging tube controlled by a preset control voltage, and the charging tube is used for charging the bit lines together.

Optionally, the bit line is connected to a pull-down branch controlled by a read result of at least one previous read cycle, and is configured to discharge the bit line to adjust a discharge speed of the bit line in a current cycle.

Optionally, the bit line is connected to a clamping circuit for clamping the bit line to limit the lowest voltage of the bit line.

Optionally, the clamping circuit includes a first NMOS transistor and a second NMOS transistor; the source electrode of the first NMOS tube is connected with a first bit line in the bit lines; the source electrode of the second NMOS tube is connected with a second bit line in the bit lines; the grid electrodes of the first NMOS tube and the second NMOS tube are connected to a clamping control voltage together; the drain electrodes of the first NMOS tube and the second NMOS tube are connected to a third potential together; when the voltage of the first bit line is lower than the difference between the clamp control voltage and the threshold voltage of the first NOMS tube, the first NMOS tube is conducted to pull up the voltage of the first bit line to the difference between the clamp control voltage and the threshold voltage of the first NOMS tube; when the voltage of the second bit line is lower than the difference between the clamp control voltage and the threshold voltage of the second NOMS tube, the second NMOS tube is conducted to pull up the voltage of the second bit line to the difference between the clamp control voltage and the threshold voltage of the second NOMS tube.

Optionally, the amplifier module is connected to a feedback control module controlled by a read result of at least one previous read cycle, and is configured to control a data read process of a current cycle.

Optionally, the feedback control module controlled by the read result is connected to the input node of the amplifier module through a capacitor, so as to control the voltage of the input node of the amplifier module.

In a second aspect, the present invention provides another read circuit for a memory. The reading circuit includes: the memory comprises a precharge module, a bit line, a plurality of memory cells, an amplifier module and a feedback control module; the feedback control module is suitable for controlling the data reading process of the current reading period based on the reading result of at least one previous reading period so as to improve the accuracy of data reading.

Optionally, the read result further includes a read address.

Optionally, the feedback control module is further adapted to control a charging and discharging process of the bit line based on a reading result of at least one previous reading cycle, so as to control a data reading process of a current reading cycle.

Optionally, the feedback control module is further adapted to control a speed and/or time of charging and discharging the bit line in a current read cycle based on a read result of at least one previous read cycle.

Optionally, the feedback control module includes at least two PMOS transistors; the source electrode of each PMOS tube is connected with a power supply in the pre-charging module; the drain electrode of each PMOS tube is connected with the bit line; the pre-charge module charges the bit line through the at least two PMOS tubes; the feedback control module is further adapted to control the speed of charging the bit line through the at least two PMOS tubes based on the read result of the previous at least one read cycle.

Optionally, the feedback control module includes at least two NMOS transistors; the drain electrode of each NMOS tube is connected with the bit line; the source electrode of each NMOS tube is connected to a first potential in common; the feedback control module is further adapted to control the speed of discharging the bit line through the at least two NMOS transistors based on the read result of the previous at least one read cycle.

Optionally, the feedback control module includes at least two CMOS inverters; the source electrode of a PMOS tube in each CMOS phase inverter is connected with the power supply in the pre-charging module; the drain electrodes of the PMOS tube and the NMOS tube in each CMOS phase inverter are connected with the bit line; the source electrodes of the NMOS tubes in each CMOS phase inverter are connected to a second potential in common; the feedback control module is further adapted to control a speed of charging and discharging the bit line through the at least two CMOS inverters based on a read result of a previous at least one read cycle.

Optionally, the feedback control module includes: a clamp circuit; the clamping circuit is adapted to clamp the bit line to limit a lowest voltage of the bit line.

Optionally, the amplifier module is connected to the feedback control module; the feedback control module is further adapted to control the relevant parameters of the amplifier module based on the reading result of at least one previous reading cycle to control the data reading process of the current reading cycle.

Optionally, the feedback control module is connected to the input node of the amplifier module through a capacitor; the feedback control module is further adapted to control the input node voltage of the amplifier module based on the read result of at least one previous read cycle to control the data read process of the current read cycle.

As described above, compared with the prior art, the reading circuit of the memory of the present invention has the following beneficial effects:

(1) when data is read from the memory cells in the memory, the data reading process of the current reading cycle can be controlled through the reading result of at least one previous reading cycle and related data, so that the problem that the voltage difference on the bit line cannot reach the working range of the amplifier under a high data reading frequency is avoided, and the accuracy of data reading can be improved.

(2) The utility model discloses can form new pre-charge module or amplifier module through increasing different components and parts on the basis of pre-charge module, amplifier module. The utility model discloses also can form solitary feedback control module through increasing different components and parts, this feedback control module can read the reading result of cycle and the charge-discharge process of relevant data control bit line through at least one before through. The utility model discloses need not improve the memory cell in the memory itself, this method is simple easily realizes and maneuverability is strong.

(3) The utility model provides an increase clamp circuit on the basis of pre-charge module, can avoid the bit line to discharge to the low potential of crossing excessively, prevent to read data in-process bit line and cause the interference to the memory cell signal to consumption and noise when data read under can reducing the low frequency improve the wholeness ability of chip.

Additional features of the invention will be set forth in part in the description which follows. Additional features of the invention will be set forth in part in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following and the accompanying drawings or may be learned from the manufacture or operation of the embodiments. The features of the present invention may be realized and attained by practice or use of the methods, instrumentalities and combinations particularly pointed out in the appended claims.

Drawings

Other features, objects and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.

FIG. 1 is an exemplary schematic diagram of a prior art read circuit for a memory cell;

FIG. 2 is an exemplary circuit diagram of the pre-charge module of FIG. 1;

FIG. 3 is an exemplary circuit diagram of the memory cell of FIG. 1;

FIG. 4 is an exemplary circuit diagram of the amplifier module of FIG. 1;

fig. 5 is a circuit diagram of a feedback control module of a read circuit of a memory according to an exemplary embodiment of the present invention;

fig. 6 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention;

fig. 7 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention;

fig. 8 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention;

fig. 9 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention;

fig. 10 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention;

fig. 11 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention;

fig. 12 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention;

fig. 13 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention;

FIG. 14 is a timing diagram for reading data of a memory cell according to the reading circuit of FIG. 1;

fig. 15 is a schematic diagram of a read circuit of a memory according to an exemplary embodiment of the present invention;

fig. 16 is a timing diagram of a read circuit reading data of a memory cell according to an exemplary embodiment of the present invention;

in the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.

Detailed Description

For solving the problem among the above-mentioned prior art, the utility model provides a method of data reading of memory and reading circuit, through increasing feedback control module, based on the current data reading process that reads cycle of reading result control of at least one reading cycle before, and then improve the degree of accuracy that reads data under high-speed reading, promote data reading speed, improve data reading ability, the method is simple easily to be realized, maneuverability is strong, power consumption and noise when data reading under the low frequency can also be reduced in addition, improve chip wholeness ability.

In the following detailed description of the embodiments, reference is made to the accompanying drawings, which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

FIG. 1 is a schematic diagram of a sensing circuit in a memory, the sensing circuit including a precharge module 110, a plurality of memory cells 120-1, 120-2, …, 120-n, and an amplifier module 130.

Fig. 2 is an exemplary circuit diagram of the pre-charge module 110 in fig. 1.

Fig. 3 is an exemplary circuit diagram of one of the memory cells 120-1 of fig. 1.

Fig. 4 is an exemplary circuit diagram of the amplifier module 130 of fig. 1.

Taking a Static Random Access Memory (SRAM) as an example, the circuits of these three parts are shown in fig. 2-4, respectively. For example, taking the memory cell 120-1 as an example, during the data reading process, the precharge module 110 is first enabled to charge the value of the bit line BL/BLB to a high voltage; then, setting the word line WL signal high, reading the data in the memory cell 120-1, and enabling the voltage of the bit line BL/BLB to have a certain voltage difference; finally, the voltage difference is transmitted to the amplifier module 130, and the data Q/QB is read out after the voltage difference is amplified.

The data reading process is as follows: as shown in FIG. 3, in memory cell 120-1, during data writing, peripheral circuitry (not shown) sets the BIT line BL and BLB signals to opposite values, e.g., 1 and 0, respectively, and then sets the WL signal to 1, at which time the value of BL/BLB may be written to the BIT and BITB points for storage; in data reading, the gate control voltage PRCHB (also referred to as a preset control voltage) signal of the charging transistors P3 and P4 in fig. 2 is set to 0, the BIT line BL/BLB signal is pulled to a high voltage and then set to 1 in the P2/P3/P4 transistor, and then the word line WL signal is set to 1, assuming that the voltage at the BIT/BITB point is 1 and 0 respectively, the charge on the BLB flows out from the channels of N3 and N0, and at this time, since the voltage at the BITB point is 0, N1 is in an off state, the BIT line BL voltage is unchanged. Therefore, the voltages of BL and BLB will have a certain voltage difference while the word line WL is set to 1. Wherein, the P0/P1/P2/P3/P4 tube is PMOS tube, and the N0/N1/N2/N3 tube is NMOS tube.

As shown in fig. 4, BLSWB is the gate control voltage signal of the M1 transistor, and the voltage of the bit line BL/BLB is transferred to the input signal DL/DLB of the amplifier module 130 via the M1 transistor; SACHB is a grid control voltage signal of the M3 tube, and the power supply charges the input signal DL/DLB of the amplifier module 130 through the M3 tube; SAEN is an enable signal for the amplifier module 130. When BLSWB is 0 and SACHB is 1, the voltage of BL/BLB is transmitted to DL/DLB through M3/M4 tube; after the bit line transmits the BL/BLB voltage to the DL/DLB point, the SAEN is set to 1, the amplifier module 130 is enabled, the amplifier module amplifies the voltage difference of the DL/DLB, the voltages of the DL/DLB and the DLB are respectively pulled to

logic

1 and 0, subsequent processing can be carried out, and the data reading process is completed; after the readout process is completed, SACHB is set to 1, SAEN is set to 0, and the power supply charges the potential of the DL/DLB point to the power supply voltage VDD through M3/M4. Wherein, the M1/M2/M3/M4 tube is a PMOS tube.

The utility model provides a data reading circuit of memory. The data reading circuit can control the data reading process of the current reading period through the reading result of at least one reading period before so as to improve the accuracy of data reading. The previous at least one read cycle may be referred to as at least one history read cycle. The previous at least one read cycle may be a previous read cycle of the current read cycle, or may be a plurality of read cycles before the current read cycle. For example, the process of reading the current memory cell is the current read cycle, and the process of reading the previous memory cell is the previous read cycle.

In some embodiments, the data reading circuit may include a precharge module, a bit line, a plurality of memory cells, an amplifier module, a feedback control module, and the like. The feedback control module can control the data reading process of the current reading period based on the reading result of at least one previous reading period so as to improve the accuracy of data reading. The reading circuit is added with a feedback control module on the basis of the reading circuit shown in the figure 1. Specifically, the memory may include a precharge module, a word line, a bit line, a plurality of memory cells, an amplifier module, a feedback control module, and the like. The precharge module is connected with the bit line. The precharge module may precharge the bit line according to a precharge signal. The storage unit may store various types of data. The amplifier module is connected to the bit line and can read data stored in the selected memory cell. Wherein memory may generally refer to devices having memory functionality. The memory may include a Static Random Access Memory (SRAM), a Dynamic Random Access Memory (DRAM), a nonvolatile memory, a ferroelectric memory (FRAM), a phase change memory (PRAM), a magnetic memory (MRAM), a Resistive Random Access Memory (RRAM), and the like. The feedback control module may control a data reading process of a current reading cycle based on a reading result of at least one previous reading cycle. In some embodiments, the read result includes a read address of the memory cell. In some embodiments, the feedback control module may control a speed and/or a time of charging and discharging the bit line by the precharge module in a current read cycle based on a read result of at least one previous read cycle. The read cycle for reading the memory cell may include: the processes of precharging the bit lines, discharging the bit lines, and reading data stored in the memory cells are not limited herein.

In some embodiments, the data reading circuit may include a precharge module, a bit line, a plurality of memory cells, an amplifier module, and the like. The pre-charge module and/or the amplifier module can control the data reading process of the current reading cycle through the reading result of at least one previous reading cycle so as to improve the accuracy of data reading. In some embodiments, a feedback control module may be added to the precharge module to form a new precharge module, for example, as shown in fig. 5-11. In some embodiments, adding a feedback control module to the amplifier module may form a new amplifier module, for example, as shown in fig. 12 and 13.

Specifically, the present invention exemplarily provides circuit diagrams of various feedback control modules, and particularly, the description of fig. 5 to 16 may be referred to. It should be noted that the feedback control blocks in fig. 5 to 13 may exist independently, or may be combined with the precharge block to form a new precharge block, or may be combined with the amplifier block to form a new amplifier block.

Fig. 5 is a circuit diagram of a feedback control module of a read circuit of a memory according to an exemplary embodiment of the present invention.

Fig. 5 is a circuit diagram of the read circuit of fig. 1, in which a feedback control module 210 is added, and the feedback control module 210 is connected to the precharge module 110. The feedback control module 210 may also be referred to as a pull-up leg.

As shown in FIG. 5, the feedback control module 210 includes at least two PMOS tubes (P4, P5) (only two shown). The source of each PMOS transistor is connected to the power supply in the precharge module 110. The drain of each PMOS transistor is connected to a bit line BL/BLB. The precharge module 110 may charge the bit line BL/BLB through at least two PMOS transistors. The feedback control module 210 may control a speed of charging the bit line BL/BLB through at least two PMOS transistors based on a read result of a previous at least one read cycle. Wherein, the at least two PMOS transistors are controlled by the read result of at least one read cycle before. For example, in the read circuit shown in fig. 1, when the next memory cell is to be read after the previous read cycle is finished (the previous memory cell has been read), the precharge module 110 needs to charge the potential of the bit line BL/BLB. At high speed reading, the bit line discharged to a lower voltage in the previous read cycle may not reach a sufficiently high voltage due to the shorter charge time and the slower charge speed. During the current read cycle, after a period of discharge, the voltage of one of the bit lines BL or BLB drops, and the voltage difference between the bit lines BL and BLB may be too small. Since the voltage difference between the bit line BL and the bit line BLB is too small, an error may occur in the data read through the amplifier module 130. In this embodiment, the two PMOS transistors of the feedback control module 210 may adjust the charging speed of the bit line BL/BLB according to whether the PMOS transistor is turned on or not, based on the result Q/QB read in the previous read cycle. For example, when Q or QB is high, i.e. the PMOS transistor is turned on, the charging speed of the bit line can be increased. Therefore, the charging speed of the bit line which is discharged to a lower voltage in the previous reading period can be increased by increasing the PMOS tube, the feedback control process can be continued until the discharging process, so that the bit line BL or one bit line BLB can reach a higher voltage after the pre-charging is finished, and after a period of discharging, the voltage difference of the bit line BL and the bit line BLB which are input to the amplifier module can be increased. Therefore, when the data in the memory cell is currently read, the feedback control module 210 adjusts the voltage difference of the bit line BL/BLB, so that the data stored in the memory cell can be correctly read in the current read cycle. In some embodiments, the feedback control module 210 may also control the reading process of the current reading cycle based on the reading address of the memory cell and the reading result. For example, the read process of the current read cycle process may be controlled based on the read address and the read result of one or more memory cells during the previous at least one read cycle. In some embodiments, the feedback control module 210 can be designed by increasing the number of PMOS transistors, which is not limited herein.

Fig. 6 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram of the read circuit of FIG. 1, in which a feedback control block 220 is added, and the feedback control block 220 is connected to the bit line BL/BLB. The feedback control module 220 may also be referred to as a pull-down leg.

As shown in FIG. 6, the feedback control module 220 includes at least two NMOS transistors (N4, N5) (only two are shown). The drain of each NMOS transistor is connected to a bit line BL/BLB. The sources of each NMOS transistor are commonly connected to a first potential (e.g., VSS in FIG. 6). For example, the source of each NMOS transistor may be commonly grounded. The feedback control module 220 may control the speed of discharging the bit lines BL/BLB by the two NMOS transistors based on the read result of at least one previous read cycle. Wherein, the at least two NMOS transistors are controlled by the read result of at least one previous read cycle. For example, in the read circuit shown in fig. 1, when the next memory cell is to be read after the previous read cycle is finished (the previous memory cell has been read), the precharge module 110 needs to charge the bit line BL/BLB. In the current read cycle, after a period of discharge, the voltage of one of the bit lines BL or BLB drops, and because the discharge speed is slow, and a bit line does not reach a sufficiently low potential, the voltage difference between BL and BLB may be too small. Since the voltage difference between the bit line BL and the bit line BLB is too small, an error may occur in the data read through the amplifier module 130. In the present embodiment, the two NMOS transistors of the feedback control module 220 are used to adjust the discharging speed of the bit line BL/BLB according to whether the two NMOS transistors are turned on or not based on the result Q/QB read in the previous read cycle. For example, when Q or QB is high, i.e. the NMOS transistor is turned on, the discharge speed of the bit line can be increased. Therefore, the discharge speed of the bit line with higher voltage after discharge in the previous reading period in the current reading period can be increased by adding the NMOS transistor, so that one of the bit line BL or the bit line BLB can reach a lower voltage after the discharge is finished, and thus the potential difference between the bit line BL and the bit line BLB can be increased, that is, the voltage of the bit line originally at the low potential is continuously pulled down, so that the voltage difference between the bit line BL and the bit line BLB is further increased, and the amplifier module 130 can correctly read data. Therefore, when the data in the memory cell is currently read, the feedback control module 220 adjusts the potential difference between the bit line BL and the bit line BLB, so that the data stored in the memory cell can be correctly read in the current read cycle. In some embodiments, the feedback control module 210 may control the read process of the current read cycle based on the read address of the memory cell and the read result. For example, the read process of the current read cycle may be controlled based on the read address and the read result of one or more memory cells during at least one previous read cycle. In some embodiments, the number of NMOS transistors may be increased to design different feedback control modules 220, which is not limited herein.

Fig. 7 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention.

Fig. 7 is a circuit diagram of the read circuit of fig. 1, with the addition of a feedback control module 230.

As shown in fig. 7, the feedback control block 230 includes two CMOS inverters. The source of the PMOS transistor in each CMOS inverter is connected to the power supply in the pre-charge module 110. The drains of the PMOS tube and the NMOS tube in each CMOS inverter are connected with a bit line. The sources of the NMOS transistors in each CMOS inverter are commonly connected to a second potential (e.g., VSS in FIG. 7). For example, the source of each NMOS transistor may be commonly grounded. The feedback control module 230 may control the rate at which the two CMOS inverters charge and discharge the bit line based on the read result of the previous at least one read cycle. In this embodiment, based on the result Q/QB read in the previous read cycle, the two CMOS inverters of the feedback control module 220 may adjust the charging and/or discharging speed of the bit line BL/BLB, so that the bit line BL and the bit line BLB may reach a larger voltage difference before being input to the amplifier module 130, and thus the data stored in the memory cell may be correctly read in the current read cycle. In some embodiments, the feedback control module 210 may control the read process of the current read cycle based on the read address of the memory cell and the read result. For example, the read process of the current read cycle process may be controlled based on the read address and the read result of one or more memory cells during at least one previous read cycle. In some embodiments, the feedback control module 230 may be designed by increasing the number of CMOS inverters, which is not limited herein.

Fig. 8 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention.

Fig. 8 is a circuit diagram of the read circuit of fig. 1, to which a feedback control module 240 is added.

As shown in fig. 8, the feedback control module 240 includes a clamp circuit. The clamp circuit may clamp the bit line BL/BLB to limit the lowest voltage of the bit line. The clamp circuit includes: a first NMOS transistor (N6) and a second NMOS transistor (N7). The source electrode of the first NMOS tube is connected with the bit line; the source electrode of the second NMOS tube is connected with the bit line; the grid electrodes of the first NMOS tube and the second NMOS tube are connected together; the drains of the first and second NMOS transistors are commonly connected to a third potential (e.g., VLCAMP in fig. 8, which may be a power supply voltage). When the voltage of the bit line BL is lower than the clamp control voltage VCEN and the threshold voltage VTH of the first NMOS transistor (i.e., VCEN-VTH), the first NMOS transistor will conduct to pull up the voltage of the bit line BL to VCEN-VTH. When the voltage of the bit line BLB is lower than the clamp control voltage VCEN and the threshold voltage VTH (i.e., VCEN-VTH) of the second NMOS transistor, the second NMOS transistor will conduct to pull up the voltage of the bit line BL to VCEN-VTH. Therefore, the feedback control module 240 may turn on the first NMOS transistor (N6) and the second NMOS transistor (N7) through the clamp circuit to pull up the voltage of the bit line BL/BLB. In some embodiments, the feedback control module 230 may be designed differently by designing different clamping circuits, which is not limited herein.

Fig. 9 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention.

Fig. 9 is a feedback control block 310 formed by adding the clamping circuit of fig. 8 to the feedback control block 210 of fig. 5. The feedback control module 310 can adjust the charging speed of the bit line BL/BLB according to whether the PMOS transistor is turned on or not, and can also control the lowest voltage of the bit line BL/BLB through the clamp circuit. By adding a clamp circuit on the basis of FIG. 5, the charging speed of the bit line BL/BLB can be adjusted, and the lowest voltage of the bit line can be limited.

Fig. 10 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention.

Fig. 10 is a feedback control block 320 formed by adding the clamp circuit of fig. 8 to the feedback control block 220 of fig. 6. The feedback control module 320 can adjust the discharging speed of the bit line BL/BLB according to whether the NMOS transistor is turned on or not, and can also control the lowest voltage of the bit line BL/BLB through the clamp circuit. By adding a clamp circuit on the basis of FIG. 6, the discharge speed of the bit line BL/BLB can be adjusted, and the lowest voltage of the bit line can be limited.

Fig. 11 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention.

Fig. 11 is a feedback control block 330 formed by adding the clamp circuit of fig. 8 to the feedback control block 230 of fig. 7. The feedback control module 310 can adjust the charging and/or discharging speed of the bit line BL/BLB through the CMOS inverter, and can control the lowest voltage of the bit line BL/BLB through the clamping circuit. By adding a clamp circuit on the basis of FIG. 7, the charging and discharging speed of the bit line BL/BLB can be adjusted, and the lowest voltage of the bit line can be limited.

Fig. 12 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention.

As shown in fig. 12, the amplifier module 130 is connected to a feedback control module 340. The feedback control module 340 may control relevant parameters of the amplifier module 130 based on the reading result of at least one previous reading cycle to control the data reading process of the current reading cycle. For example, when the voltage difference of the bit line BL/BLB inputted to the amplifier module 130 is too low, the feedback control module 340 may adjust a part of the parameters of the amplifier module 130 to increase the voltage difference of the bit line BL/BLB, thereby ensuring that the amplifier module 130 can correctly read out the data in the memory cell.

Fig. 13 is a circuit diagram of a feedback control module of a read circuit of a memory according to another exemplary embodiment of the present invention.

As shown in fig. 13, the feedback control module 350 is connected to the input node of the amplifier module 130 through capacitors (C1, C2). The feedback control module 350 may control a voltage of the input nodes (DL, DLB) of the amplifier module 130 based on the read result of at least one previous read cycle to control a data read process of the current read cycle. When the voltage difference of the bit line BL/BLB is too low, the feedback control module 350 may adjust the voltage of the input node (DL, DLB) of the amplifier module 130, and increase the voltage difference of the input node (DL, DLB), thereby ensuring that the amplifier module 130 can correctly read the data in the memory cell.

FIG. 14 is a timing diagram for reading data of a memory cell according to the reading circuit of FIG. 1.

As shown in fig. 14, the read cycle includes charge and discharge phases; in the discharging stage, the amplifier module is enabled, and the data stored in the storage unit can be read; when the word line WL (0) is enabled and the amplifier is enabled, the data in the memory cells controlled by the word line WL (0) can be read (t 13-t 14); after the last reading period is finished, the pre-charging module needs to pre-charge the bit line BL (at the stage of t 14-t 15) to enable the potential of the bit line BLB to reach a high potential, and the potential of the bit line BLB does not reach a sufficiently high potential due to too low charging speed; when reading the data of the next memory cell, in the amplifier module enabling stage (t 16-t 17), the voltage difference between the bit lines BL and BLB is Δ V1, and since the voltage difference is too small, a misreading occurs, as shown by the dashed line box in the figure, Q/QB should be flipped, but not flipped, and a misreading occurs.

Fig. 15 is a schematic diagram of a read circuit of a memory according to an exemplary embodiment of the present invention.

Fig. 16 is a timing diagram of a read circuit reading data of a memory cell according to an exemplary embodiment of the invention.

For the purpose of describing the reading circuit and method of the memory of the present invention, fig. 15 is an exemplary reading circuit of the memory. The read circuit includes a precharge module 410, a plurality of memory cells 420-1, 420-2, …, 420-n, an amplifier module 430, a feedback control module 440, and the like. Feedback control 440 may control the read process of the memory cell currently to be read based on the read result of the previous at least one read cycle. For example, when the result Q (1)/QB (1) of the previous memory cell 420-1 is read; the feedback control module 440 may control the charging and discharging processes of the bit line BL/BLB based on Q (1)/QB (1), such that when the next memory cell 420-2 is read, the voltage difference of the bit line BL/BLB may be made large enough for the amplifier module 440 to correctly read the result Q (2)/QB (2) of the memory cell 420-2. Fig. 16 is an exemplary timing diagram based on the read circuit of fig. 15. As shown in FIG. 16, after the reading of the previous memory cell 420-1 is finished, the precharge module 410 needs to charge the bit line (stages t 24-t 25), and compared to the stages t 14-t 15 in FIG. 14, the feedback control module 440 is added to increase the charging speed of the bit line, i.e., the bit line BLB can reach a higher level in the same time; when the next memory cell 420-2 is read (at stages t 26-t 27), the voltage difference between the bit lines BL/BLB is Δ V2 (greater than Δ V1 in FIG. 14), the read result Q/QB flips, and the data of the memory cell 420-2 is correctly read.

It should be noted that the above is only a schematic diagram of an exemplary read circuit and a read process of the present invention, and different read circuits can also be implemented by connecting, combining, etc. the above different circuits. It will be appreciated by those skilled in the art that, given the teachings of the present system, any combination of modules or sub-system configurations may be used to connect to other modules without departing from such teachings.

It is obvious to a person skilled in the art that the invention is not restricted to details of the above-described exemplary embodiments, but that it can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be implemented by one element. The terms first, second, etc. are used to denote names, but not any particular order.

Claims

1. A read circuit for a memory, comprising:

the device comprises a pre-charging module, a storage unit and an amplifier module;

in the pre-charging module or the amplifier module, the data reading process of the current reading period is controlled through the reading result of at least one reading period, so that the accuracy of data reading is improved.

2. The reading circuit of the memory according to claim 1, wherein in the precharging module, the bit line charging and discharging process is controlled by the reading result of at least one previous reading cycle, so as to control the data reading process of the current cycle.

3. A read circuit of a memory according to claim 2, wherein the bit line is connected to a pull-up branch controlled by the read result of at least one previous read cycle for charging the bit line to adjust the charging speed of the bit line in the current read cycle.

4. The reading circuit of the memory according to claim 3, wherein the bit lines are further connected to a charging tube controlled by a preset control voltage for commonly charging the bit lines.

5. A reading circuit of a memory according to claim 2, wherein the bit line is connected to a pull-down branch controlled by a read result of at least one previous reading cycle for discharging the bit line to adjust a discharging speed of the bit line in a current cycle.

6. The read circuit of the memory of claim 2, further comprising: a clamp circuit; the bit line is connected with the clamping circuit and used for clamping the bit line so as to limit the lowest voltage of the bit line.

7. The reading circuit of the memory according to claim 6, wherein the clamp circuit comprises a first NMOS transistor and a second NMOS transistor;

the source electrode of the first NMOS tube is connected with a first bit line in the bit lines;

the source electrode of the second NMOS tube is connected with a second bit line in the bit lines;

the grid electrodes of the first NMOS tube and the second NMOS tube are connected to a clamping control voltage together;

the drain electrodes of the first NMOS tube and the second NMOS tube are connected to a third potential together;

when the voltage of the first bit line is lower than the difference between the clamp control voltage and the threshold voltage of the first NMOS transistor, the first NMOS transistor is conducted to pull up the voltage of the first bit line to the difference between the clamp control voltage and the threshold voltage of the first NMOS transistor;

when the voltage of the second bit line is lower than the difference value of the clamp control voltage and the threshold voltage of the second NMOS transistor, the second NMOS transistor is conducted to pull up the voltage of the second bit line to the difference value of the clamp control voltage and the threshold voltage of the second NMOS transistor.

8. The reading circuit of the memory according to claim 1, wherein the amplifier module is connected to a feedback control module controlled by the reading result of at least one previous reading cycle, for controlling the data reading process of the current cycle.

9. The read circuit of claim 8, wherein the feedback control module controlled by the read result is connected to the input node of the amplifier module through a capacitor to control the voltage of the input node of the amplifier module.

10. A read circuit for a memory, comprising:

the memory comprises a precharge module, a bit line, a plurality of memory cells, an amplifier module and a feedback control module;

the feedback control module is suitable for controlling the data reading process of the current reading period based on the reading result of at least one previous reading period so as to improve the accuracy of data reading.

11. A read circuit for a memory as claimed in claim 10, wherein the read result further comprises a read address.

12. The reading circuit of the memory according to claim 10, wherein the feedback control module is further adapted to control the charging and discharging processes of the bit line based on the reading result of at least one previous reading cycle, so as to control the data reading process of the current reading cycle.

13. The reading circuit of claim 10, wherein the feedback control module is further adapted to control the speed and/or time of charging and discharging the bit line in a current reading cycle based on the reading result of at least one previous reading cycle.

14. The reading circuit of the memory according to claim 10, wherein the feedback control module comprises at least two PMOS transistors;

the source electrode of each PMOS tube is connected with a power supply in the pre-charging module;

the drain electrode of each PMOS tube is connected with the bit line;

the pre-charge module charges the bit line through the at least two PMOS tubes;

the feedback control module is further adapted to control the speed of charging the bit line through the at least two PMOS tubes based on the read result of the previous at least one read cycle.

15. The reading circuit of the memory according to claim 10, wherein the feedback control module comprises at least two NMOS transistors;

the drain electrode of each NMOS tube is connected with the bit line;

the source electrode of each NMOS tube is connected to a first potential in common;

the feedback control module is further adapted to control the speed of discharging the bit line through the at least two NMOS transistors based on the read result of the previous at least one read cycle.

16. The read circuit of the memory according to claim 10, wherein the feedback control module comprises at least two CMOS inverters;

the source electrode of a PMOS tube in each CMOS phase inverter is connected with the power supply in the pre-charging module;

the drain electrodes of the PMOS tube and the NMOS tube in each CMOS phase inverter are connected with the bit line;

the source electrodes of the NMOS tubes in each CMOS phase inverter are connected to a second potential in common;

the feedback control module is further adapted to control a speed of charging and discharging the bit line through the at least two CMOS inverters based on a read result of a previous at least one read cycle.

17. A read circuit for a memory according to any of claims 13 to 16, wherein the feedback control module comprises: a clamp circuit;

the clamping circuit is adapted to clamp the bit line to limit a lowest voltage of the bit line.

18. The memory reading circuit according to claim 10, wherein the amplifier module is connected to the feedback control module;

the feedback control module is further adapted to control the relevant parameters of the amplifier module based on the reading result of at least one previous reading cycle to control the data reading process of the current reading cycle.

19. The memory read circuit of claim 18, wherein the feedback control module is connected to the input node of the amplifier module by a capacitor;

the feedback control module is further adapted to control the input node voltage of the amplifier module based on the read result of at least one previous read cycle to control the data read process of the current read cycle.