CN112863571A

CN112863571A - Near-threshold ultralow-leakage latch type memory unit and read-write control circuit thereof

Info

Publication number: CN112863571A
Application number: CN202110234522.8A
Authority: CN
Inventors: 单伟伟; 王涛
Original assignee: Southeast University
Current assignee: Southeast University
Priority date: 2021-03-03
Filing date: 2021-03-03
Publication date: 2021-05-28
Anticipated expiration: 2041-03-03
Also published as: CN112863571B

Abstract

The invention discloses a latch type memory unit with near threshold value and ultra-low electric leakage and a read-write control circuit thereof, comprising: decoder, control circuit, memory array, input drive circuit and output latch circuit. The decoder translates the input address signal into one-hot code with only one bit as high level; the control circuit generates a read-write control signal of the storage array according to the read-write enable signal, the system clock signal and the one-hot code output by the decoder; the storage array is composed of tristate Latch and is used for storing data; the input drive circuit is used for delaying and driving input data, so that the problem of data overlapping writing caused by clock deflection and time delay of the write enable control circuit is avoided; the output latch circuit latches the output of the memory array according to the read enable signal and the system clock signal. Compared with a common standard unit memory or a standard 6-pipe SRAM, the latch type memory unit and the read-write control circuit thereof can obviously reduce power consumption.

Description

Near-threshold ultralow-leakage latch type memory unit and read-write control circuit thereof

Technical Field

The invention relates to a near-threshold ultralow-leakage latch type memory unit and a read-write control circuit thereof, which realize a storage function similar to a standard SRAM by utilizing pure digital logic and belong to the technical field of basic electronic circuits.

Background

The memory is widely researched as a core component of an electronic system, the access speed and the bandwidth of the memory can often determine the performance of the whole system, and the memory access power consumption is often large in the total power consumption of the system. Currently, a Static Random Access Memory (SRAM) is generally used as a main-stream cache, and a 6-transistor unit is generally used as a one-bit storage unit, which has the advantages of small area and high integration level, but also has the problem of low yield under low voltage due to a common read-write path, and therefore, the SRAM often works in a high voltage domain, resulting in higher power consumption. On the other hand, many EDA manufacturers currently provide Memory Compiler tools to generate SRAMs according to specifications specified by users, but although it is convenient, the SRAMs generated under the constraints of small-capacity and irregular-shape specifications have the problems of large overhead of peripheral circuits, waste of capacity and the like.

In view of the above problems, research has been made on constructing a memory using a Latch (Latch) in a standard cell as a one-bit memory cell, which is called a standard cell memory, and compared with a standard 6-transistor SRAM, the standard cell memory has a better voltage scaling characteristic and can work well even at a lower voltage, so that it enjoys a power consumption bonus due to voltage reduction. On the one hand, however, in order to solve the problem that Latch as a level trigger component is sensitive to glitch, the standard cell memory needs to add a row of flip-flops with the same number as the width of a storage word at a data input end, and an output circuit of the standard cell memory needs a plurality of large fanin selector circuits, data of corresponding row cells are selected according to addresses to be output, and the read-write power consumption is obviously increased due to the peripheral circuits; on the other hand, such standard cell memories tend to connect the system clock signal to the Latch enable terminal through a cascade of Integrated Clock Gating (ICG) cells, so that the clock load is relatively large.

Disclosure of Invention

The purpose of the invention is as follows: in view of the above background deficiencies, the present invention provides a near-threshold ultralow-leakage latch-type memory cell and a read/write control circuit thereof, which are suitable for operation at a near-threshold voltage, can be flexibly customized, and can significantly reduce power consumption.

The technical scheme is as follows: the invention adopts the following technical scheme for realizing the aim of the invention:

a latch type memory unit with near threshold and ultra-low leakage and a read-write control circuit thereof comprise:

a decoder for translating an input address signal into a one-hot code having only one bit at a high level;

the control circuit generates a read-write control signal of the storage array according to the read-write enable signal, the system clock signal and the one-hot code output by the decoder;

the storage array is M multiplied by C, wherein M represents the row number of the storage array, C represents the column number of the storage array, and the tri-state Latch is used for storing data;

the input driving circuit delays and drives input data;

and an output latch circuit for latching the output of the memory array according to the read enable signal and the system clock signal.

Furthermore, the control circuit generates read-write control signals of the storage array according to the one-hot code signal WL [ M-1:0], the system clock signal CLK, the high-level read enable signal REN and the high-level write enable signal WEN decoded by the decoder, wherein the read-write control signals comprise a high-level read word line signal R [ M-1:0], a low-level read word line signal RB [ M-1:0], a high-level write word line signal W [ M-1:0] and a low-level write word line signal WB [ M-1:0 ]; the specific process is as follows: the system clock signal CLK obtains an inverted clock signal CLKn through a first inverter, the inverted clock signal CLKn and a high-level write enable signal WEN are used as input signals of the first AND gate, the first AND gate outputs an internal write enable signal wr, the internal write enable signal wr and a one-hot code signal WL [ M-1:0] output by a decoder, the 1 st bit WL [0] is connected to the input end of the first NAND gate, the output of the first NAND gate is connected to a low-level write enable port WB of each tri-state Latch in the first row of the memory array on one hand, namely a low-level write word line is driven, the output of the second inverter is connected to a second inverter, and the output of the second inverter is connected to a high-level write enable port W of each tri-state Latch in the first row of the memory array, namely a high-level; the high/low level write word line signal generating mechanism of the storage units of the other rows is similar to that of the first row; the high level read enable signal REN is directly connected with the 1 st bit WL [0] of the one-hot code signal WL [ M-1:0] output by the decoder to be connected with the input port of the second NAND gate, the output of the high level read enable signal REN is connected with the low level read enable port RB of each tri-state Latch in the first row of the memory array on one hand, namely, the low level read word line is driven, and the output of the third inverter is connected with the high level read enable port R of each tri-state Latch in the first row of the memory array on the other hand, namely, the high level read word line is driven; the high/low level read word line signal generation mechanism for the remaining rows of memory cells is similar to that for the first row.

Furthermore, the memory array is composed of a tristate Latch, and is composed of a write drive circuit, a Latch circuit and a read drive circuit, wherein the tristate Latch comprises 14 transistors in total, 7 PMOS tubes and 7 NMOS tubes in total, and the total number of the PMOS tubes and the NMOS tubes is 8, and the tristate Latch is respectively a data input port D, a high-level write enable port W, a low-level write enable port WB, a high-level read enable port R, a low-level read enable port RB and a data output port Q.

Further, the write driving circuit is a first tri-state gate formed by a first transistor, a second transistor and a fourth transistor, and the specific structure is as follows: the source electrode of the first transistor is connected with a power supply, the grid electrode of the first transistor is connected with a data input port D, the drain electrode of the first transistor is connected with the source electrode of the third transistor, the source electrode of the second transistor is connected with the ground, the grid electrode of the first transistor is connected with the data input port D, the drain electrode of the first transistor is connected with the source electrode of the fourth transistor, the source electrode of the third transistor is connected with the drain electrode of the first transistor, the grid electrode of the first transistor is connected with a low-level write enable port WB, the drain electrode of the first transistor is connected with the drain electrode of the fourth transistor, the source electrode of; under the condition that W is 1 and WB is 0, the first tri-state gate is equivalent to an inverter, and inverted data of the data output port D is transmitted to the drain connection point of the third transistor and the fourth transistor; under the condition that W is 0 and WB is 1, the first tri-state gate outputs a high impedance state; the control logic does not allow other combinations of W and WB to occur.

Further, the latch circuit is composed of a fifth transistor to a tenth transistor, and the specific structure is as follows: a source of the fifth transistor is connected with the power supply, a gate is connected with drains of the third transistor and the fourth transistor, a drain is connected with a drain of the sixth transistor, a source of the sixth transistor is connected with the ground, a gate is connected with drains of the third transistor and the fourth transistor, a drain is connected with a drain of the fifth transistor, a source of the seventh transistor is connected with the power supply, a gate is connected with drains of the fifth transistor and the sixth transistor, a drain is connected with a source of the ninth transistor, a source of the eighth transistor is connected with the ground, a gate is connected with drains of the fifth transistor and the sixth transistor, a drain is connected with a source of the tenth transistor, a source of the ninth transistor is connected with a drain of the seventh transistor, a gate is connected with the high-level write enable port W, a drain is connected with a drain of the tenth transistor, a source of the tenth transistor is connected with a drain of the eighth transistor, the drain electrode is connected with the drain electrode of the ninth transistor; the fifth transistor and the sixth transistor form an inverter, and the seventh transistor to the tenth transistor form a second tri-state gate; under the condition that W is 1 and WB is 0, the tri-state gate outputs a high impedance state, a feedback loop formed by the tri-state gate and the inverter is broken, and the data of the node N1 is driven by the first tri-state gate only; under the condition that W is 0 and WB is 1, a feedback loop formed by the inverter is closed, and input data is latched to an N2 node; the control logic does not allow other combinations of W and WB to occur.

Further, the read driving circuit is a third tri-state gate formed by eleventh to fourteenth transistors, and the specific structure is as follows: the source electrode of the eleventh transistor is connected with a power supply, the grid electrode of the eleventh transistor is connected with the drain electrodes of the ninth transistor and the tenth transistor, the drain electrode of the eleventh transistor is connected with the source electrode of the thirteenth transistor, the source electrode of the twelfth transistor is connected with the ground, the grid electrode of the twelfth transistor is connected with the drain electrodes of the ninth transistor and the tenth transistor, the drain electrode of the fourteenth transistor is connected with the source electrode of the fourteenth transistor, the source electrode of the thirteenth transistor is connected with the drain electrode of the eleventh transistor, the grid electrode of the thirteenth transistor is connected with the low-level read enable port RB, the drain electrode of the thirteenth transistor is connected with the data output port Q, the source electrode; under the condition that R is 1 and RB is 0, the data latched by the latch circuit is transmitted to the data output port Q; under the conditions that R is 0 and RB is 1, outputting a high-resistance state; the control logic does not allow other combinations of R and RB to occur.

Furthermore, in the input driving circuit, after input data is delayed by the delay unit, the input driving circuit is connected with each driving unit so as to drive each column of writing bit lines; the delay value of the delay unit is determined by referring to the clock skew and the delay of the write enable control circuit.

Has the advantages that: by adopting the technical scheme, the invention has the following beneficial effects:

1) the invention customizes the low-leakage tri-state Latch as a basic 1-bit memory cell, and has two advantages compared with a standard 6-tube SRAM cell provided by a process manufacturer: firstly, the invention can work under lower voltage (near threshold region), thereby working together with the main digital circuit under low voltage to obtain lower power consumption; secondly, the invention adopts a multi-tube serial stacked structure and a transistor with an ultrahigh threshold value, thereby greatly reducing the leakage current;

2) according to the invention, the inverted signal of the clock is used as the control signal in the write control circuit, so that the problem of data miswriting caused by the fact that burrs in a decoding stage are transmitted to the write enable port of the tristate Latch is avoided, and compared with the scheme that a sampling register is added at the data input end of a common standard unit memory, the write power consumption and the electric leakage can be reduced;

3) the invention can directly connect the output ports of the tri-state memory units in different rows and columns to form the read bit line, and can save a large fan-in selector circuit and reduce the read power consumption and the electric leakage compared with the common standard unit memory.

Drawings

FIG. 1 is a schematic diagram of a tri-state Latch based memory circuit of the present invention;

FIG. 2 is a schematic diagram of a tri-state Latch according to the present invention;

FIG. 3 is a timing diagram illustrating read/write control of the memory circuit according to the present invention;

FIG. 4 is a diagram of a comparison of the tri-state Latch of the present invention with a conventional Latch and D flip-flop;

FIG. 5 shows a 128 × 32 memory embodiment of the present invention.

The figure shows that: decoder 1, control circuit 2, memory array 3, input drive circuit 4, output latch circuit 5.

Detailed Description

The technical solutions of the present invention will be described in detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the embodiments.

The latch type memory unit with the near threshold and the ultra-low leakage current and the read-write control circuit thereof comprise a decoder 1, a control circuit 2, a memory array 3, an input drive circuit 4 and an output latch circuit 5, wherein the memory scale is M multiplied by C, wherein M represents the row number of the memory array, and C represents the column number of the memory array, as shown in figure 1. The decoder receives the input address signal

Translate into one-hot code signal WL [ M-1:0] with only one bit as high level]As an input signal for the control circuit; the control circuit generates a read-write control signal of the storage array according to the read-write enabling signal, the system clock signal and the one-hot code output by the decoder; the storage array is composed of tristate Latch and is used for storing data; the input drive circuit is used for delaying and driving input data, so that the problem of data overlapping writing caused by clock deflection and a write enable control circuit is avoided; the output latch circuit latches the output of the memory array according to the read enable signal and the system clock signal.

The present invention adopts tristate Latch as a one-bit memory cell as shown in fig. 2, which is composed of a write drive circuit, a Latch circuit and a read drive circuit, wherein the tristate Latch comprises 14 transistors in total, 7 PMOS tubes and NMOS tubes respectively, and 8 ports in total are provided, and the tristate Latch is respectively a data input port D, a high-level write enable port W, a low-level write enable port WB, a high-level read enable port R, a low-level read enable port RB and a data output port Q.

The write driving circuit is a first tri-state gate Tsg1 formed by a first transistor M0 to a fourth transistor M3, and the specific structure is as follows: the source of the first transistor M0 is connected to the power supply, the gate is connected to the data input port D, the drain is connected to the source of the third transistor M2, the source of the second transistor M1 is connected to ground, the gate is connected to the data input port D, the drain is connected to the source of the fourth transistor M3, the source of the third transistor M2 is connected to the drain of the first transistor M0, the gate is connected to the low-level write enable port WB, the drain is connected to the drain of the fourth transistor M3, the source of the fourth transistor M3 is connected to the drain of the second transistor M1, the gate is connected to the high-level write enable port W, and the drain is connected to the drain of the third transistor M2; under the condition that W is 1 and WB is 0, the first tri-state gate Tsg1 is equivalent to an inverter, and the inverted data of the data output port D is transmitted to the drain connection points of the third transistor and the fourth transistor; under the condition that W is 0 and WB is 1, the first tri-state gate Tsg1 outputs a high impedance state; the control logic does not allow other combinations of W and WB to occur.

The latch circuit is composed of a fifth transistor M4 to a tenth transistor M9, and has a specific structure as follows: a source of the fifth transistor M4 is connected to the power supply, a gate is connected to the drains of the third transistor M2 and the fourth transistor M3, a drain is connected to the drain of the sixth transistor M5, a source of the sixth transistor M5 is connected to ground, a gate is connected to the drains of the third transistor M2 and the fourth transistor M3, a drain is connected to the drain of the fifth transistor M4, a source of the seventh transistor M6 is connected to the power supply, a gate is connected to the drains of the fifth transistor M4 and the sixth transistor M5, a drain is connected to the source of the ninth transistor M8, a source of the eighth transistor M7 is connected to ground, a gate is connected to the drains of the fifth transistor M4 and the sixth transistor M5, a drain is connected to the source of the tenth transistor M9, a source of the ninth transistor is connected to the drain of the seventh transistor M6, a gate is connected to the high-level write enable port W, a drain is connected to the tenth transistor M9, a drain of the tenth transistor M9 is connected to, a gate connected to the low-level write enable signal WB, and a drain connected to the drain of the ninth transistor M8; the fifth transistor M4 and the sixth transistor M5 form an inverter Inv1, and the seventh transistor M6 to the tenth transistor M9 form a second tri-state gate Tsg 2; under the condition that W is 1 and WB is 0, the tri-state gate outputs a high impedance state, and a feedback loop formed by the tri-state gate and the inverter is broken, so that the data of the node N1 is driven by only the first tri-state gate Tsg 1; under the condition that W is 0 and WB is 1, a feedback loop formed by the inverter is closed, and input data is latched to an N2 node; the control logic does not allow other combinations of W and WB to occur.

The read driving circuit is a third tri-state gate Tsg3 formed by an eleventh transistor M10 to a fourteenth transistor M13, and the specific structure is as follows: the source of the eleventh transistor M10 is connected to the power supply, the gate is connected to the drains of the ninth transistor M8 and the tenth transistor M9, the drain is connected to the source of the thirteenth transistor M12, the source of the twelfth transistor M11 is connected to ground, the gate is connected to the drains of the ninth transistor M8 and the tenth transistor M9, the drain is connected to the source of the fourteenth transistor M13, the source of the thirteenth transistor M12 is connected to the drain of the eleventh transistor M10, the gate is connected to the low-level read enable port RB, the drain is connected to the data output port Q, the source of the fourteenth transistor M13 is connected to the drain of the twelfth transistor M11, the gate is connected to the high-level read enable port R, and the drain is connected to the data output port Q; under the condition that R is 1 and RB is 0, the data latched by the latch circuit is transmitted to the data output port Q; under the conditions that R is 0 and RB is 1, outputting a high-resistance state; the control logic does not allow other combinations of R and RB to occur.

As can be seen from the above, the entire tri-state Latch is composed of three tri-state gates and one inverter, all transistors adopt an extra-high voltage Threshold (EHVT) transistor to reduce the leakage, and the stacked structure of the multiple transistors in series helps to reduce the leakage power consumption of the cell.

And (3) obtaining a tristate Latch layout according to the width-length ratio size shown in the table 1 by using a Virtuoso layout drawing tool under the TSMC28nm process. The comparison of the tri-state Latch and the standard Latch and D trigger related indexes in the process library under the working conditions of TT process corner, 0.5V voltage, 25 ℃ and 40kHz is shown in FIG. 4. It can be seen that the area of the tri-state Latch is slightly smaller than that of the Latch, and is about half of that of the D flip-flop, the leakage power consumption is only about one third of that of the Latch, and the dynamic power consumption is about one fourth of that of the Latch.

TABLE 1 Tri-state Latch respective transistor sizes

Transistor with a metal gate electrode	Width/length (nm)	Transistor with a metal gate electrode	Width/length (nm)
				M0	110/40	M6	110/40
M1	110/40	M7	110/40
				M2	110/40	M8	110/40
M3	110/40	M9	110/40
				M4	200/40	M10	110/40
M5	200/40	M11	110/40

The structure of an embodiment of a 128 × 32 memory formed by the tri-state Latch as a one-bit memory cell is shown in fig. 5, and the embodiment is composed of a decoder 1, a control circuit 2, a memory array 3, an input driving circuit 4 and an output Latch circuit 5, the memory size is 128 × 32, and the embodiment has 5 input ports and1 output port, namely, a system clock signal CLK input port, a high-level write enable signal WEN input port, a high-level read enable signal REN port, a data signal Din input port, an address signal Addr input port and a data Dout output port. The functions of each part are as follows:

the decoder translates the input address Addr [6:0] into a one-hot signal WL [127:0] with only one bit high, which is used as the input signal for the control circuit.

The control circuit generates read-write control signals of the memory array according to the one-hot code signals WL [127:0] decoded by the decoder, the system clock signal CLK, the high-level read enable signal REN and the high-level write enable signal WEN: high read word line signals R [127:0], low read word line signals RB [127:0], high write word line signals W [127:0], and low write word line signals WB [127-1:0 ]. The system clock signal CLK obtains an inverted clock signal CLKn through a first inverter I1, the inverted clock signal CLKn AND a high-level write enable signal WEN are used as input signals of a first AND gate AND1, the first AND gate outputs an internal write enable signal wr, the internal write enable signal wr AND a one-hot code signal WL [127:0] 1 bit WL [0] output by a decoder are connected to the input end of a first NAND gate ND1, the output of the first NAND gate is connected to a low-level write enable port WB of each tri-state Latch in a first row of the memory array on one hand, namely a low-level write bit line is driven, the output of the first NAND gate ND1 is connected to a second inverter I2 on the other hand, AND the output of a second inverter I2 is connected to a high-level write enable port W of each tri-state Latch in the first row of the memory array. The high/low write word line signal generation mechanism for the remaining rows of memory cells is similar to that for the first row. It can be seen from the above circuit connection relationship that, during data write operation, the high level stage of the clock only performs decoding, and the tristate Latch is not really opened, and only in the low level stage of the clock, the decoding result is really propagated to the write enable port of the tristate Latch. For data reading, because sampling is finally performed through the output latch circuit, the glitch output does not need to be considered. The high level read enable signal REN is directly connected with the 1 st bit WL [0] of the one-hot code signal WL [127:0] output by the decoder to be connected to the input port of the second NAND gate, the output of the high level read enable signal REN is connected to the low level read enable port RB of each tri-state Latch in the first row of the memory array on the one hand, namely, the low level read word line is driven, and is connected to the third inverter I3 on the other hand, the output of the third inverter I3 is connected to the high level read enable port R of each tri-state Latch in the first row of the memory array, namely, the high level read word line is driven. The high/low level read word line signal generation mechanism for the remaining rows of memory cells is similar to that for the first row.

The memory array is composed of 128 multiplied by 32 tristate latches, the read-write enable ports of the same row of units are respectively connected to form a read-write line and a write-write line, and the read-write line is controlled by a control circuit; in order to reduce the capacitance of the read-write bit lines, the bit lines are partitioned, and read-write data ports of the cells in the same column of the 1 st to 32 th rows, the 33 st to 64 th rows, the 65 th to 96 th rows and the 97 th to 128 th rows are respectively connected to form read-bit lines RBL0[31:0] -RBL3[31:0] and write-bit lines WBL0[31:0] -WBL3[31:0], wherein the write-bit lines are driven by an input driving circuit, and the read-bit lines are used as input data signals of an output latch circuit. In a standard unit memory based on the common Latch, read ports of memory cells in different rows need to be connected to a data input port of a large fan-in selector, and a read address signal is used as a selection signal to select a corresponding memory word from memory words in different rows.

The input driving circuits have 3 functions, one of which is to delay input data, so that the problem of data coverage and writing caused by clock deflection, time delay of a write enable control circuit and the like can be avoided; secondly, the writing bit line capacitor is driven; third, data is driven to one of the write bit lines WBL0-WBL3 according to the high bit address Addr [6:5] selection. Thus, the input data signals Din [31:0] are first coupled to the input ports of delay cells D1, the output ports thereof are coupled to the inputs of C drivers (B [0] -B [31]), and the outputs of the drivers drive the column bitlines, respectively.

The output latch circuit is composed of an integrated gate control unit, C D triggers and C4 input selectors, and mainly carries out sampling latch on the read bit line data selected by the high-bit address Addr [6:5] under the condition that the read enable is effective. And each column of reading bit lines are respectively connected with the data input ports of the D flip-flops, the clock ports of the flip-flops are connected with the output of the clock gating unit, and the output of the flip-flops is used as the output of the final memory. The clock input port of the integrated gating unit is connected to a system clock signal CLK, a control signal is connected to a high-level read enable signal REN, and when the read is effective, the system clock signal is transmitted to the clock end of each trigger; when a read is inactive, the clock signal is gated, thereby reducing the dynamic power consumption of the output latch circuit.

The timing of the memory is shown in fig. 3. In the first clock period T1, the address input is 0, the data input is D0, and the high write enable signal WEN is pulled high, i.e., data D0 is written to the row with address 0, i.e., the 1 st row of memory cells. As can be seen from the figure, the write enable signal W [0] of the memory cell in row 1 is actually pulled high in the negative level phase of the clock, AND due to the clock skew AND the delay of the first inverter I1, the first AND gate AND1, the second NAND gate ND2, the third inverter I3, etc. in the write control circuit, the high level pulse width of W [0] is not completely aligned with the clock signal, but has a time lag of t1, which may cause the problem that the write-after data overwrites the write-before data when the write operation is continuously performed, as will be analyzed in detail below. In the second clock period T2, the address input is 1, the data input is D1, and the high write enable signal WEN remains high, i.e., the data D1 continues to be written into the row with the address of 1, i.e., the row 2 memory cells. As previously described, the write enable signal W [0] for the first row of memory cells does not immediately return low for the instant of the clock rising edge, which has a time lag of t1 with respect to the clock rising edge, and a more extreme case is where the data input port has updated data from D0 to D1 after the clock rising edge, which results in data D1 being written into the first row of memory cells, overwriting the previously written D0. To solve this problem, the present invention connects the signal Din _ delay after the input data signal Din is delayed to the driver to drive the memory array write bit lines, and this delay should be larger than the sum of the clock skew and the delay of the write enable control circuit. In the third clock cycle T3, the address input becomes 0, and the high-level write enable signal WEN returns to low level, the high-level read enable signal REN is pulled high, i.e. data of the row with address 0, i.e. the 1 st row of memory cells, is read, and in the next clock cycle T4, data is read out to the Dout port.

For comparison with the 128 × 32 Memory circuit of this embodiment, a Memory circuit of the same size composed of a standard 6-transistor SRAM was produced by the Memory Compiler tool provided by ARM, and the minimum operating voltage thereof was 0.72V, and a Memory of the same size was constructed by a conventional method using the standard Latch provided in the process library. In order to take account of speed and leakage power consumption, for a standard cell memory and the invention, the memory cell adopts an extremely high Threshold EHVT transistor, and the peripheral decoding and other circuits adopt a Regular Threshold (RVT) transistor. The comparison conditions of the area, the total power consumption and the leakage power consumption of the three implementation modes under the working conditions of TT process angle, 25 ℃ and 10MHz are shown in Table 2, although the tristate Latch of the invention has larger area than the 6-tube unit of the standard SRAM, the whole area of the memory is smaller than that of the standard SRAM, and the reason is that the peripheral circuit is simpler; in terms of power consumption, the total power consumption of the invention is about one fourth of that of a standard unit memory, and the leakage power consumption is only about one seventh of that of the standard unit memory.

TABLE 2 comparison of this example with SRAM and standard cell memory area and power consumption

	Area (um)²)	Power consumption (uW)	Creepage power consumption (uW)
				SRAM(tt0p72v25c，10MHz)	5650	27.98	1.753
Standard cell memory (tt0p5v25c, 10MHz)	6184	2.33	0.688
				The invention (tt0p5v25c, 10MHz)	4113	0.605	0.102

The above are merely preferred embodiments of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A latch type memory unit with near threshold and ultra-low leakage current and a read-write control circuit thereof are characterized by comprising:

a decoder (1) for translating an input address signal into a one-hot code having only one bit at a high level;

the control circuit (2) generates a read-write control signal of the storage array according to the read-write enable signal, the system clock signal and the one-hot code output by the decoder;

the storage array (3) is M multiplied by C in storage scale, wherein M represents the row number of the storage array, C represents the column number of the storage array, and the tri-state Latch is used for storing data;

an input drive circuit (4) for delaying and driving input data;

an output latch circuit (5) latches the output of the memory array based on the read enable signal and the system clock signal.

2. The latch-type memory cell and its read/write control circuit with near-threshold ultra-low leakage as claimed in claim 1, wherein the control circuit (2) generates the read/write control signals of the memory array including a high-level read word line signal R [ M-1:0], a low-level read word line signal RB [ M-1:0], a high-level write word line signal W [ M-1:0], and a low-level write word line signal WB [ M-1:0] according to the one-hot code signal WL [ M-1:0], the system clock signal CLK, the high-level read enable signal REN, and the high-level write enable signal WEN decoded by the decoder; the specific process is as follows: the system clock signal CLK obtains an inverted clock signal CLKn through a first inverter (I1), the inverted clock signal CLKn AND a high-level write enable signal WEN are used as input signals of a first AND gate (AND1), the first AND gate outputs an internal write enable signal wr, the internal write enable signal wr AND a one-hot code signal WL [ M-1:0] 1 st bit WL [0] output by a decoder are connected to the input end of a first NAND gate (ND1), the output of the first NAND gate is connected to a low-level write enable port WB of each tristate Latch in a first row of the storage array on one hand, namely a low-level write word line is driven, AND is connected to a second inverter (I2) on the other hand, the output of the second inverter (I2) is connected to a high-level write tristate enable port W of each Latch in the first row of the storage array, namely a high-level write word line is driven; the high/low level write word line signal generating mechanism of the storage units of the other rows is similar to that of the first row; the high level read enable signal REN is directly connected with the 1 st bit WL [0] of the one-hot code signal WL [ M-1:0] output by the decoder, and is connected to the input port of the second NAND gate, the output of the high level read enable signal is connected to the low level read enable port RB of each tri-state Latch in the first row of the memory array on the one hand, namely, the low level read word line is driven, and is connected to the third inverter (I3) on the other hand, the output of the third inverter (I3) is connected to the high level read enable port R of each tri-state Latch in the first row of the memory array, namely, the high level read word line is driven; the high/low level read word line signal generation mechanism for the remaining rows of memory cells is similar to that for the first row.

3. The Latch-type memory cell with near-threshold and ultra-low leakage as claimed in claim 1, wherein said memory array (3) is composed of tri-state Latch, which is composed of write driver, Latch, and read driver, and comprises 14 transistors in total, and 7 PMOS transistors and NMOS transistors each having 8 ports, which are respectively a data input port D, a high-level write enable port W, a low-level write enable port WB, a high-level read enable port R, a low-level read enable port RB, and a data output port Q.

4. The latching memory cell and its read/write control circuit according to claim 3, wherein the write driving circuit is a first tri-state gate (Tsg1) formed by a first transistor (M0) to a fourth transistor (M3), and has the following specific structure: the source of the first transistor (M0) is connected with a power supply, the gate is connected with a data input port D, the drain is connected with the source of the third transistor (M2), the source of the second transistor (M1) is connected with the ground, the gate is connected with the data input port D, the drain is connected with the source of the fourth transistor (M3), the source of the third transistor (M2) is connected with the drain of the first transistor (M0), the gate is connected with a low-level write enable port WB, the drain is connected with the drain of the fourth transistor (M3), the source of the fourth transistor (M3) is connected with the drain of the second transistor (M1), the gate is connected with a high-level write enable port W, and the drain is connected with the drain of the third transistor (M2); under the condition that W is 1 and WB is 0, the first tri-state gate (Tsg1) is equivalent to an inverter, and inverted data of the data output port D is transmitted to drain connection points of the third transistor and the fourth transistor; a first tri-state gate (Tsg1) outputs a high impedance state under the condition that W is 0 and WB is 1; the control logic does not allow other combinations of W and WB to occur.

5. The memory cell of claim 3, wherein the latch circuit comprises a fifth transistor (M4) to a tenth transistor (M9), and is specifically configured as follows: a source of the fifth transistor (M4) is connected to a power supply, a gate is connected to drains of the third transistor (M2) and the fourth transistor (M3), a drain is connected to a drain of the sixth transistor (M5), a source of the sixth transistor (M5) is connected to ground, a gate is connected to drains of the third transistor (M2) and the fourth transistor (M3), a drain is connected to a drain of the fifth transistor (M4), a source of the seventh transistor (M6) is connected to the power supply, a gate is connected to drains of the fifth transistor (M4) and the sixth transistor (M5), a drain is connected to a source of the ninth transistor (M8), a source of the eighth transistor (M7) is connected to ground, a gate is connected to drains of the fifth transistor (M4) and the sixth transistor (M5), a drain is connected to a source of the tenth transistor (M9), a source of the ninth transistor is connected to a drain of the seventh transistor (M6), and a gate of the seventh transistor (M6) is connected to a high-level write enable port, a drain connected to the drain of the tenth transistor (M9), a source of the tenth transistor (M9) connected to the drain of the eighth transistor (M7), a gate connected to the low-level write enable signal WB, and a drain connected to the drain of the ninth transistor (M8); wherein the fifth transistor (M4) and the sixth transistor (M5) constitute an inverter (Inv1), and the seventh transistor (M6) to the tenth transistor (M9) constitute a second tri-state gate (Tsg 2); under the condition that W is 1 and WB is 0, the tri-state gate outputs a high impedance state, and a feedback loop formed by the tri-state gate and the inverter is broken, so that the data of the node N1 is driven by only the first tri-state gate (Tsg 1); under the condition that W is 0 and WB is 1, a feedback loop formed by the inverter is closed, and input data is latched to an N2 node; the control logic does not allow other combinations of W and WB to occur.

6. The latch-type memory cell and its read/write control circuit according to claim 3, wherein the read driving circuit is a third tri-state gate (Tsg3) formed by the eleventh to fourteenth transistors (M10 to M13), and has the following specific structure: a source of the eleventh transistor (M10) is connected to the power supply, a gate is connected to drains of the ninth transistor (M8) and the tenth transistor (M9), a drain is connected to the source of the thirteenth transistor (M12), a source of the twelfth transistor (M11) is connected to ground, a gate is connected to drains of the ninth transistor (M8) and the tenth transistor (M9), a drain is connected to the source of the fourteenth transistor (M13), a source of the thirteenth transistor (M12) is connected to the drain of the eleventh transistor (M10), a gate is connected to the low-level read enable port RB, a drain is connected to the data output port Q, a source of the fourteenth transistor (M13) is connected to the drain of the twelfth transistor (M11), a gate is connected to the high-level read enable port R, and a drain is connected to the data output port Q; under the condition that R is 1 and RB is 0, the data latched by the latch circuit is transmitted to the data output port Q; under the conditions that R is 0 and RB is 1, outputting a high-resistance state; the control logic does not allow other combinations of R and RB to occur.

7. The latch-type memory cell and its read-write control circuit of claim 1, characterized in that, in the input driving circuit (4), the input data is delayed by the delay unit (D1) and then connected to each driving unit to drive each column of write bit lines; the delay value of the delay unit (D1) is determined with reference to the clock skew and the delay of the write enable control circuit.