CN109525222A - A kind of single phase clock Double-edge D trigger - Google Patents
A kind of single phase clock Double-edge D trigger Download PDFInfo
- Publication number
- CN109525222A CN109525222A CN201811367937.7A CN201811367937A CN109525222A CN 109525222 A CN109525222 A CN 109525222A CN 201811367937 A CN201811367937 A CN 201811367937A CN 109525222 A CN109525222 A CN 109525222A
- Authority
- CN
- China
- Prior art keywords
- nmos tube
- edge
- grid
- tube
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3562—Bistable circuits of the master-slave type
Abstract
The invention discloses a kind of single phase clock Double-edge D triggers, comprising: rising edge trigger circuit 1,2, two phase inverters of failing edge trigger circuit and two input nand gate circuits 3.Under Cadence environment, using UMC 28nmCMOS technique, analog simulation is carried out to single phase clock Double-edge D trigger of the invention, simulation result shows that the circuit can be transmitted in the correct sampling that the rising edge and failing edge of clock signal complete data, there is fast response speed again, low energy consumption, which is delayed, to be accumulated.The single phase clock Double-edge D trigger circuit structure is simple, and transistor size is few, is a kind of Double-edge D trigger of good performance, high-speed, low-power consumption digital processing system in be with a wide range of applications.
Description
Technical field
The invention belongs to d type flip flop field, in particular to a kind of single phase clock Double-edge D trigger.
Background technique
In current VLSI Design field, reduce power consumption, improves data processing rate and pay close attention to
Field.Trigger is widely applied in digital integrated electronic circuit system, and trigger not only can control jumping for circuit work
Journey can also be used to realize frequency divider, counter and register etc..In digital display circuit, about 30% to 70% system
Power consumption be used to drive clock network and trigger, and the transmission time of trigger also limits the rate of data processing.Thus exist
Present high-speed, low-power consumption digital processing system in, seek a kind of low-power consumption, the trigger of high-speed has important meaning
Justice.
In various triggers, d type flip flop is the element most generally used.D type flip flop can be divided into single edging trigger (when
The rising edge or failing edge of clock trigger) and double edge trigger (rising edge and failing edge of clock carry out data sampling biography respectively
It is defeated).Compared with single edge D flip-flop, Double-edge D trigger may be implemented twice under the conditions of clock rate is consistent
Data processing amount, therefore the requirement of the high-speed of digital integrated electronic circuit development, low-power consumption can be better met.
As shown in figure 3, traditional failing edge d type flip flop is by phase inverter, cmos transmission gate etc., totally 16 transistors are constituted
(wherein phase inverter INV1 and INV2, cmos transmission gate TG1 and TG2 are made of two CMOS transistors).In Fig. 3, CLK table
Show clock signal, CLKB indicates the inverted signal of CLK, and when clock CLK effectively (it is low level that clock is jumped from high level), circuit can
The data D of input is transferred to output node Q (Q=D)；When clock CLK stops (clock is low level), circuit still can be with
The logic level of oneself is maintained in output node.The major defect of conventional D flip flop is that the capacitive load of clock signal is very big, this
The power consumption that will lead to clock network increases, while there is also signal reverse conductions to ask using the d type flip flop of cmos transmission gate realization
Topic, so that late-class circuit may influence the state of first order latch, causes register output error data.
Summary of the invention
The purpose of the present invention is to provide a kind of single phase clock Double-edge D triggers, to solve the above problems.
To achieve the above object, the invention adopts the following technical scheme:
A kind of single phase clock Double-edge D trigger, including rising edge trigger circuit (1), failing edge trigger circuit (2),
One phase inverter INV1, the second phase inverter INV2 and two input nand gate circuits (3)；Rising edge trigger circuit (1) with two input with
Not circuit (3) connection, failing edge trigger circuit (2) are connected to two input nand gate circuits (3) by the second phase inverter INV2；
Rising edge trigger circuit (1) connects the first phase inverter INV1.
Further, rising edge trigger circuit includes the first PMOS tube PM1, the second PMOS tube PM2, the first NMOS tube NM1
With the second NMOS tube NM2；The source electrode of first PMOS tube PM1 is connected with supply voltage Vdd, and grid is connected with clock signal clk, leakage
Pole is connected with the grid of the drain electrode of the first NMOS tube NM1 and the second NMOS tube NM2；The source electrode and electricity of second PMOS tube PM2
Source voltage Vdd is connected, and grid is connected with clock signal clk, the drain electrode of drain electrode and the second NMOS tube NM2, the 5th PMOS tube PM5's
The grid of grid and the 6th NMOS tube NM6 are connected；The source electrode of first NMOS tube NM1 is connected with ground wire Gnd, grid with
The output end of first phase inverter INV1 is connected；The source electrode of second NMOS tube NM2 is connected with ground wire Gnd.
Further, failing edge trigger circuit includes third PMOS tube PM3, the 4th PMOS tube PM4, third NMOS tube NM3
With the 4th NMOS tube NM4；The source electrode of third PMOS tube PM3 is connected with supply voltage Vdd, and grid is connected with input signal D, drain electrode
It is connected with the grid of the drain electrode of third NMOS tube NM3 and the 4th PMOS tube PM4；The source electrode and power supply of 4th PMOS tube PM4
Voltage Vdd is connected, and drain electrode is connected with the input terminal of the drain electrode of the 4th NMOS tube NM4 and the second phase inverter INV2；Third
The grid of NMOS tube NM3 is connected with clock signal clk, and source electrode is connected with ground wire Gnd；The grid of the third NMOS tube NM4 with
Clock signal clk is connected, and source electrode is connected with ground wire Gnd.
Further, two input nand gate circuits include the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 5th NMOS tube
NM5 and the 6th NMOS tube NM6；The source electrode of 5th PMOS tube PM5 is connected with supply voltage Vdd, grid and the second PMOS tube PM2's
Drain electrode, the drain electrode of the second NMOS tube NM2 are connected with the grid of the 6th NMOS tube NM6, the leakage of drain electrode and the 6th PMOS tube PM6
The drain electrode of pole, the 6th NMOS tube NM6 is connected with output end Q；The source electrode of 6th PMOS tube PM6 is connected with supply voltage Vdd,
Grid is connected with the output end of the grid of the 5th NMOS tube NM5 and the second phase inverter INV2；The source electrode of 5th NMOS tube NM5
It is connected with ground wire Gnd, drain electrode is connected with the source electrode of the 6th NMOS tube NM6.
Further, the input terminal of the first phase inverter INV1 is connected with input signal D, output end and the first NMOS tube NM1
Grid be connected；The input terminal of second phase inverter INV2 and the drain electrode of the 4th PMOS tube PM4 and the drain electrode of the 4th NMOS tube NM4 are equal
It is connected, output end is connected with the grid of the grid of the 5th NMOS tube NM5 and the 6th PMOS tube PM6.
Compared with prior art, the present invention has following technical effect:
The present invention is since edging trigger circuit is only made of 4 transistors, therefore the propagation delay of circuit is short, thus has fast
Response speed.Energy consumption delay product calculation formula is shown below:
EDP=Pavtp 2
P in formulaavIndicate the average power consumption that output signal is overturn every time.As can be seen from the above equation, energy consumption delay product EDP and electricity
Road propagation delay it is square directly proportional, be delayed product since the propagation delay of circuit is short, thus with low energy consumption.
Single phase clock Double-edge D trigger circuit structure of the invention is simple, and transistor size is few, is a kind of functional
Double-edge D trigger, high-speed, low-power consumption digital processing system in be with a wide range of applications.
Detailed description of the invention
Fig. 1 is the circuit diagram of single phase clock Double-edge D trigger of the present invention；
Fig. 2 is the logical simulation timing diagram of single phase clock Double-edge D trigger of the invention.
Fig. 3 is a kind of circuit diagram of traditional failing edge d type flip flop；
Specific embodiment
Below in conjunction with attached drawing, the present invention is further described:
The circuit diagram that Fig. 1 is single phase clock Double-edge D trigger described in the embodiment of the present invention is please referred to, described is bilateral
It include rising edge trigger circuit 1,2, two phase inverters of failing edge trigger circuit and two input nand gate circuits 3 along d type flip flop.
Referring to Fig. 1, the rising edge trigger circuit 1 includes: the first PMOS tube PM1, the second PMOS tube PM2, the first NMOS
Pipe NM1 and the second NMOS tube NM2.Wherein,
The source electrode of the first PMOS tube PM1 is connected with supply voltage Vdd, and grid is connected with clock signal clk, drain electrode with
The drain electrode of first NMOS tube NM1 is connected with the grid of the second NMOS tube NM2；The source electrode and power supply of the second PMOS tube PM2
Voltage Vdd is connected, and grid is connected with clock signal clk, drain electrode and the drain electrode of the second NMOS tube NM2, the grid of the 5th PMOS tube PM5
Pole is connected with the grid of the 6th NMOS tube NM6；The source electrode of the first NMOS tube NM1 is connected with ground wire Gnd, grid and first
The output of phase inverter INV1 is connected；The source electrode of the second NMOS tube NM2 is connected with ground wire Gnd.
Referring to Fig. 1, the failing edge trigger circuit 2 includes: third PMOS tube PM3, the 4th PMOS tube PM4, the 3rd NMOS
Pipe NM3 and the 4th NMOS tube NM4.Wherein,
The source electrode of the third PMOS tube PM3 is connected with supply voltage Vdd, and grid is connected with input signal D, drain electrode and the
The drain electrode of three NMOS tube NM3 is connected with the grid of the 4th PMOS tube PM4；Source electrode and the power supply electricity of the 4th PMOS tube PM4
Vdd is pressed to be connected, drain electrode is connected with the input terminal of the drain electrode of the 4th NMOS tube NM4 and the second phase inverter INV2；The third
The grid of NMOS tube NM3 is connected with clock signal clk, and source electrode is connected with ground wire Gnd；The grid of the third NMOS tube NM4 with
Clock signal clk is connected, and source electrode is connected with ground wire Gnd.
Referring to Fig. 1, the two input nand gates circuit 3 includes: the 5th PMOS tube PM5, the 6th PMOS tube
PM6, the 5th NMOS tube NM5 and the 6th NMOS tube NM6.Wherein,
The source electrode of the 5th PMOS tube PM5 is connected with supply voltage Vdd, the drain electrode of grid and the second PMOS tube PM2,
The drain electrode of two NMOS tube NM2 is connected with the grid of the 6th NMOS tube NM6, drain electrode and the drain electrode of the 6th PMOS tube PM6, the 6th
The drain electrode of NMOS tube NM6 is connected with output end Q；The source electrode of the 6th PMOS tube PM6 is connected with supply voltage Vdd, grid
It is connected with the output end of the grid of the 5th NMOS tube NM5 and the second phase inverter INV2；The source electrode of the 5th NMOS tube NM5 with
Ground wire Gnd is connected, and drain electrode is connected with the source electrode of the 6th NMOS tube NM6.
Referring to Fig. 1, the input terminal of the first phase inverter INV1 is connected with input signal D, output end and the first NMOS tube
The grid of NM1 is connected；The input terminal of the second phase inverter INV2 and drain electrode and the 4th NMOS tube NM4 of the 4th PMOS tube PM4
Drain electrode be connected, output end is connected with the grid of the grid of the 5th NMOS tube NM5 and the 6th PMOS tube PM6.
Next the working principle of single phase clock Double-edge D trigger of the present invention is described below:
First analyze rising edge clock trigger process, referring to Figure 1 in rising edge trigger circuit 1.Work as input signal
D1 is low level, when clock signal clk is low level, the first NMOS tube NM1 cut-off, and the first PMOS tube PM1 conducting, thus node
A is charged to high level.At this point, the second NMOS tube NM2 and the second PMOS tube PM2 conducting, through reasonable settings NM2 and PM2
Size, the charging of node B can be made to be greater than electric discharge, thus node B will be charged to high level.Work as clock signal clk
It is high level by low level jump, that is, when rising edge clock arrival, the first PMOS tube PM1 and the second PMOS tube PM2 will
Cut-off, node A are maintained as original high level, and the second NMOS tube NM2 conducting, it is low level that node B can be discharged by NM2
" 0 ", the low level of input signal D1 is properly transferred to output node B at this time.When input signal D1 is high level, clock signal
When CLK is low level, the first NMOS tube NM1 and the first PMOS tube PM1 are connected, through reasonable settings the size of NM1 and PM1,
The electric discharge of node A can be made to be greater than charging, thus node A can be discharged as low level " 0 ".At this point, the second NMOS tube NM2 is cut
Only, the second PMOS tube PM2 is connected, thus node B can be charged to high level by PM2.When clock signal clk is jumped by low level
Become high level, that is, when rising edge clock arrival, the first PMOS tube PM1 and the second PMOS tube PM2 will end, node A
It is maintained as original low level " 0 ", the second NMOS tube NM2 cut-off, so node B is maintained as original high level, at this time
The high level of input signal D1 is properly transferred to output node B.When clock signal clk be high level, the first PMOS tube PM1 and
Second PMOS tube PM2 cut-off, if input signal D1 is low level by high level jump, the first NMOS tube NM1 will end, node
A can maintain original low level " 0 ", then the second NMOS tube NM2 ends, node B can keep original high level.When clock is believed
Number CLK is high level, the first PMOS tube PM1 and the second PMOS tube PM2 cut-off, if input signal D1 is high electricity by low level jump
Flat, the first NMOS tube NM1 will be connected, and node A can be discharged to low level " 0 " by NM1, then the second NMOS tube NM2 ends,
Node B can keep original low level " 0 ".In conclusion rising edge trigger circuit 1 can correctly realize clock signal clk
Rising edge triggering, is properly transferred to output node B for input signal D1.When CLK is low level, output node B perseverance is height
Level, when CLK is high level, output node B not will receive the interference of input signal D1 change.
Then analyze clock falling edge trigger process, referring to Figure 1 in failing edge trigger circuit 2.As input signal D
For high level, when clock signal clk is high level, third NMOS tube NM3 conducting, third PMOS tube PM3 ends, thus node C
It is discharged to low level " 0 ".At this point, the 4th NMOS tube NM4 and the 4th PMOS tube PM4 conducting, through reasonable settings NM4 and
The size of PM4 can make the electric discharge of node F be greater than charging, thus node F will be discharged as low level " 0 " by NM4.
When clock signal clk is low level by high level jump, that is, clock falling edge arrives, third NMOS tube NM3 and the 4th
NMOS tube NM4 will end, and node C is maintained as original low level " 0 ", and the 4th PMOS tube PM4 conducting, node F can pass through
PM4 is charged as high level, and the high level of input signal D is properly transferred to output node F at this time.When input signal D is low electricity
It is flat, when clock signal clk is high level, third NMOS tube NM3 and third PMOS tube PM3 conducting, through reasonable settings NM3 and
The size of PM3 can make the charging of node C be greater than electric discharge, thus node C can be charged to high level.At this point, the 4th PMOS
Pipe PM4 cut-off, the 4th NMOS tube NM4 conducting, thus node F can be discharged to low level " 0 " by NM4.Work as clock signal clk
It is low level by high level jump, that is, when clock falling edge arrival, third NMOS tube NM3 and the 4th NMOS tube NM4 will
Shutdown, node C are maintained as original high level, the 4th PMOS tube PM4 cut-off, so node F is maintained as original low electricity
Flat " 0 ", the low level of input signal D is properly transferred to output node F at this time.When clock signal clk is low level, third
NMOS tube NM3 and the 4th NMOS tube NM4 cut-off, if input signal D is low level by high level jump, third PMOS tube PM3 will
It can be connected, node C can charge to high level by PM3, then the 4th PMOS tube PM4 ends, node F can keep original height electricity
It is flat.When clock signal clk is low level, third NMOS tube NM3 and the 4th NMOS tube NM4 cut-off, if input signal D is by low level
Jump is high level, and third PMOS tube PM3 will end, and node C can keep original high level, then the 4th PMOS tube PM4
Cut-off, node F can keep original low level " 0 ".In conclusion failing edge trigger circuit 2 can correctly realize that clock is believed
The triggering of number CLK failing edge, is properly transferred to output node F for input signal D.When CLK is high level, output node F is permanent
For low level " 0 ", when CLK is low level, output node F not will receive the interference of input signal D change.
Analysis to above-mentioned two circuit characteristic is it is found that rising edge trigger circuit 1 in clock pulses CLK is high period
Between, the level of output node B depends on the input signal D1 before the rising edge of clock pulses CLK, under required settling time
Numerical value, output node B will be charged to high level or be discharged to low level " 0 ", in clock pulses CLK between low period,
Output node B has the path for being connected to supply voltage Vdd, it will is charged to high level.Failing edge trigger circuit 2 is in clock
Between low period, the level of output node F depends on before the failing edge of clock pulses CLK pulse CLK, required when establishing
Between under input signal D numerical value, output node F will be charged to high level or be discharged to low level " 0 ", in clock pulses
For CLK between high period, output node F has the path for being connected to ground wire Gnd, it will is discharged to low level " 0 ".Therefore,
Two circuits are functionally complementary, and during clock pulses CLK is high level (low level), and output node F (B), which has, to be connected
It is grounded the path of Gnd (supply voltage Vdd).
Failing edge trigger circuit 2 is utilized when clock signal clk rising edge arrives using the characteristic of two above circuit
The characteristic that perseverance is 0 is exported when CLK is high level, so that the structure of rising edge trigger circuit 1 can be used as signal output；When
When clock signal CLK failing edge arrives, the characteristic that perseverance is 1 is exported when CLK is low level using rising edge trigger circuit 1, so that
The structure of failing edge trigger circuit 2 can be used as signal output, complete the function of double edge trigger.Double-edge D trigger circuit
Structure is as shown in Figure 1, combination export structure is two input nand gate circuits 3.It is electric for height by low level jump in clock pulses CLK
Usually, rising edge trigger circuit 1 realizes data sampling transmission, and circuit node F is by pre-arcing to low level " 0 ", by second
Phase inverter INV2 makes node E be high level, so that the output valve Q of NAND gate circuit 3 depends on the numerical value of node B.In clock
When pulse CLK by high level jump is low level, failing edge trigger circuit 2 realizes data sampling transmission, and circuit node B is pre-
High level is charged to, so that the output valve Q of NAND gate circuit 3 depends on the numerical value of node F.Finally, in order to enable output data
With input data polarity having the same, it is inserted into two phase inverters INV1 and INV2 in circuit.
In conclusion single phase clock Double-edge D trigger of the invention, is touched by rising edge d type flip flop circuit, failing edge
The combination of Power Generation Road, two phase inverters and two input nand gate circuits controls, and can distinguish in the rising edge and failing edge of clock
Output end is completed to transmit the correct sampling of input data.During clock level is stablized, output node not will receive input letter
The interference that number state changes realizes the Double-edge D trigger of single phase clock control.
Single phase clock Double-edge D trigger of the invention is realized using UMC 28nm CMOS technology.In Cadence ring
Under border, simulating, verifying is carried out to Double-edge D trigger, environment temperature is 27 DEG C, process corner TT, supply voltage 1.05V.
Fig. 3 is please referred to, Fig. 3 is the logical simulation timing of single phase clock Double-edge D trigger described in the embodiment of the present invention
Figure, wherein CLK is clock signal, and D is the signal of input, and B is the output signal of node B, and E is the output signal of node E, and Q is
The final output signal of Double-edge D trigger.From simulation result as can be seen that the output state of node B is in the upper of clock signal
It rises along jumping, the output state of node F is jumped in the failing edge of clock signal, finally
The state of output signal Q is jumped in rising edge and failing edge.During clock signal level is stablized, output
Signal Q not will receive the interference of status input signal change, and the logic function of entire trigger is correct, be that a single phase clock is double
Edge D flip-flop.
The time sequence parameter of 1 the simulation experiment result of table (using the circuit of Fig. 1 as simulation object)
The Irms and EDP of trigger under the different overturning rates of table 2 (using the circuit of Fig. 1 as simulation object)
Table 1 is the time sequence parameter of the simulation experiment result, as can be seen from the table, the bilateral edge of single phase clock of the invention
D type flip flop has outstanding performance.In rising edge triggering, maximum propagation delay only needs 14.71ps；It is triggered in failing edge
When, maximum propagation delay only needs 16.67ps.Table 2 is the power consumption assessment to circuit, is fixed in the voltage and simulation time of circuit
When, under different Data flipping rates, the rms current Irms and energy consumption of circuit are delayed product EDP as evaluation criteria.From table 2
In data can be seen that single phase clock Double-edge D trigger of the invention with very little energy consumption delay product, in Data flipping
When rate is 50%, EDP is only 443.89 (fJ.ps)；When Data flipping rate is 100%, EDP is only 246.27 (fJ.ps).
Single phase clock Double-edge D trigger of the invention can complete data in the rising edge and failing edge of clock signal
Correct sampling transmission, and there is fast response speed, low energy consumption is delayed product.The single phase clock Double-edge D trigger circuit
Structure is simple, and transistor size is few, is a kind of Double-edge D trigger of good performance, in high-speed, the digital processing of low-power consumption
It is with a wide range of applications in system.
Finally it is pointed out that the above embodiments explanation is not limitation of the present invention, only of the invention
A kind of feasible scheme, person skilled in the relevant technique in the spirit and principles in the present invention it is made modification, addition and
Replacement, all should be in protection scope of the present invention.
Claims (5)
1. a kind of single phase clock Double-edge D trigger, which is characterized in that including rising edge trigger circuit (1), failing edge triggering electricity
Road (2), the first phase inverter INV1, the second phase inverter INV2 and two input nand gate circuits (3)；Rising edge trigger circuit (1) with
The connection of two input nand gate circuits (3), failing edge trigger circuit (2) are connected to two input nand gates by the second phase inverter INV2
Circuit (3)；Rising edge trigger circuit (1) connects the first phase inverter INV1.
2. a kind of single phase clock Double-edge D trigger according to claim 1, which is characterized in that rising edge trigger circuit
Including the first PMOS tube PM1, the second PMOS tube PM2, the first NMOS tube NM1 and the second NMOS tube NM2；First PMOS tube PM1's
Source electrode is connected with supply voltage Vdd, and grid is connected with clock signal clk, the drain electrode and second of drain electrode and the first NMOS tube NM1
The grid of NMOS tube NM2 is connected；The source electrode of second PMOS tube PM2 is connected with supply voltage Vdd, grid and clock signal
CLK is connected, the drain electrode of drain electrode and the second NMOS tube NM2, the grid of the 5th PMOS tube PM5 and the grid of the 6th NMOS tube NM6
It is connected；The source electrode of first NMOS tube NM1 is connected with ground wire Gnd, and grid is connected with the output end of the first phase inverter INV1；The
The source electrode of two NMOS tube NM2 is connected with ground wire Gnd.
3. a kind of single phase clock Double-edge D trigger according to claim 1, which is characterized in that failing edge trigger circuit
Including third PMOS tube PM3, the 4th PMOS tube PM4, third NMOS tube NM3 and the 4th NMOS tube NM4；Third PMOS tube PM3's
Source electrode is connected with supply voltage Vdd, and grid is connected with input signal D, drain electrode and fourth PMOS of the drain electrode with third NMOS tube NM3
The grid of pipe PM4 is connected；The source electrode of 4th PMOS tube PM4 is connected with supply voltage Vdd, drain electrode and the 4th NMOS tube NM4
Drain electrode be connected with the input terminal of the second phase inverter INV2；The grid of third NMOS tube NM3 is connected with clock signal clk,
Source electrode is connected with ground wire Gnd；The grid of the third NMOS tube NM4 is connected with clock signal clk, and source electrode is connected with ground wire Gnd.
4. a kind of single phase clock Double-edge D trigger according to claim 1, which is characterized in that two input nand gates electricity
Road includes the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 5th NMOS tube NM5 and the 6th NMOS tube NM6；5th PMOS tube PM5
Source electrode be connected with supply voltage Vdd, the drain electrode of grid and the second PMOS tube PM2, the drain electrode and the 6th of the second NMOS tube NM2
The grid of NMOS tube NM6 is connected, drain electrode and the drain electrode of the 6th PMOS tube PM6, the drain electrode of the 6th NMOS tube NM6 and output end
Q is connected；The source electrode of 6th PMOS tube PM6 is connected with supply voltage Vdd, the grid and of grid and the 5th NMOS tube NM5
The output end of two phase inverter INV2 is connected；The source electrode of 5th NMOS tube NM5 is connected with ground wire Gnd, drain electrode and the 6th NMOS
The source electrode of pipe NM6 is connected.
5. a kind of single phase clock Double-edge D trigger according to claim 1, which is characterized in that the first phase inverter INV1
Input terminal be connected with input signal D, output end is connected with the grid of the first NMOS tube NM1；The input of second phase inverter INV2
End and the 4th PMOS tube PM4 drain and the drain electrode of the 4th NMOS tube NM4 is connected, output end and the 5th NMOS tube NM5's
The grid of grid and the 6th PMOS tube PM6 are connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811367937.7A CN109525222B (en) | 2018-11-16 | 2018-11-16 | Double-edge D trigger of single-phase clock |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811367937.7A CN109525222B (en) | 2018-11-16 | 2018-11-16 | Double-edge D trigger of single-phase clock |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109525222A true CN109525222A (en) | 2019-03-26 |
| CN109525222B CN109525222B (en) | 2022-11-04 |
Family
ID=65778373
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811367937.7A Active CN109525222B (en) | 2018-11-16 | 2018-11-16 | Double-edge D trigger of single-phase clock |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109525222B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110798184A (en) * | 2019-12-02 | 2020-02-14 | 深圳清华大学研究院 | Time delay circuit unit |
| CN114050807A (en) * | 2021-11-05 | 2022-02-15 | 安徽大学 | Master-slave trigger based on TFET |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020140481A1 (en) * | 2001-03-28 | 2002-10-03 | Tschanz James W. | Dual edge-triggered explicit pulse generator circuit |
| US20030226077A1 (en) * | 2002-05-28 | 2003-12-04 | International Business Machines Corporation | Low power level-sensitive scan mechanism |
| US20050189977A1 (en) * | 2004-03-01 | 2005-09-01 | Chung-Hui Chen | Double-edge-trigger flip-flop |
| CN1697320A (en) * | 2005-06-15 | 2005-11-16 | 清华大学 | Sensitive amplifier structured falling edge CMOS trigger |
| CN1702963A (en) * | 2005-06-09 | 2005-11-30 | 清华大学 | Synchronous enabled type condition presetting CMOS trigger |
| CN102723930A (en) * | 2012-06-29 | 2012-10-10 | 北京大学 | Double-edge D trigger |
| US20160173090A1 (en) * | 2014-12-16 | 2016-06-16 | Intel Corporation | Apparatus and method for detecting or repairing minimum delay errors |
-
2018
- 2018-11-16 CN CN201811367937.7A patent/CN109525222B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020140481A1 (en) * | 2001-03-28 | 2002-10-03 | Tschanz James W. | Dual edge-triggered explicit pulse generator circuit |
| US20030226077A1 (en) * | 2002-05-28 | 2003-12-04 | International Business Machines Corporation | Low power level-sensitive scan mechanism |
| US20050189977A1 (en) * | 2004-03-01 | 2005-09-01 | Chung-Hui Chen | Double-edge-trigger flip-flop |
| CN1702963A (en) * | 2005-06-09 | 2005-11-30 | 清华大学 | Synchronous enabled type condition presetting CMOS trigger |
| CN1697320A (en) * | 2005-06-15 | 2005-11-16 | 清华大学 | Sensitive amplifier structured falling edge CMOS trigger |
| CN102723930A (en) * | 2012-06-29 | 2012-10-10 | 北京大学 | Double-edge D trigger |
| US20160173090A1 (en) * | 2014-12-16 | 2016-06-16 | Intel Corporation | Apparatus and method for detecting or repairing minimum delay errors |
Non-Patent Citations (1)
| Title |
|---|
| 张璇等: "触发器的性能和功耗的分析与比较", 《现代电子技术》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110798184A (en) * | 2019-12-02 | 2020-02-14 | 深圳清华大学研究院 | Time delay circuit unit |
| CN110798184B (en) * | 2019-12-02 | 2023-02-10 | 深圳清华大学研究院 | Time delay circuit unit |
| CN114050807A (en) * | 2021-11-05 | 2022-02-15 | 安徽大学 | Master-slave trigger based on TFET |
| CN114050807B (en) * | 2021-11-05 | 2024-03-26 | 安徽大学 | Master-slave trigger based on TFET |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109525222B (en) | 2022-11-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102708816B (en) | Shift register, grid driving device and display device | |
| US20090295448A1 (en) | Radiation Hardened CMOS Master Latch With Redundant Clock Input Circuits and Design Structure Therefor | |
| CN102437836B (en) | Low-power-consumption pulse type D trigger | |
| CN102799211B (en) | Internal clock gating apparatus | |
| CN109379061A (en) | TSPC trigger with set function | |
| CN109525222A (en) | A kind of single phase clock Double-edge D trigger | |
| CN102931959A (en) | Circuit for quickly discharging power-on resetting circuit subjected to power failure | |
| TW201421907A (en) | Pulse-based flip flop | |
| Hiremath et al. | Design and Implementation of Synchronous 4-Bit Up Counter Using 180 nm CMOS Process Technology | |
| CN102386908B (en) | Heat insulation domino circuit and heat insulation domino ternary AND gate circuit | |
| CN106357249A (en) | Power-on reset circuit and integrated circuit | |
| CN101814907A (en) | Signal delay circuit and oscillator using signal delay circuit | |
| CN111867183A (en) | LED drive circuit, power frequency square wave signal sampling circuit and method | |
| CN109150138A (en) | latch | |
| CN111769826B (en) | TSPC trigger with setting and resetting functions | |
| CN104022758B (en) | A kind of band resets the power consumption equilibrium trigger of set port | |
| CN105958975B (en) | A kind of pulse-type D flip-flop based on FinFET | |
| TW419891B (en) | Asynchronous sensing differential logic (ASDL) circuit | |
| CN103093824A (en) | Register circuit for preventing single particle from being overturned | |
| Zhang et al. | Leakage Reduction of Power-Gating Sequential Circuits Based on Complementary Pass-Transistor Adiabatic Logic Circuits | |
| CN104299639B (en) | Soft failure resistant memory cell, latch and trigger | |
| CN108923777A (en) | The inverter module of radiation hardened | |
| CN204190727U (en) | A kind of radiation hardening flip-flop circuit based on complicated three mutual latch units | |
| CN109088618A (en) | C2MOS trigger | |
| Muthukumar et al. | Low-power and area-efficient 9-transistor double-edge triggered flip-flop |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |