CN109150138A - latch - Google Patents
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- CN109150138A CN109150138A CN201810947033.5A CN201810947033A CN109150138A CN 109150138 A CN109150138 A CN 109150138A CN 201810947033 A CN201810947033 A CN 201810947033A CN 109150138 A CN109150138 A CN 109150138A
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- grid
- transistor
- nmos transistor
- pmos transistor
- memory node
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
- H03K3/0233—Bistable circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
- H03K19/00338—In field effect transistor circuits
Abstract
The invention discloses a kind of latch, are made of a storage element, 4 transmission gates and a Muller C cell；Storage unit is made of 3 groups of 2P1N type phase inverters and 3 groups of 1P2N type phase inverters, every group of 2P1N type phase inverter is composed in series by two PMOS transistors and a NMOS transistor, every group of 1P2N type phase inverter is composed in series by a PMOS transistor and two NMOS transistors, and storage unit shares 6 memory nodes；The tenth PMOS transistor~the 13rd PMOS transistor and the tenth NMOS transistor~the 13rd NMOS transistor in Muller C cell are sequentially connected in series, the drain electrode of 13rd PMOS transistor is connected with the drain electrode of the tenth NMOS transistor, output end Q of the node of connection as latch；Data input pin of the input terminal of four transmission gates as latch, the output end of the 4th transmission gate are connected with the end Q.The present invention can resist two node overturnings, intercept the soft error of storage unit transmission.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of latch.
Background technique
The reliability for first feeding chip of integrated circuit technique node brings many challenges, and one of challenge is exactly single
Particle overturns (SEU) bring soft error.
Soft error may occur in different electronic equipments, such as automotive electronics, Medical Devices etc..
In recent years, since process node is constantly advanced, the distance between device is increasingly closer, and device size is also increasingly
Small, this makes an important sources of the single event multiple bit upset caused by charge-trapping and charge share as soft error.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of latch, can resist two node overturnings, intercept storage
The soft error of unit transmission.
In order to solve the above technical problems, latch of the invention, by a storage element, 4 transmission gates and a Muller C
Unit composition；CLK is clock signal, and CLKB is the clock signal that CLK passes through that level-one phase inverter obtains；
The storage unit is made of 3 groups of 2P1N type phase inverters and 3 groups of 1P2N type phase inverters, every group of 2P1N type phase inverter by
Two PMOS transistors and a NMOS transistor are composed in series, and every group of 1P2N type phase inverter is by a PMOS transistor and two
NMOS transistor is composed in series；First PMOS transistor source electrode is connected with power voltage terminal VDD in every group of phase inverter, finally
The source electrode of one NMOS transistor is grounded, and the drain electrode of PMOS transistor is connected with the drain electrode of NMOS transistor in every group of phase inverter
Node be memory node；
First group of 2P1N type phase inverter is connected by the 7th PMOS transistor, the first PMOS transistor and the first NMOS transistor
Composition, memory node therein are denoted as S1；First group of 1P2N type phase inverter by the second PMOS transistor, the 7th NMOS transistor and
Second NMOS transistor is composed in series, and memory node therein is denoted as S2；Second group of 2P1N type phase inverter is by the 8th PMOS crystal
Pipe, third PMOS transistor and third NMOS transistor are composed in series, and memory node therein is denoted as S3；Second group of 1P2N type is anti-
Phase device is composed in series by the 4th PMOS transistor, the 8th NMOS transistor and the 4th NMOS transistor, memory node note therein
For S4；Third group 2P1N type phase inverter is by the 9th PMOS transistor, the 5th PMOS transistor and the 5th NMOS transistor series connection group
At memory node therein is denoted as S5；Third group 1P2N type phase inverter is by the 6th PMOS transistor, the 9th NMOS transistor and
Six NMOS transistors are composed in series, and memory node therein is denoted as S6；The grid of second PMOS transistor, the 6th NMOS transistor
It is connected with the grid of the 8th NMOS transistor with the memory node S1；Grid, the 8th PMOS of 5th PMOS transistor are brilliant
Memory node S2 described in the grid of the grid of body pipe and the first NMOS transistor NM1 is connected；The grid of 4th PMOS transistor,
The grid of the grid of second NMOS transistor and the 9th NMOS transistor is connected with storage memory node S3；First PMOS crystal
The grid of the grid of pipe PM1, the grid of the 9th PMOS transistor and third NMOS transistor is connected with the memory node S4；
The grid and the memory node of the grid of 6th PMOS transistor, the grid of the 4th NMOS transistor and the 7th NMOS transistor
S5 is connected；The grid of the grid of third PMOS transistor, the grid of the 7th PMOS transistor and the 5th NMOS transistor with deposit
Storage node S6 is connected；
The Muller C cell is by the tenth PMOS transistor~the 13rd PMOS transistor and the tenth NMOS transistor~tenth
Three NMOS transistors are sequentially connected in series；Wherein, the source electrode of the tenth PMOS transistor is connected with power voltage terminal, and the 13rd
Output end Q of the node that the drain electrode of PMOS transistor is connected with the drain electrode of the tenth NMOS transistor as latch, the 13rd
The source electrode of NMOS transistor is grounded, the grid input clock signal CLK of the 13rd PMOS transistor, the grid of the tenth NMOS transistor
Pole input clock signal CLKB, the grid of the tenth PMOS transistor and the grid of the 13rd NMOS transistor and memory node S2 phase
Connection, the grid of the 11st PMOS transistor and the grid of the tenth bi-NMOS transistor are connected with memory node S4, and the 12nd
The grid of the 11st transistor of grid and NMOS of PMOS transistor is connected with memory node S6；It is protected in output end Q connection one
Holder, when single-particle inversion occurring in the memory unit, for eliminating the high-impedance state generated in output end.
The input terminal of four transmission gates is connected, as the data input pin D of latch, control terminal input clock
Signal CLK, inverted control terminals input clock signal CLKB；The output end of first transmission gate is connected with memory node S1, and second
The output end of transmission gate is connected with memory node S3, and the output end of third transmission gate is connected with memory node S5, and the 4th passes
The output end of defeated door is connected with the output end Q of latch.
Latch of the invention has the characteristics that optimised power consumption, high speed, highly reliable, has an anti-node and two nodes
The function of overturning intercepts the soft error that storage unit transmission comes；It is connected to the retainer of output end, is a weak retainer, energy
Enough prevent output end from generating high-impedance state.
4th transmission gate provides high speed transmission path, and as CLK=1, data pass through the 4th transmission from data input pin D
Door reaches latch outputs Q, realizes the characteristic of the high speed transmission data of latch.
When clock CLK is high level, the 13rd PMOS transistor and the tenth NMOS transistor in Muller C cell are closed
It closes, the data mask that Muller C cell can spread out of storage unit, then when input signal is incoming from the 4th transmission gate, it will not
It is influenced by data in storage unit, so that input signal smoothly reaches output end Q.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the latch implementations (one) schematic diagram；
Fig. 2 is 2P1N type phase inverter and 1P2N type phase inverter schematic diagram employed in figure 1；
Fig. 3 is the waveform diagram of latch each point shown in Fig. 1；
Fig. 4 is the latch implementations (two) schematic diagram.
Specific embodiment
Embodiment one
As shown in connection with fig. 1, the latch in the present embodiment, by a storage element, 4 transmission gate TG1~TG 4
It is constituted with a Muller C cell (Muller C-element or C cell).
The storage unit is made of 3 groups of 2P1N type phase inverters and 3 groups of 1P2N type phase inverters.Referring to fig. 2 (a), every group
2P1N type phase inverter is composed in series by two PMOS transistors and a NMOS transistor, wherein A1, B1, C1 are input terminal, Q1
For output end.Referring to fig. 2 (b), every group of 1P2N type phase inverter is composed in series by a PMOS transistor and two NMOS transistors,
Wherein, A2, B2, C2 are input terminal, and Q2 is output end.
There are six memory nodes altogether in the storage unit, are denoted as respectively: memory node S1~S6, wherein memory node
S1, S3, S5, output end of each memory node respectively with the grid end of 3 MOSS transistors and a transmission gate are connected；It deposits
Node S2, S4, S6 are stored up, grid end of each memory node respectively with 3 MOSS transistors is connected.
Transmission gate TG1~the TG4 is cmos transmission gate, is made of a NMOS transistor and a PMOS transistor.
Muller C cell has similar inverter function.When the input logic level of Muller C cell is consistent, Muller C is mono-
Member is inverter function；When the input logic level of Muller C cell is not complete consistent, high-impedance state is exported.
In the present embodiment, the Muller C cell is by 4 PMOS transistor PM10~PM13 and 4 NMOS transistor NM10
~NM13 is sequentially connected in series.
In the present embodiment, CLK is clock signal, and CLKB is the clock signal that CLK passes through that level-one phase inverter obtains.
First group of 2P1N type phase inverter is by PMOS transistor PM7, PMOS transistor PM1, NMOS transistor NM1 series connection group
At the source electrode of PMOS transistor PM7 is connected with power voltage terminal VDD, the drain electrode of PMOS transistor PM1 and NMOS transistor
The node of the drain electrode connection of NM1 is denoted as memory node S1, the source electrode ground connection of NMOS transistor NM1.
First group of 1P2N type phase inverter is by PMOS transistor PM2, NMOS transistor NM7 and NMOS transistor NM2 series connection group
At the source electrode of PMOS transistor PM2 is connected with power voltage terminal VDD, grid and the memory node S1 phase of PMOS transistor PM2
Connection, the node that the drain electrode of PMOS transistor PM2 is connected with the drain electrode of NMOS transistor NM7 are denoted as memory node S2, NMOS
The source electrode of transistor NM2 is grounded.
Second group of 2P1N type phase inverter is by PMOS transistor PM8, PMOS transistor PM3 and NMOS transistor NM3 series connection group
At the source electrode of PMOS transistor PM8 is connected with power voltage terminal VDD, grid and the memory node S2 phase of PMOS transistor PM8
Connection, the node that the drain electrode of PMOS transistor PM3 is connected with the drain electrode of NMOS transistor NM3 are denoted as memory node S3, NMOS
The source electrode of transistor NM3 is grounded.
Second group of 1P2N type phase inverter is by PMOS transistor PM4, NMOS transistor NM8 and NMOS transistor NM4 series connection group
At the source electrode of PMOS transistor PM4 is connected with power voltage terminal VDD, grid and the memory node S3 phase of PMOS transistor PM4
Connection, the node that the drain electrode of PMOS transistor PM4 is connected with the drain electrode of NMOS transistor NM8 are denoted as memory node S4, NMOS
The grid of transistor NM8 is connected with memory node S1, the source electrode ground connection of NMOS transistor NM4.
Third group 2P1N type phase inverter is by PMOS transistor PM9, PMOS transistor PM5 and NMOS transistor NM5 series connection group
At the source electrode of PMOS transistor PM9 is connected with power voltage terminal VDD, grid and the memory node S4 phase of PMOS transistor PM9
Connection, the node that the drain electrode of PMOS transistor PM5 is connected with the drain electrode of NMOS transistor NM5 are denoted as memory node S5, PMOS
The grid of transistor PM5 is connected with memory node S2, the source electrode ground connection of NMOS transistor NM5.
Third group 1P2N type phase inverter is by PMOS transistor PM6, NMOS transistor NM9 and NMOS transistor NM6 series connection group
At the source electrode of PMOS transistor PM6 is connected with power voltage terminal VDD, grid and the memory node S5 phase of PMOS transistor PM6
Connection, the node that the drain electrode of PMOS transistor PM6 is connected with the drain electrode of NMOS transistor NM9 are denoted as memory node S6, NMOS
The grid of transistor NM9 is connected with memory node S3, and the grid of NMOS transistor NM6 is connected with memory node S1, NMOS
The source electrode of transistor NM6 is grounded.
The grid of NMOS transistor NM1 is connected with memory node S2, the grid and memory node S3 of NMOS transistor NM2
It is connected, the grid of NMOS transistor NM3 and the grid of PMOS transistor PM1 are connected with memory node S4, NMOS transistor
The grid of NM4 and the grid of NMOS transistor NM7 are connected with memory node S5, grid, the PMOS crystal of PMOS transistor PM3
The grid of pipe PM7 and the grid of NMOS transistor NM5 are connected with memory node S6.
The source electrode of PMOS transistor PM10 in Muller C cell is connected with power voltage terminal, PMOS transistor PM13's
Drain output end Q of the node being connected with the drain electrode of NMOS transistor NM10 as latch, the source of NMOS transistor NM13
Pole ground connection.The grid input clock signal of grid the input clock signal CLK, NMOS transistor NM10 of PMOS transistor PM13
CLKB.The grid of PMOS transistor PM10 and the grid of NMOS transistor NM13 are connected with memory node S2, PMOS transistor
The grid of PM11 and the grid of NMOS transistor NM12 are connected with memory node S4, the grid and NMOS of PMOS transistor PM12
The grid of transistor NM11 is connected with memory node S6.
The input terminal of four transmission gate TG1~TG4 is connected, the data input pin D as latch.Four transmission gates
The control terminal input clock signal CLK of TG1~TG4, inverted control terminals input clock signal CLKB.The output end of transmission gate TG1
Be connected with memory node S1, the output end of transmission gate TG2 is connected with memory node S3, the output end of transmission gate TG3 with deposit
Storage node S5 is connected, and the output end of transmission gate TG4 is connected with the output end Q of latch.
In one retainer WK of output end Q connection, when single-particle inversion occurring in the memory unit, for eliminating in output end
The high-impedance state of generation.The retainer WK is two concatenated phase inverters in the present embodiment.
When the work of above-mentioned latch is in break-through mode, if clock signal clk is high level, CLKB is low level.It is solemn
The PMOS transistor PM13 in C cell is strangled, NMOS transistor NM10 is closed, and data are incoming from input terminal D, passes through transmission gate TG1
~TG4 reaches three memory nodes S1, S3 and S5 and output end Q in storage unit.
When the work of above-mentioned latch is in latch mode, if clock signal clk is low level, CLKB is high level.It passes
Defeated door TG1~TG4 is closed, and the PMOS transistor PM13 in Muller C cell, NMOS transistor NM10 are both turned on, and data are from storage
Three memory node S2, S4 and S6 outflows reach output end Q by Muller C cell in unit.Therefore, the present invention has general
The function of the shared basic latch data of latch.
Fig. 3 is the waveform diagram of each point in latch circuit shown in figure, in which:
(1) in 3.5ns, apply single-particle inversion (SEU) pulse 1 at memory node S1, it can be seen that latch
The logic state of the output end Q of device circuit is unaffected, and output Q keeps 0 logic state.This demonstrates latch electricity of the invention
Road has the function of resisting a node overturning.
(2) in 6ns, memory node S4, latch circuit output end Q at simultaneously apply single-particle inversion pulse 1,
It can be seen that output end Q is pulled back to rapidly original correct logic level.
(3) in 13.5ns, apply single-particle inversion (SEU) pulse 1 simultaneously at memory node S5, S6, it can be seen that
Storage S5, S6 are pulled back to rapidly original correct logic level, and the logic state of the output end Q of latch circuit is not by shadow
It rings, output Q keeps 1 logic state.
(4) in 16ns, apply single-particle inversion (SEU) pulse 1 simultaneously at memory node S2, S3, memory node S2,
S3 cannot be pulled back to original correct logic level, and memory node S1 and S4 are flipped, but due to memory node at this time
S5, S6 keep original correct logic state, and Muller C cell can shield the soft error come out from storage unit, and output end Q is protected
Original correct status is held, but output end Q can be in high-impedance state, but due to the effect of weak retainer, so that output end Q will not
Into high-impedance state.Over time the change of logic state, therefore weak retainer may occur for the high-impedance state of node
Circuit can be made not enter high-impedance state.
(5) in 23.5ns, apply single-particle inversion (SEU) pulse 1 simultaneously at memory node S1, S3, it can be seen that
Memory node S1, S3 are pulled back to rapidly original correct logic level, and the logic state of the output end Q of circuit is unaffected,
Output end Q keeps 0 logic state.
(6) in 26ns, apply single-particle inversion (SEU) pulse 1 simultaneously at memory node S2, S5, it can be seen that deposit
Storage node S2, S5 are pulled back to rapidly original correct logic level, and the logic state of the output end Q of circuit is unaffected, defeated
Q keeps 0 logic state out.
From above-mentioned (2), (3), (4), (5), the process of (6) description, demonstrating the present invention has two nodes overturnings of resistance
Function.
Embodiment two
The difference between this embodiment and the first embodiment lies in 3 groups of 2P1N type phase inverters in the storage unit, are changed to 2P2N type
Phase inverter is sequentially connected in series by every group of 2P2N type phase inverter by two PMOS transistors and two NMOS transistors.Specifically
For, be exactly, first group of 2P2N type phase inverter by PMOS transistor PM7, PMOS transistor PM1, NMOS transistor NM14 and
NMOS transistor NM1 composition.The node of the drain electrode connection of the drain electrode and NMOS transistor NM14 of PMOS transistor PM1, is denoted as and deposits
Store up node S1, the grid input clock signal CLKB of NMOS transistor NM14.Second group of 2P2N type phase inverter is by PMOS transistor
PM8, PMOS transistor PM3, NMOS transistor NM15 and NMOS transistor NM3 composition.The drain electrode of PMOS transistor PM3 and NMOS
The node of the drain electrode connection of transistor NM15, is denoted as memory node S3, the grid input clock signal of NMOS transistor NM15
CLKB.Third group 2P2N type phase inverter is by PMOS transistor PM9, PMOS transistor PM5, NMOS transistor NM16 and NMOS crystal
Pipe NM5 composition.The node of the drain electrode connection of the drain electrode and NMOS transistor NM16 of PMOS transistor PM5, is denoted as memory node S3,
The grid input clock signal CLKB of NMOS transistor NM16.Remaining circuit structure and Fig. 1 are just the same.
The latch of the embodiment of the present invention one is fewer than the latch of embodiment two to use three NMOS transistors, therefore, shared
Area is smaller.Increased NMOS transistor NM14~NMOS crystal in three groups of 2P2N phase inverters in the latch of embodiment two
The grid input clock signal CLKB of pipe NM16, it is possible to reduce dynamic power consumption and short-circuit dissipation from positive feedback, to reach
To the purpose for reducing power consumption, therefore the latch of power dissipation ratio embodiment one is lower.
Above by specific embodiment, invention is explained in detail, but these are not constituted to of the invention
Limitation.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these
It should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of latch, which is characterized in that be made of a storage element, 4 transmission gates and a Muller C cell；CLK is
Clock signal, CLKB are the clock signal that CLK passes through that level-one phase inverter obtains；
The storage unit is made of 3 groups of 2P1N type phase inverters and 3 groups of 1P2N type phase inverters, and every group of 2P1N type phase inverter is by two
PMOS transistor and a NMOS transistor are composed in series, and every group of 1P2N type phase inverter is by a PMOS transistor and two NMOS
Transistor is composed in series；First PMOS transistor source electrode is connected with power voltage terminal VDD in every group of phase inverter, the last one
The source electrode of NMOS transistor is grounded, the section that the drain electrode of PMOS transistor is connected with the drain electrode of NMOS transistor in every group of phase inverter
Point is memory node；
First group of 2P1N type phase inverter is by the 7th PMOS transistor, the first PMOS transistor and the first NMOS transistor series connection group
At memory node therein is denoted as S1；First group of 1P2N type phase inverter is by the second PMOS transistor, the 7th NMOS transistor and
Bi-NMOS transistor is composed in series, and memory node therein is denoted as S2；Second group of 2P1N type phase inverter by the 8th PMOS transistor,
Third PMOS transistor and third NMOS transistor are composed in series, and memory node therein is denoted as S3；Second group of 1P2N type reverse phase
Device is composed in series by the 4th PMOS transistor, the 8th NMOS transistor and the 4th NMOS transistor, and memory node therein is denoted as
S4；Third group 2P1N type phase inverter is composed in series by the 9th PMOS transistor, the 5th PMOS transistor and the 5th NMOS transistor,
Memory node therein is denoted as S5；Third group 1P2N type phase inverter is by the 6th PMOS transistor, the 9th NMOS transistor and the 6th
NMOS transistor is composed in series, and memory node therein is denoted as S6；The grid of second PMOS transistor, the 6th NMOS transistor and
The grid of 8th NMOS transistor is connected with the memory node S1；Grid, the 8th PMOS crystal of 5th PMOS transistor
Memory node S2 described in the grid of the grid of pipe and the first NMOS transistor NM1 is connected；The grid of 4th PMOS transistor,
The grid of the grid of bi-NMOS transistor and the 9th NMOS transistor is connected with storage memory node S3；First PMOS transistor
The grid of the grid of PM1, the grid of the 9th PMOS transistor and third NMOS transistor is connected with the memory node S4；The
The grid and the memory node S5 of the grid of six PMOS transistors, the grid of the 4th NMOS transistor and the 7th NMOS transistor
It is connected；Grid and the storage of the grid of third PMOS transistor, the grid of the 7th PMOS transistor and the 5th NMOS transistor
Node S6 is connected；
The Muller C cell is by the tenth PMOS transistor~the 13rd PMOS transistor and the tenth NMOS transistor~13rd
NMOS transistor is sequentially connected in series；Wherein, the source electrode of the tenth PMOS transistor is connected with power voltage terminal, the 13rd PMOS
Output end Q, ten three NMOS of the node that the drain electrode of transistor is connected with the drain electrode of the tenth NMOS transistor as latch
The source electrode of transistor is grounded, the grid input clock signal CLK of the 13rd PMOS transistor, and the grid of the tenth NMOS transistor is defeated
Enter clock signal CLKB, the grid of the tenth PMOS transistor and the grid of the 13rd NMOS transistor are connected with memory node S2
It connecing, the grid of the 11st PMOS transistor and the grid of the tenth bi-NMOS transistor are connected with memory node S4, and the 12nd
The grid of the 11st transistor of grid and NMOS of PMOS transistor is connected with memory node S6；It is protected in output end Q connection one
Holder, when single-particle inversion occurring in the memory unit, for eliminating the high-impedance state generated in output end.
The input terminal of four transmission gates is connected, as the data input pin D of latch, control terminal input clock signal
CLK, inverted control terminals input clock signal CLKB；The output end of first transmission gate is connected with memory node S1, the second transmission
The output end of door is connected with memory node S3, and the output end of third transmission gate is connected with memory node S5, the 4th transmission gate
Output end be connected with the output end Q of latch.
2. latch as described in claim 1, it is characterised in that: the retainer is two concatenated phase inverters.
3. latch as described in claim 1, it is characterised in that: transmission gate is cmos transmission gate, by a NMOS transistor
It is constituted with a PMOS transistor.
4. latch as described in claim 1, it is characterised in that: the latch work is in break-through mode, if CLK is height
When level, CLKB is low level, the 13rd PMOS transistor in Muller C cell, and the tenth NMOS transistor is closed, and data are from defeated
Enter to hold D incoming, by four transmission gates, reaches three memory nodes S1, S3 and S5 and output end Q in storage unit.
5. latch as described in claim 1, it is characterised in that: the latch work is in latch mode, if CLK is low
When level, CLKB is high level, and four transmission gates are closed, the 13rd PMOS transistor in Muller C cell, the tenth NMOS crystal
Pipe is both turned on, and data three memory node S2, S4 and S6 outflows from storage unit reach output end Q by Muller C cell.
6. a kind of latch, which is characterized in that be made of a storage element, 4 transmission gates and a Muller C cell；CLK is
Clock signal, CLKB are the clock signal that CLK passes through that level-one phase inverter obtains；
The storage unit is made of 3 groups of 2P2N type phase inverters and 3 groups of 1P2N type phase inverters, and every group of 2P2N type phase inverter is by two
PMOS transistor and two NMOS transistors are composed in series, and every group of 1P2N type phase inverter is by a PMOS transistor and two NMOS
Transistor is composed in series；The source electrode of first PMOS transistor is connected with power voltage terminal VDD in every group of phase inverter, last
The source electrode of a NMOS transistor is grounded, and the drain electrode of PMOS transistor is connected with the drain electrode of NMOS transistor in every group of phase inverter
Node is memory node；
First group of 2P2N type phase inverter is by the 7th PMOS transistor, the first PMOS transistor, the 14th NMOS transistor and first
NMOS transistor is sequentially connected in series, and memory node is denoted as S1；Second group of 2P2N type phase inverter is by the 8th PMOS transistor,
Three PMOS transistors, the 15th NMOS transistor and third NMOS transistor are sequentially connected in series, and memory node is denoted as S3；The
Three groups of 2P2N type phase inverters are brilliant by the 9th PMOS transistor, the 5th PMOS transistor, the 16th NMOS transistor and the 5th NMOS
Body pipe is sequentially connected in series, and memory node is denoted as S5；The grid input clock signal of 14th~the 16th NMOS transistor
CLKB；First group of 1P2N type phase inverter is by the second PMOS transistor, the 7th NMOS transistor and the second NMOS transistor series connection group
At memory node therein is denoted as S2；Second group of 1P2N type phase inverter is by the 4th PMOS transistor, the 8th NMOS transistor and
Four NMOS transistors are composed in series, and memory node therein is denoted as S4；Third group 1P2N type phase inverter by the 6th PMOS transistor,
9th NMOS transistor and the 6th NMOS transistor are composed in series, and memory node therein is denoted as S6；Second PMOS transistor
The grid of grid, the 6th NMOS transistor and the 8th NMOS transistor is connected with the memory node S1；5th PMOS crystal
Memory node S2 described in the grid of the grid of pipe, the grid of the 8th PMOS transistor and the first NMOS transistor NM1 is connected；The
The grid and storage memory node S3 of the grid of four PMOS transistors, the grid of the second NMOS transistor and the 9th NMOS transistor
It is connected；Grid, the grid of the 9th PMOS transistor and the grid of third NMOS transistor of first PMOS transistor PM1 and institute
Memory node S4 is stated to be connected；The grid and the 7th NMOS transistor of the grid of 6th PMOS transistor, the 4th NMOS transistor
Grid be connected with the memory node S5；The grid and the 5th of the grid of third PMOS transistor, the 7th PMOS transistor
The grid of NMOS transistor is connected with memory node S6；
The Muller C cell is by the tenth PMOS transistor~the 13rd PMOS transistor and the tenth NMOS transistor~13rd
NMOS transistor is sequentially connected in series；Wherein, the source electrode of the tenth PMOS transistor is connected with power voltage terminal, the 13rd PMOS
Output end Q, ten three NMOS of the node that the drain electrode of transistor is connected with the drain electrode of the tenth NMOS transistor as latch
The source electrode of transistor is grounded, the grid input clock signal CLK of the 13rd PMOS transistor, and the grid of the tenth NMOS transistor is defeated
Enter clock signal CLKB, the grid of the tenth PMOS transistor and the grid of the 13rd NMOS transistor are connected with memory node S2
It connecing, the grid of the 11st PMOS transistor and the grid of the tenth bi-NMOS transistor are connected with memory node S4, and the 12nd
The grid of the 11st transistor of grid and NMOS of PMOS transistor is connected with memory node S6；It is protected in output end Q connection one
Holder, when single-particle inversion occurring in the memory unit, for eliminating the high-impedance state generated in output end.
The input terminal of four transmission gates is connected, as the data input pin D of latch, control terminal input clock signal
CLK, inverted control terminals input clock signal CLKB；The output end of first transmission gate is connected with memory node S1, the second transmission
The output end of door is connected with memory node S3, and the output end of third transmission gate is connected with memory node S5, the 4th transmission gate
Output end be connected with the output end Q of latch.
7. latch as claimed in claim 6, it is characterised in that: the retainer is two concatenated phase inverters.
8. latch as claimed in claim 6, it is characterised in that: transmission gate is cmos transmission gate, by a NMOS transistor
It is constituted with a PMOS transistor.
9. latch as claimed in claim 6, it is characterised in that: the latch work is in break-through mode, if CLK is height
When level, CLKB is low level, the 13rd PMOS transistor in Muller C cell, and the tenth NMOS transistor is closed, and data are from defeated
Enter to hold D incoming, by four transmission gates, reaches three memory nodes S1, S3 and S5 and output end Q in storage unit.
10. latch as claimed in claim 6, it is characterised in that: the latch work is in latch mode, if CLK is
When low level, CLKB is high level, and four transmission gates are closed, the 13rd PMOS transistor in Muller C cell, and the tenth NMOS is brilliant
Body pipe is both turned on, and data three memory node S2, S4 and S6 outflows from storage unit reach output end by Muller C cell
Q。
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| CN201810947033.5A CN109150138A (en) | 2018-08-20 | 2018-08-20 | latch |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810947033.5A CN109150138A (en) | 2018-08-20 | 2018-08-20 | latch |
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| CN109150138A true CN109150138A (en) | 2019-01-04 |
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| CN109936358A (en) * | 2019-02-13 | 2019-06-25 | 天津大学 | Resist the latch structure of the double overturnings of single-particle |
| CN111988030A (en) * | 2020-08-24 | 2020-11-24 | 合肥工业大学 | Single-particle three-point overturning reinforced latch |
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| CN108134597A (en) * | 2018-01-08 | 2018-06-08 | 安徽大学 | A kind of completely immune latch of three internal nodes overturning |
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Application publication date: 20190104 |