CN110166041A - Latch - Google Patents
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- CN110166041A CN110166041A CN201910280313.XA CN201910280313A CN110166041A CN 110166041 A CN110166041 A CN 110166041A CN 201910280313 A CN201910280313 A CN 201910280313A CN 110166041 A CN110166041 A CN 110166041A
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- 238000010586 diagram Methods 0.000 description 16
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
Abstract
The present invention provides a kind of latch, and four Muller C cells, four by the Muller C cell of clock control and four transmission gates；Wherein for eight Muller C cells by the distribution counterclockwise of its footmark sequence and end to end composition loop, the output end signal of each Muller C cell is corresponding with its footmark, and the output end signal of eight Muller C cells is in distribution counterclockwise；The footmark of two input end signals of same Muller C cell is all odd number or is all even number, and four transmission gates share an input node D.The invention proposes the latch of two kinds of novel anti-two nodes overturnings, the selection of node pair covers 4 whole class nodes pair, thus prove when any two memory node to simultaneously occur transient error overturning, circuit can make each memory node original correct logic level back by itself feedback, and circuit of the invention has the function of anti-two nodes overturning.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of latch.
Background technique
The reliability for first feeding chip of integrated circuit technique node brings many challenges, and one of challenge is exactly single
Particle effect bring soft error.Soft error may occur in different electronic equipments, such as automotive electronics, Medical Devices
Deng.
In recent years, since process node is constantly advanced, device is leaned on increasingly closer, and device size is also smaller and smaller, this makes
Obtaining single event multiple bit upset caused by charge-trapping and charge share becomes an important sources of soft error.
Traditional latch is when occurring node overturning, without the function of holding soft error.Due to caused by charge share
Two node overturnings, so that the latch failure of Rong Yiwei node overturning, does not also have the function of holding soft error.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of latch, existing for solving
There is the problems in technology.
In order to achieve the above objects and other related objects, the present invention provides a kind of latch, and the latch includes at least:
Four Muller C cells: MC2, MC4, MC6, MC8；Four Muller C cells by clock control: MC1, MC3, MC5, MC7；And
Four transmission gates TG1, TG2, TG3, TG4；Eight Muller C cell MC1 to MC8 according to its footmark sequence counterclockwise distribution and
End to end composition loop, enabling x is 1 to 8 integer, and the output end signal Sx of each Muller C cell is corresponding with its footmark MCx,
And the output end signal S1 to S8 of eight Muller C cells is in distribution counterclockwise；Two input terminals of same Muller C cell
The footmark of signal is all odd number or is all even number；The output end of four transmission gate TG1 to TG4 is sequentially connected signal respectively
S1,S3,S5,S7；Four transmission gates share an input node D.
Preferably, the output node Q of the latch is the node of the output end signal S7 of the Muller C cell MC7.
Preferably, the footmark of two input end signals of the same Muller C cell be all odd number or be all even number group
Conjunction includes: that input end signal is S1, S3, output end signal S4；Input end signal is S2, S4, output end signal S5；Input
End signal is S3, S5, output end signal S6；Input end signal is S4, S6, output end signal S7；Input end signal is S5,
S7, output end signal S8；Input end signal is S6, S8, output end signal S1；Input end signal is S7, S1, output end letter
Number be S2；Input end signal is S8, S2, output end signal S3.
Preferably, two input end signals of the same Muller C cell are all high level or are all low level.
The present invention also provides a kind of latch, the latch is included at least: four Muller C cells: MC2, MC4, MC6,
MC8；Four Muller C cells by clock control: MC1, MC3, MC5, MC7；And four transmission gates TG1, TG2, TG3, TG4；
Eight Muller C cell MC1 to MC8 are distributed clockwise according to its footmark sequence and end to end composition loop, and enabling x is 1 to 8
Integer, the output end signal Sx of each Muller C cell is corresponding with its footmark MCx, and the output of eight Muller C cells
End signal S1 to S8 is in distribution counterclockwise；The footmark of two input end signals of same Muller C cell is all odd number or is all idol
Number；The output end of four transmission gate TG1 to TG4 is sequentially connected signal S1, S7, S5, S3 respectively；Four transmission gates are total
There is an input node D.
Preferably, the output node Q of the latch is the node of the output end signal S7 of the Muller C cell MC7.
Preferably, the footmark of two input end signals of the same Muller C cell be all odd number or be all even number group
Conjunction includes: that input end signal is S1, S3, output end signal S8；Input end signal is S8, S2, output end signal S7；Input
End signal is S7, S1, output end signal S6；Input end signal is S6, S8, output end signal S5；Input end signal is S5,
S7, output end signal S4；Input end signal is S4, S6, output end signal S3；Input end signal is S3, S5, output end letter
Number be S2；Input end signal is S2, S4, output end signal S1.
Preferably, two input end signals of the same Muller C cell are all high level or are all low level.
As described above, latch of the invention, have the advantages that novel two anti-the invention proposes two kinds
The latch of node overturning, the selection of node pair cover 4 whole class nodes pair, thus prove to work as any two memory node
To transient error overturning occurs simultaneously, circuit can make each memory node original correctly logic electricity back by itself feedback
Flat, circuit of the invention has the function of anti-two nodes overturning.
Detailed description of the invention
Fig. 1 a is shown as the two input Muller C cells and its simplified structure diagram of the prior art；
Fig. 1 b is shown as in the prior art by two input Muller C cells of clock signal control and its simplified structural representation
Figure；
Fig. 1 c is shown as transmission gate in the prior art and its simplified structure diagram；
Fig. 2 a is shown as a kind of electrical block diagram of latch of the invention；
Fig. 2 b is shown as the circuit reduction node diagram of the latch of Fig. 2 a；
Fig. 3 is shown as the waveform diagram of each signal in Fig. 2 a latch circuit；
Fig. 4 a is shown as the electrical block diagram of another latch of the invention；
Fig. 4 b is shown as the circuit reduction node diagram of the latch of Fig. 4 a.
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to Fig. 1 a to Fig. 4 b.It should be noted that diagram provided in the present embodiment only illustrates in a schematic way
Basic conception of the invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
As shown in Figure 1a, Fig. 1 a is shown as the two input Muller C cells and its simplified structure diagram of the prior art；Fig. 1 a
In two input Muller C (Muller C, abbreviation: MC) units, when input A it is identical with B logic state when (while for " 1 " or
" 0 "), which is inverter function；When inputting A and not identical B logic state, export as high-impedance state.
Referring to Fig. 1 b, Fig. 1 b is shown as in the prior art by two input Muller C cells of clock signal control and its simplification
Structural schematic diagram.Two input Muller C (Muller C) units that clock signal controls in Fig. 1 b, CLK are opposite with CLKB current potential.When
When CLK=0, CLKB=1, this element is identical as Fig. 1 a function；Work as CLK=1, when CLKB=0, this element output is high-impedance state.
Referring to Fig. 1 c, Fig. 1 c is shown as transmission gate in the prior art and its simplified structure diagram.In Fig. 1 c, work as CLK
When=1, CLKB=0, transmission gate opens (" being connected " in other words)；Work as CLK=0, when CLKB=1, transmission gate is closed (in other words
" cut-off ").
Embodiment one
The present invention provides a kind of latch, and as shown in Figure 2 a, Fig. 2 a is shown as a kind of circuit knot of latch of the invention
Structure schematic diagram.The latch includes at least: four Muller C cells: MC2, MC4, MC6, MC8；Four Mu by clock control
Strangle C cell: MC1, MC3, MC5, MC7；And four transmission gates TG1, TG2, TG3, TG4；Wherein, eight Muller C cells
MC1 to MC8 is distributed counterclockwise according to its footmark sequence and end to end composition loop, and enabling x is 1 to 8 integer, each Muller C
The output end signal Sx of unit is corresponding with its footmark MCx, and the output end signal S1 to S8 of eight Muller C cells is in inverse
Hour hands distribution；The footmark of two input end signals of same Muller C cell is all odd number or is all even number；Four transmission gates
The output end of TG1 to TG4 is sequentially connected signal S1, S3, S5, S7 respectively；Four transmission gates share an input node D.
The Muller C cell MC1 to MC8 of the invention is the Muller C cell of two inputs.In Fig. 2 a, the Muller C cell
The output end of MC1 connects an input terminal of the Muller C cell MC2, described in the output end connection of the Muller C cell MC2
One of input terminal of Muller C cell MC3, the output end of the Muller C cell MC3 connect its of the Muller C cell MC4
In an input terminal, the output end of the Muller C cell MC4 connects one of input terminal of the Muller C cell MC5, institute
The output end for stating Muller C cell MC5 connects one of input terminal of the Muller C cell MC6, and the Muller C cell MC6 is defeated
Outlet connects one of input terminal of the Muller C cell MC7, and the output end of the Muller C cell MC7 connects the Muller
One of input terminal of C cell MC8, the output end of the Muller C cell MC8 connect wherein the one of the Muller C cell MC1
A input terminal.
In the embodiment of the present invention latch circuit, the footmark of two input end signals of the same Muller C cell is same
It for odd number or is all even number；If two input end signals of Muller C cell MC1 are S6, S8；Two inputs of Muller C cell MC2
End signal is S1, S7；Two input end signals of Muller C cell MC3 are S2, S8；Two input terminals of Muller C cell MC4 are believed
Number be S1, S3；Two input end signals of Muller C cell MC5 are S2, S4；Two input end signals of Muller C cell MC6 are
S3, S5；Two input end signals of Muller C cell MC7 are S4, S6；Two input end signals of Muller C cell MC8 are S5,
S7。
The output end signal Sx of each Muller C cell is corresponding with its footmark MCx in the embodiment of the present invention latch circuit,
If the output end signal of Muller C cell MC1 is S1, the output end signal of Muller C cell MC2 is S2, and Muller C cell MC3's is defeated
End signal is S3 out, and the output end signal of Muller C cell MC4 is S4, and the output end signal of Muller C cell MC5 is S5, Muller C
The output end signal of unit MC6 is S6, and the output end signal of Muller C cell MC7 is S7, the output end signal of Muller C cell MC8
For S8.Preferably, the output node Q of the latch is the section of the output end signal S7 of the Muller C cell MC7 to the present embodiment
Point.The input node of circuit is D.
Preferably, the footmark of two input end signals of the same Muller C cell of the embodiment of the present invention is all odd number or same
Combination for even number includes: that input end signal is S1, S3, output end signal S4；Input end signal is S2, S4, output end letter
Number be S5；Input end signal is S3, S5, output end signal S6；Input end signal is S4, S6, output end signal S7；Input
End signal is S5, S7, output end signal S8；Input end signal is S6, S8, output end signal S1；Input end signal is S7,
S1, output end signal S2；Input end signal is S8, S2, output end signal S3.Further, the embodiment of the present invention
Two input end signals of same Muller C cell are all high level " 1 " or are all low level " 0 ".
With reference to Fig. 2 b, Fig. 2 b is shown as the circuit reduction node diagram of the latch of Fig. 2 a.By Fig. 2 b it is found that Muller C's is defeated
Enter end signal to for < SX,SX+2>, output end signal SX+3.Assuming that S1 and S3 are overturn simultaneously.Overturning can be led while S1 and S3
The overturning for causing S4, since S6 and S8 is not affected, S1 can be restored to original correct logic level, S2 and S8's
Correct logic level can also make S3 be restored to original correct logic level, and later, the recovery of S1 and S3 can make S4 extensive again
It is multiple.Finally, all nodes of circuit are original correct logic level.
The basic principle of latch circuit function described in the present embodiment:
1. break-through mode: when clock signal clk is high level, CLKB is low level.MC1, MC3, MC5, MC7 are in
Off state, output are high-impedance state.Data are incoming from input terminal D, by transmission gate TG1-TG4, reach in storage unit
Memory node S1, S3, S5 and output end Q (S7).
2. latch mode: when clock signal clk is low level, CLKB is high level.Transmission gate TG1-TG4 is closed,
MC1, MC3, MC5, MC7 are on state, at this point, the Muller C cell of 4 clock controls is functionally showed with MC2, MC4,
MC6, MC8 are identical.According to the relationship of latch, data are sustainedly and stably spread out of from output end Q (S7).
When clock signal clk is high level, CLKB is low level, and circuit is in break-through mode at this time, is stored when two
When mistake overturning occurs for node, error signal will not be stored, because input terminal D constantly has data incoming, mistake is quickly
Just refreshed, will not be latched.So consider that CLKB is high level, and circuit is in when clock signal clk is low level
Situation under latch mode.
Two bit flippings: two node potentials are flipped simultaneously.Node S1-S8 in storage unit can be divided into 28
It is right, wherein 8 classes can be summarized as again by their design feature:
(1)<S2X-1,S2X>:<S1,S2>,<S3,S4>,<S5,S6>,<S7,S8>；
(2)<S2X,S2X+1>:<S2,S3>,<S4,S5>,<S6,S7>,<S8,S1>；
(3)<S2X-1,S2X+1>:<S1,S3>,<S3,S5>,<S5,S7>,<S7,S1>；
(4)<S2X,S2X+2>:<S2,S4>,<S4,S6>,<S6,S8>,<S8,S2>；
(5)<S2X-1,S2X+2>:<S1,S4>,<S3,S6>,<S5,S8>,<S7,S2>；
(6)<S2X,S2X+3>:<S2,S5>,<S4,S7>,<S6,S1>,<S8,S3>；
(7)<S2X-1,S2X+3>:<S1,S5>,<S3,S7>；
(8)<S2X,S2X+4>:<S2,S6>,<S4,S8>.
Wherein 1≤X≤4, and X is integer.Enabling N is the integer less than 13, as N > 8, SN-8→SN(by SN-8Again it assigns
To SN)。
In the case where being low level (CLKB is high level at this time) due to CLK, the Muller C cell of clock control (MC1,
MC3, MC5, MC7) it can be equivalent to the Muller C cell (MC2, MC4, MC6, MC8) of no clock control, above 8 kinds of classification can be into one
Step is divided into following 4 class:
(1)<SX,SX+1>:<S1,S2>,<S2,S3>,<S3,S4>,<S4,S5>,<S5,S6>,<S6,S7>,<S7,S8>,<
S8,S1>；
(2)<SX,SX+2>:<S1,S3>,<S2,S4>,<S3,S5>,<S4,S6>,<S5,S7>,<S6,S8>,<S7,S1>,<
S8,S2>；
(3)<SX,SX+3>:<S1,S4>,<S2,S5>,<S3,S6>,<S4,S7>,<S5,S8>,<S6,S1>,<S7,S2>,<
S8,S3>；
(4)<SX,SX+4>:<S1,S5>,<S2,S6>,<S3,S7>,<S4,S8>.
Wherein 1≤X≤8, and X is integer.Enabling N is the integer less than 13, works as SN> S8When, SN-8→SN(by SN-8Again it assigns
To SN)。
The waveform diagram of each signal in Fig. 2 a latch circuit is shown as with reference to Fig. 3, Fig. 3.Waveform description: (1) to section
Point is to < SX,SX+1> verifying: in 6ns, transient error (transient fault, referred to as: TF) is applied simultaneously to S1 and S2
Pulse；In 12ns, transient error pulse is applied simultaneously to S3 and S4.(2) to node to < SX,SX+2> verifying: in 26ns
When, transient error pulse is applied simultaneously to S5 and Q (S7)；In 32ns, transient error pulse is applied simultaneously to S6 and S8.(3)
To node to < SX,SX+3> verifying: in 46ns, transient error pulse applied simultaneously to S1 and S4；In 52ns, to S2 and
S5 applies transient error pulse simultaneously.(4) to node to < SX,SX+4> verifying: in 66ns, S3 and Q (S7) are applied simultaneously
Transient error pulse；In 72ns, transient error pulse is applied simultaneously to S4 and S8.Therefore, in conclusion above node pair
Selection cover 4 whole class nodes pair, thus prove when any two memory node to simultaneously occur transient error overturning, electricity
Lu Junneng makes each memory node original correct logic level back by itself feedback.
Embodiment two
The present invention also provides another latch, and a, Fig. 4 a are shown as the electricity of another latch of the invention referring to fig. 4
Line structure schematic diagram.The latch includes at least: four Muller C cells: MC2, MC4, MC6, MC8；Four by clock control
Muller C cell: MC1, MC3, MC5, MC7；And four transmission gates TG1, TG2, TG3, TG4；Eight Muller C cells
MC1 to MC8 is distributed clockwise according to its footmark sequence and end to end composition loop, and enabling x is 1 to 8 integer, each Muller C
The output end signal Sx of unit is corresponding with its footmark MCx, and the output end signal S1 to S8 of eight Muller C cells is in inverse
Hour hands distribution；The footmark of two input end signals of same Muller C cell is all odd number or is all even number；Four transmission gates
The output end of TG1 to TG4 is sequentially connected signal S1, S7, S5, S3 respectively；Four transmission gates share an input node D.
Preferably, the output node Q of the latch is the output end signal S7 of the Muller C cell MC7 to the present embodiment
Node.
The Muller C cell MC1 to MC8 of the invention is the Muller C cell of two inputs.In Fig. 4 a, the Muller C cell
The output end of MC1 connects an input terminal of the Muller C cell MC8, described in the output end connection of the Muller C cell MC8
One of input terminal of Muller C cell MC7, the output end of the Muller C cell MC7 connect its of the Muller C cell MC6
In an input terminal, the output end of the Muller C cell MC6 connects one of input terminal of the Muller C cell MC5, institute
The output end for stating Muller C cell MC5 connects one of input terminal of the Muller C cell MC4, and the Muller C cell MC4 is defeated
Outlet connects one of input terminal of the Muller C cell MC3, and the output end of the Muller C cell MC3 connects the Muller
One of input terminal of C cell MC2, the output end of the Muller C cell MC2 connect wherein the one of the Muller C cell MC1
A input terminal.
The output end signal Sx of each Muller C cell is corresponding with its footmark MCx in the embodiment of the present invention latch circuit,
If the output end signal of Muller C cell MC1 is S1, the output end signal of Muller C cell MC8 is S8, and Muller C cell MC7's is defeated
End signal is S7 out, and the output end signal of Muller C cell MC6 is S6, and the output end signal of Muller C cell MC5 is S5, Muller C
The output end signal of unit MC4 is S4, and the output end signal of Muller C cell MC3 is S3, the output end signal of Muller C cell MC2
For S2.Preferably, the output node Q of the latch is the section of the output end signal S7 of the Muller C cell MC7 to the present embodiment
Point.The input node of circuit is D.
In the embodiment of the present invention latch circuit, the footmark of two input end signals of the same Muller C cell is same
It for odd number or be all the combination of even number include: input end signal is S1, S3, output end signal S8；Input end signal is S8,
S2, output end signal S7；Input end signal is S7, S1, output end signal S6；Input end signal is S6, S8, output end letter
Number be S5；Input end signal is S5, S7, output end signal S4；Input end signal is S4, S6, output end signal S3；Input
End signal is S3, S5, output end signal S2；Input end signal is S2, S4, output end signal S1.Further, this reality
Two input end signals for applying the same Muller C cell of example are all high level " 1 " or are all low level " 0 ".
As shown in Figure 4 b, Fig. 4 b is shown as the circuit reduction node diagram of the latch of Fig. 4 a.Assuming that S1 and S3 are overturn simultaneously.
Overturning will lead to the overturning of S8 while S1 and S3, since S4 and S6 is not affected, S3 can be restored to it is original just
The correct logic level of true logic level, S2 and S4 can also make S1 be restored to original correct logic level, later, S1 and S3
Recovery can S8 be restored again.Finally, all nodes of circuit are original correct logic level.
In conclusion the invention proposes the latch of two kinds of novel anti-two nodes overturnings, the selection of node pair is contained
4 whole class nodes pair have been covered, have thus been proved when any two memory node to occurring transient error overturning, the equal energy of circuit simultaneously
Make each memory node original correct logic level back by itself feedback, circuit of the invention has anti-two nodes overturning
Function.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (8)
1. a kind of latch, which is characterized in that the latch includes at least:
Four Muller C cells: MC2, MC4, MC6, MC8；Four Muller C cells by clock control: MC1, MC3, MC5, MC7；
And four transmission gates TG1, TG2, TG3, TG4；
Eight Muller C cell MC1 to MC8 enable the x be according to its footmark sequence distribution and end to end composition loop counterclockwise
The output end signal Sx of 1 to 8 integer, each Muller C cell is corresponding with its footmark MCx, and eight Muller C cells
Output end signal S1 to S8 is in distribution counterclockwise；The footmark of two input end signals of same Muller C cell is all odd number or same
For even number；
The output end of four transmission gate TG1 to TG4 is sequentially connected signal S1, S3, S5, S7 respectively；Four transmission gates
Share an input node D.
2. latch according to claim 1, it is characterised in that: the output node Q of the latch is that the Muller C is mono-
The node of the output end signal S7 of first MC7.
3. latch according to claim 2, it is characterised in that: two input end signals of the same Muller C cell
Footmark be all odd number or be all even number combination include: input end signal be S1, S3, output end signal S4；Input terminal letter
Number be S2, S4, output end signal S5；Input end signal is S3, S5, output end signal S6；Input end signal is S4, S6,
Output end signal is S7；Input end signal is S5, S7, output end signal S8；Input end signal is S6, S8, output end signal
For S1；Input end signal is S7, S1, output end signal S2；Input end signal is S8, S2, output end signal S3.
4. latch according to claim 3, it is characterised in that: two input end signals of the same Muller C cell
It is all high level or is all low level.
5. a kind of latch, which is characterized in that the latch includes at least:
Four Muller C cells: MC2, MC4, MC6, MC8；Four Muller C cells by clock control: MC1, MC3, MC5, MC7；
And four transmission gates TG1, TG2, TG3, TG4；
Eight Muller C cell MC1 to MC8 enable the x be according to its footmark sequence distribution and end to end composition loop clockwise
The output end signal Sx of 1 to 8 integer, each Muller C cell is corresponding with its footmark MCx, and eight Muller C cells
Output end signal S1 to S8 is in distribution counterclockwise；The footmark of two input end signals of same Muller C cell is all odd number or same
For even number；
The output end of four transmission gate TG1 to TG4 is sequentially connected signal S1, S7, S5, S3 respectively；Four transmission gates
Share an input node D.
6. latch according to claim 5, it is characterised in that: the output node Q of the latch is that the Muller C is mono-
The node of the output end signal S7 of first MC7.
7. latch according to claim 6, it is characterised in that: two input end signals of the same Muller C cell
Footmark be all odd number or be all even number combination include: input end signal be S1, S3, output end signal S8；Input terminal letter
Number be S8, S2, output end signal S7；Input end signal is S7, S1, output end signal S6；Input end signal is S6, S8,
Output end signal is S5；Input end signal is S5, S7, output end signal S4；Input end signal is S4, S6, output end signal
For S3；Input end signal is S3, S5, output end signal S2；Input end signal is S2, S4, output end signal S1.
8. latch according to claim 7, it is characterised in that: two input end signals of the same Muller C cell
It is all high level or is all low level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910280313.XA CN110166041A (en) | 2019-04-09 | 2019-04-09 | Latch |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111162772A (en) * | 2020-01-15 | 2020-05-15 | 合肥工业大学 | High-performance low-overhead three-point flip self-recovery latch |
| CN111327308A (en) * | 2020-03-02 | 2020-06-23 | 上海华虹宏力半导体制造有限公司 | Latch capable of turning three-bit node |
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| US20110025372A1 (en) * | 2009-07-29 | 2011-02-03 | The Boeing Company | Method and apparatus for reducing radiation and cross-talk induced data errors |
| CN104901676A (en) * | 2015-06-06 | 2015-09-09 | 合肥工业大学 | Latch resistant to single-particle multi-node overturning |
| US20180076797A1 (en) * | 2016-09-15 | 2018-03-15 | Board Of Trustees Of Southern Illinois University On Behalf Of Southern Illinois University Carbonda | Systems and methods for a robust double node upset tolerant latch |
| CN108011628A (en) * | 2017-12-05 | 2018-05-08 | 安徽大学 | A kind of latch of three node of tolerable upset |
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| US20110025372A1 (en) * | 2009-07-29 | 2011-02-03 | The Boeing Company | Method and apparatus for reducing radiation and cross-talk induced data errors |
| CN104901676A (en) * | 2015-06-06 | 2015-09-09 | 合肥工业大学 | Latch resistant to single-particle multi-node overturning |
| US20180076797A1 (en) * | 2016-09-15 | 2018-03-15 | Board Of Trustees Of Southern Illinois University On Behalf Of Southern Illinois University Carbonda | Systems and methods for a robust double node upset tolerant latch |
| CN108011628A (en) * | 2017-12-05 | 2018-05-08 | 安徽大学 | A kind of latch of three node of tolerable upset |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111162772A (en) * | 2020-01-15 | 2020-05-15 | 合肥工业大学 | High-performance low-overhead three-point flip self-recovery latch |
| CN111162772B (en) * | 2020-01-15 | 2022-09-20 | 合肥工业大学 | High-performance low-overhead three-point flip self-recovery latch |
| CN111327308A (en) * | 2020-03-02 | 2020-06-23 | 上海华虹宏力半导体制造有限公司 | Latch capable of turning three-bit node |
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