CN108092660B - Sub-threshold circuit optimization method and system - Google Patents
Sub-threshold circuit optimization method and system Download PDFInfo
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- CN108092660B CN108092660B CN201711484159.5A CN201711484159A CN108092660B CN 108092660 B CN108092660 B CN 108092660B CN 201711484159 A CN201711484159 A CN 201711484159A CN 108092660 B CN108092660 B CN 108092660B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
Abstract
The embodiment of the invention discloses an optimization method of a subthreshold circuit, which comprises the following steps: determining a unit D trigger in the sub-threshold logic gate netlist, wherein the unit D trigger has one-bit data input; grouping the unit D triggers according to rows, wherein the unit D triggers in the group are connected with the same clock signal; and replacing the unit D triggers in the group with multi-bit D triggers to obtain an optimized sub-threshold logic gate netlist, wherein the multi-bit D triggers comprise a plurality of independent unit D trigger main circuits and a clock signal circuit, the clock signal circuit provides clock signals for the independent unit D trigger main circuits, and each unit D trigger main circuit and the clock signal circuit form a unit D trigger respectively. The invention improves the frequency characteristic of the sub-threshold circuit clock network, reduces the power consumption of the clock network, reduces the area of the circuit and further improves the performance of the sub-threshold circuit.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to an optimization method and system of a sub-threshold circuit.
Background
The sub-threshold circuit is a digital logic circuit with the working voltage lower than the threshold voltage of a transistor device, and the dynamic power consumption and the static power consumption of the circuit can be greatly reduced because the circuit works in a sub-threshold region.
However, as integrated circuit technology continues to advance, higher demands are placed on the performance of the circuit, and it is desirable that the power consumption of the circuit be smaller and faster. How to further improve the circuit speed and reduce the power consumption in the design of the sub-threshold circuit is a further problem to be solved in the design of the sub-threshold circuit.
Disclosure of Invention
The invention provides an optimization method and system of a sub-threshold circuit, which can improve the frequency characteristic of the sub-threshold circuit and reduce the power consumption of the sub-threshold circuit.
The invention provides an optimization method of a subthreshold circuit, which comprises the following steps:
determining a unit D trigger in the sub-threshold logic gate netlist, wherein the unit D trigger has one-bit data input;
grouping the unit D triggers, wherein the unit D triggers in the group are connected with the same clock signal;
and replacing the unit D triggers in the group with multi-bit D triggers to obtain an optimized sub-threshold logic gate netlist, wherein the multi-bit D triggers comprise a plurality of independent unit D trigger main circuits and a clock signal circuit, the clock signal circuit provides clock signals for the independent unit D trigger main circuits, and each unit D trigger main circuit and the clock signal circuit form a unit D trigger respectively.
Optionally, the grouping the unit D triggers includes:
establishing a directed graph according to the sub-threshold logic gate netlist, performing signal flow analysis through the directed graph, and determining the sequence of the unit D triggers in the signal flow direction;
the unit D triggers are grouped according to the sequence of the signal flow, and the signal flow directions of the unit D triggers in the group are consistent and are connected with the same clock signal.
Optionally, the unit D flip-flops are grouped by row.
Optionally, the grouping the unit D flip-flops by rows includes:
determining the sub-threshold circuit layout according to the sub-threshold logic gate netlist;
according to the sub-threshold circuit layout, the D triggers on the same row are grouped according to the relative position relation, and meanwhile, the D triggers in the group are connected with the same clock signal.
Optionally, the determining a unit D flip-flop in the sub-threshold logic gate netlist includes:
a single-site D flip-flop is designated in a logic gate cell library as a specific basic cell, and a logic cell referencing the specific basic cell in the sub-threshold logic gate netlist is a single-site D flip-flop.
Optionally, the determining a unit D flip-flop in the sub-threshold logic gate netlist includes:
according to the logic description, a basic unit of a unit D trigger is determined from a unit library used by a sub-threshold logic gate netlist, and a logic unit of the basic unit is referred to as the unit D trigger in the sub-threshold netlist.
Optionally, after replacing the single-bit D flip-flop in the group with the multi-bit D flip-flop, the method further includes: and a buffer unit is inserted into a clock signal input end of the multi-bit D flip-flop, wherein the input end of the buffer unit is connected with a clock signal provided by the clock signal circuit, and the output end of the buffer unit is connected with a clock input signal end of the multi-bit D flip-flop.
Optionally, after the clock signal input terminal of the multi-bit D flip-flop is inserted into the buffer unit, the method further includes: the device size within the buffer cell is optimized.
In addition, the invention also provides an optimization system of the subthreshold circuit, which comprises the following components:
optionally, the unit D trigger determining unit is configured to determine a unit D trigger in the sub-threshold logic gate netlist, where the unit D trigger has one bit of data input;
the grouping unit is used for grouping the unit D triggers, and the unit D triggers in the group are connected with the same clock signal;
and the replacing unit is used for replacing the unit D triggers in the group with the multi-bit D triggers so as to obtain the optimized sub-threshold logic gate netlist, wherein the multi-bit D triggers comprise a plurality of independent unit D trigger main circuits and a clock signal circuit, the clock signal circuit provides clock signals for the independent unit D trigger main circuits, and each unit D trigger main circuit and the clock signal circuit form one unit D trigger respectively.
Optionally, the grouping unit includes:
the directed graph analysis unit is used for establishing a directed graph according to the sub-threshold logic gate network table, performing signal flow analysis through the directed graph and determining the sequence of each unit D trigger in the signal flow direction;
and the signal flow grouping unit is used for grouping the unit D triggers according to the sequence of the signal flow, and the signal flow directions of the unit D triggers in the group are consistent and are connected with the same clock signal.
Optionally, in the grouping unit, the unit D flip-flops are grouped by rows, and the grouping unit includes:
the layout unit is used for determining the layout of the sub-threshold circuit according to the sub-threshold logic gate netlist;
and the layout grouping unit is used for grouping the D triggers on the same row according to the relative position relation according to the sub-threshold circuit layout, and meanwhile, the D triggers in the group are connected with the same clock signal.
Optionally, in the unit D flip-flop determination unit, the unit D flip-flop is specified in the logic gate cell library as a specific basic cell, and the logic cell in the sub-threshold logic gate netlist that refers to the specific basic cell is the unit D flip-flop.
Optionally, in the unit D trigger determination unit, a basic unit of the unit D trigger is determined from a cell library used in a sub-threshold logic gate netlist according to a logic description, and a logic unit referring to the basic unit in the sub-threshold netlist is the unit D trigger.
Optionally, the method further comprises: and the buffer insertion unit is used for inserting a buffer unit into a clock signal input end of the multi-bit D flip-flop, wherein the input end of the buffer unit is connected with a clock signal provided by the clock signal circuit, and the output end of the buffer unit is connected with a clock input signal end of the multi-bit D flip-flop.
Optionally, the method further comprises: and the buffer optimization unit is used for optimizing the device size in the buffer unit.
According to the optimization method and system of the sub-threshold circuit provided by the embodiment of the invention, in the sub-threshold logic gate netlist, a plurality of unit D triggers are used for replacing a plurality of unit D triggers, a plurality of unit D trigger main circuits in the multi-bit D triggers share one clock signal circuit, and the scale of the clock network is reduced, so that the load capacitance of the sub-threshold circuit clock network can be reduced, the frequency characteristic of the sub-threshold circuit clock network is improved, the power consumption of the clock network is reduced, the area of the circuit is reduced, and the performance of the sub-threshold circuit is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a flowchart illustrating a method for optimizing a sub-threshold circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram illustrating a method for optimizing a sub-threshold circuit, in which a single-bit D flip-flop in a group is replaced with a multi-bit D flip-flop according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating a structure of a unit D flip-flop in the method for optimizing a sub-threshold circuit according to the embodiment of the present invention;
fig. 4 is a schematic structural diagram of an optimization system of a sub-threshold circuit according to an embodiment of the present invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The sub-threshold circuit means that the operating voltage of the circuit is near or below the threshold of a transistor device, and since the power consumption of the circuit is proportional to the square of the voltage in a digital circuit, the sub-threshold circuit can effectively reduce the power consumption of the circuit. In electronic design automation, a logic gate netlist refers to a description mode for describing a digital circuit connection condition by using a basic logic gate and/or a higher-level design unit, which transfers information on circuit connection, and is usually described by using a hardware description language, and a layout of an integrated circuit can be generated according to the logic gate netlist. The sub-threshold logic gate netlist refers to a logic gate netlist for designing a sub-threshold logic circuit, wherein a logic gate is designed for sub-threshold operation of a device.
In order to further increase the operating speed of the sub-threshold circuit, the present invention provides an optimization method of the sub-threshold circuit, which is shown in fig. 1 and includes:
s01, determining a unit D trigger in the sub-threshold logic gate netlist, wherein the unit D trigger has one-bit data input;
s02, grouping the unit D triggers, wherein the unit D triggers in the group are connected with the same clock signal;
and S03, replacing the unit D triggers in the group with multi-bit D triggers to obtain an optimized sub-threshold logic gate netlist, wherein the multi-bit D triggers comprise a plurality of independent unit D trigger main circuits and a clock signal circuit, the clock signal circuit provides clock signals for the independent unit D trigger main circuits, and each unit D trigger main circuit and the clock signal circuit form a unit D trigger respectively.
In the embodiment of the invention, a plurality of unit D triggers are replaced by a plurality of unit D triggers, a plurality of unit D trigger main circuits in the multi-bit D triggers share one clock signal circuit, and the scale of a clock network is reduced, so that the load capacitance of a sub-threshold circuit clock network can be reduced, the frequency characteristic of the sub-threshold circuit clock network is improved, the power consumption of the clock network is reduced, the area of the circuit is reduced, and the performance of the sub-threshold circuit is further improved.
In order to better understand the technical solution and the technical effects of the present invention, the following detailed description will be given with reference to specific examples.
At step S01, a unit D flip-flop in the sub-threshold logic gate netlist is determined, the unit D flip-flop having one bit of data input and output.
The optimization method can be carried out in electronic design automation software, and firstly, the sub-threshold logic gate netlist to be optimized can be loaded into the software.
In the embodiment of the present invention, the unit D flip-flop refers to a D flip-flop having a single data bit input and two output states, which is an information storage device having two stable states, "0" and "1", referred to herein as a unit D flip-flop for convenience of description and distinction from the multi-bit D flip-flop in the present application, each of which includes a logic circuit, a main storage latch, a main-slave transfer circuit, a slave storage latch, a data output driving circuit, and a clock signal circuit, for convenience of description, in the present application, the logic circuit, the main memory latch, the main-slave transfer circuit, the slave memory latch, the data output driving circuit, and the like are referred to as a unit D flip-flop main circuit, these circuits output two states of "0" and "1" as triggered by a clock signal output from a clock circuit.
When determining the unit D trigger in the sub-threshold logic gate netlist, various methods can be adopted for implementation. In some embodiments, a unit-D flip-flop may be designated in a logic gate cell library as a particular base cell, and the logic cell in the sub-threshold logic gate netlist that references the base cell is a unit-D flip-flop. The logic gate cell library is a cell library used for designing the netlist, various basic cells are arranged in the cell library, and when a circuit is designed, the basic cells are quoted from the cell library according to the design requirement, and the connection relation among the cells is determined, so that the netlist is generated. Therefore, before generating the netlist, the unit D flip-flop used may be specified in the cell library, and when specifying, the basic cell may be described by a specific name, or the name used by the basic cell may be listed in a specific query list, and when searching, the named basic cells are all used as the unit D flip-flops, so that when generating the netlist, the specified unit D flip-flop is referred to, and by searching for a specific reference, the unit D flip-flop may be determined from the netlist. The method is simple, high in execution efficiency and capable of rapidly determining the unit D trigger from the sub-threshold logic gate netlist.
In other embodiments, a basic cell of a unit D flip-flop may be determined from a cell library used in a sub-threshold logic gate netlist according to a logic description, and a logic unit referring to the basic cell in the sub-threshold netlist is the unit D flip-flop.
All basic cells in a cell library used by the netlist can be traversed, whether the cells are unit D triggers or not is judged through logic description of the basic cells, so that the basic cells of the unit D triggers are determined in the cell library, and then the logic cells which refer to the basic cells are determined to be the unit D triggers from the logic gate netlist. The method also determines the basic unit of the unit D trigger from the unit library, is simple to implement, has high execution efficiency, and can quickly determine the unit D trigger from the sub-threshold logic gate netlist.
Of course, in other embodiments, the unit D flip-flop may also be determined from the netlist according to the logic description by traversing the sub-threshold logic gate netlist, and this method needs to traverse the entire netlist for determination, which is inefficient in execution.
Next, in step S02, the unit D flip-flops are grouped, and the unit D flip-flops in the group are connected to the same clock signal.
In this step, the unit D flip-flops are grouped, and the grouping may be performed in accordance with an appropriate method. The grouping can be done according to the signal stream or according to the rows.
In some embodiments, the packets may be grouped by signal flow path. Specifically, the method comprises the following steps: establishing a directed graph according to the sub-threshold logic gate netlist, performing signal flow analysis through the directed graph, and determining the sequence of the unit D trigger in the signal flow direction; the unit D triggers are grouped according to the sequence of the signal flow, and the signal flow directions of the unit D triggers in the group are consistent and are connected with the same clock signal.
The sub-threshold logic gate network table comprises the connection relation of logic gates and the input and output attributes of logic gate ports, a directed graph can be established through the information, signal flow analysis can be carried out by using the directed graph, the direction of the unit D trigger on the signal flow is determined according to the signal direction, and the unit D triggers are grouped according to the signal flow direction, so that after the grouping, the signal flow directions of the unit D triggers in the group are consistent and the same clock signal is connected.
In other embodiments, the grouping may also be in a relative positional relationship. Specifically, the method comprises the following steps: determining the sub-threshold circuit layout according to the sub-threshold logic gate netlist; according to the sub-threshold circuit layout, the D triggers on the same row are grouped according to the relative position relation, and meanwhile, the D triggers in the group are connected with the same clock signal.
In this embodiment, the unit D flip-flops in each group belong to the same row, but it is understood that the unit D flip-flops in the same row may be divided into one or more groups, and the unit D flip-flops in the group are all connected to the same clock signal, as necessary.
According to the netlist, the layout of the circuit, that is, the layout of the relative positions of the cells in the circuit, can be determined by means of layout software, and according to the layout, the unit D flip-flops on the same row can be grouped according to the relative position relationship, for example, a row is divided into two parts, the unit D flip-flops in each part form a group, which is only an example here, and can be grouped according to the number of specific unit D flip-flops in each row and the like, the unit D flip-flops in each row can be divided into one or more groups, and at the same time, the D flip-flops in each group are connected with the same clock signal.
Then, in step S03, the unit D flip-flops in the group are replaced with multi-bit D flip-flops to obtain an optimized sub-threshold logic gate netlist, where the multi-bit D flip-flop includes a plurality of independent unit D flip-flop main circuits and a clock signal circuit, the clock signal circuit provides a clock signal for the plurality of independent unit D flip-flop main circuits, and each unit D flip-flop main circuit and the clock signal circuit respectively form a unit D flip-flop.
In the implementation of the present invention, the multi-bit D flip-flop is relative to the unit D flip-flop, and referring to fig. 2, an example in which a group of two unit D flip-flops is replaced with a two-bit D flip-flop is shown, where diagram (a) is a schematic diagram of a group of two unit D flip-flops, diagram (B) is a schematic diagram of a two-bit D flip-flop, and in this example group, as shown in diagram (a), each unit D flip-flop includes a respective unit D flip-flop main circuit and a clock signal circuit, including a first unit D flip-flop composed of a first unit D flip-flop main circuit 110 and a first clock signal circuit 112, and a second unit D flip-flop composed of a second unit D flip-main circuit 120 and a second clock signal circuit 122, and the first clock signal circuit 112 and the second clock signal circuit 122 are connected to the same clock signal clk. As shown in fig. B, the two-bit D flip-flop includes two unit D flip-flop main circuits 110 and 120 and a clock signal circuit 130, the clock signal circuit 130 is a shared clock circuit of the two unit D flip-flop main circuits 110 and 120, and each unit D flip-flop main circuit 110 and 120 may respectively form a unit D flip-flop with the shared clock signal circuit 130. The unit D flip-flop circuit is a circuit capable of outputting "0" and "1" states in response to a trigger signal output from a clock signal circuit, and as shown in fig. 3, each unit D flip-flop main circuit 110 mainly includes: logic circuits, main storage latches, master-slave transfer circuits, slave storage latches, data output driver circuits, and the like.
It can be understood that the connection relationship of the input and the output of each unit D trigger main circuit in the multi-bit D trigger is still consistent with the input and output connection relationship of the unit D trigger, and each input and output of the unit D trigger main circuit corresponds to the input and output of one unit D trigger.
In this way, a plurality of unit D flip-flops in each row are replaced with a plurality of multi-bit D flip-flops to obtain an optimized sub-threshold logic gate netlist, which can be further used for subsequent layout design and optimization. Through replacement, the load capacitance of the sub-threshold circuit clock network can be reduced, so that the frequency characteristic of the sub-threshold circuit clock network is improved, the power consumption of the clock network is reduced, the area of the circuit is reduced, and the performance of the sub-threshold circuit is further improved.
Further, the method can further include a buffer unit insertion step, specifically including: the circuit comprises a clock signal circuit, a buffer unit and a multi-bit D flip-flop, wherein the clock signal circuit is used for providing a clock signal for the multi-bit D flip-flop, the input end of the buffer unit is connected with the clock signal provided by the clock signal circuit, and the output end of the buffer unit is connected with the clock input signal end of the multi-bit D flip-flop.
That is, a buffer unit is added in front of a clock input signal end of the multi-bit D flip-flop, so that a clock signal provided by a clock signal circuit is provided to the clock input signal end of the multi-bit D flip-flop after passing through the buffer unit, and the clock input signal end of the multi-bit D flip-flop, that is, each unit D in the multi-bit D flip-flop, triggers a main circuit to connect with the clock input signal end of the clock signal. Thus, the time delay function of the clock signal can be realized, and the time of the clock signal reaching the clock signal input end of the multi-bit flip-flop is further optimized.
Then, further, optimization of the device size in the buffer unit can also be performed. Therefore, the circuit speed performance is improved, the circuit has a smaller area, and the integration level of the circuit is improved. In optimizing the device size of the variable threshold inverter, a suitable optimization algorithm, such as a simulated annealing algorithm or a genetic algorithm, may be used for optimization. After the size optimization, an optimized sub-threshold logic gate netlist is further obtained.
The above detailed description of the optimization method according to the embodiment of the present invention, and in addition, the present invention further provides a corresponding optimization system for implementing the method, which is shown in fig. 4 and includes:
a unit D trigger determining unit 210, configured to determine a unit D trigger in the sub-threshold logic gate netlist, where the unit D trigger has one bit of data input;
a grouping unit 220, configured to group the unit D flip-flops, where the unit D flip-flops in the group are connected to the same clock signal;
and a replacing unit 230, configured to replace a unit D flip-flop in the group with a multi-bit D flip-flop to obtain an optimized sub-threshold logic gate netlist, where the multi-bit D flip-flop includes a plurality of independent unit D flip-flop main circuits and a clock signal circuit, the clock signal circuit provides a clock signal for the plurality of independent unit D flip-flop main circuits, and each unit D flip-flop main circuit and the clock signal circuit form a unit D flip-flop respectively.
Further, the grouping unit 220 includes:
the directed graph analysis unit is used for establishing a directed graph according to the sub-threshold logic gate network table, performing signal flow analysis through the directed graph and determining the sequence of each unit D trigger in the signal flow direction;
and the signal flow grouping unit is used for grouping the unit D triggers according to the sequence of the signal flow, and the signal flow directions of the unit D triggers in the group are consistent and are connected with the same clock signal.
Further, in the grouping unit, unit D flip-flops are grouped by rows.
Further, the grouping unit 220 includes:
the layout unit is used for determining the layout of the sub-threshold circuit according to the sub-threshold logic gate netlist;
and the layout grouping unit is used for grouping the D triggers on the same row according to the relative position relation according to the sub-threshold circuit layout, and meanwhile, the D triggers in the group are connected with the same clock signal.
Further, in the unit D flip-flop determination unit 210, a unit D flip-flop is specified in the logic gate cell library as a specific basic cell, and a logic cell in the sub-threshold logic gate netlist referring to the specific basic cell is a unit D flip-flop.
Further, in the unit D trigger determining unit 210, a basic unit of the unit D trigger is determined from a cell library used by the sub-threshold logic gate netlist according to the logic description, and the logic unit referring to the basic unit in the sub-threshold netlist is the unit D trigger.
Further, still include: and the buffer insertion unit is used for inserting a buffer unit into a clock signal input end of the multi-bit D flip-flop, wherein the input end of the buffer unit is connected with a clock signal provided by the clock signal circuit, and the output end of the buffer unit is connected with a clock input signal end of the multi-bit D flip-flop.
Further, still include: and the buffer optimization unit is used for optimizing the device size in the buffer unit.
The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present teachings, or modify equivalent embodiments to equivalent variations, without departing from the scope of the present teachings, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, they are described in a relatively simple manner, and reference may be made to some descriptions of method embodiments for relevant points. The above-described system embodiments are merely illustrative, wherein the modules or units described as separate parts may or may not be physically separate, and the parts displayed as modules or units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Claims (5)
1. A method for optimizing a subthreshold circuit, comprising:
determining a unit D trigger in the sub-threshold logic gate netlist, wherein the unit D trigger has one-bit data input;
establishing a directed graph according to the sub-threshold logic gate netlist, performing signal flow analysis through the directed graph, determining the sequence of each unit D trigger in the signal flow direction, grouping the unit D triggers according to the sequence of the signal flow, wherein the unit D triggers in a group have the same signal flow direction and are connected with the same clock signal; or determining the sub-threshold circuit layout according to the sub-threshold logic gate netlist, grouping the D triggers on the same row according to the relative position relationship according to the sub-threshold circuit layout, and simultaneously connecting the D triggers in the group with the same clock signal;
and replacing the unit D triggers in the group with multi-bit D triggers to obtain an optimized sub-threshold logic gate netlist, wherein the multi-bit D triggers comprise a plurality of independent unit D trigger main circuits and a clock signal circuit, the clock signal circuit provides clock signals for the independent unit D trigger main circuits, and each unit D trigger main circuit and the clock signal circuit form a unit D trigger respectively.
2. The optimization method of claim 1, wherein the determining unit D flip-flops in the sub-threshold logic gate netlist comprises:
a single-site D flip-flop is designated in a logic gate cell library as a specific basic cell, and a logic cell referencing the specific basic cell in the sub-threshold logic gate netlist is a single-site D flip-flop.
3. The optimization method of claim 1, wherein the determining unit D flip-flops in the sub-threshold logic gate netlist comprises:
according to the logic description, a basic unit of a unit D trigger is determined from a unit library used by a sub-threshold logic gate netlist, and a logic unit referring to the basic unit in the sub-threshold logic gate netlist is the unit D trigger.
4. The optimization method of claim 1, wherein after replacing the single-bit D flip-flops within the group with multi-bit D flip-flops, further comprising:
and a buffer unit is inserted into a clock signal input end of the multi-bit D flip-flop, wherein the input end of the buffer unit is connected with a clock signal provided by the clock signal circuit, and the output end of the buffer unit is connected with a clock input signal end of the multi-bit D flip-flop.
5. An optimization system for a sub-threshold circuit, comprising:
the unit D trigger determining unit is used for determining a unit D trigger in the sub-threshold logic gate netlist, and the unit D trigger is provided with one-bit data input;
the grouping unit is used for establishing a directed graph according to the sub-threshold logic gate network table, performing signal flow analysis through the directed graph, determining the sequence of each unit D trigger in the signal flow direction, and grouping the unit D triggers according to the sequence of the signal flow, wherein the unit D triggers in the group have the same signal flow direction and are connected with the same clock signal source; or according to the sub-threshold circuit layout, grouping the D triggers on the same line according to the relative position relation, and simultaneously connecting the D triggers in the group with the same clock signal source;
and the replacing unit is used for replacing the unit D triggers in the group with the multi-bit D triggers so as to obtain the optimized sub-threshold logic gate netlist, wherein the multi-bit D triggers comprise a plurality of independent unit D trigger main circuits and a clock signal circuit, the clock signal circuit provides clock signals for the independent unit D trigger main circuits, and each unit D trigger main circuit and the clock signal circuit form one unit D trigger respectively.
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| CN105897221A (en) * | 2015-02-13 | 2016-08-24 | 三星电子株式会社 | Multi-bit flip-flops and scan chain circuits |
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| TW200534585A (en) * | 2004-04-09 | 2005-10-16 | Samsung Electronics Co Ltd | High speed flip-flops and complex gates using the same |
| WO2012125241A2 (en) * | 2011-03-16 | 2012-09-20 | Analog Devices, Inc. | Clock gated power saving shift register |
| CN105591645A (en) * | 2014-10-22 | 2016-05-18 | 京微雅格（北京）科技有限公司 | Multistage serial-parallel conversion circuit |
| CN105897221A (en) * | 2015-02-13 | 2016-08-24 | 三星电子株式会社 | Multi-bit flip-flops and scan chain circuits |
| CN106527575A (en) * | 2016-10-21 | 2017-03-22 | 东南大学—无锡集成电路技术研究所 | Activity similarity based trigger grouping clock gating method |
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