CN105097016B - A kind of SRAM output latch circuits - Google Patents
A kind of SRAM output latch circuits Download PDFInfo
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- CN105097016B CN105097016B CN201410216693.8A CN201410216693A CN105097016B CN 105097016 B CN105097016 B CN 105097016B CN 201410216693 A CN201410216693 A CN 201410216693A CN 105097016 B CN105097016 B CN 105097016B
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Abstract
The present invention provides a kind of SRAM output latch circuits, and the SRAM output latch circuits include at least：For the sense amplifier of amplified signal, for producing the presetting bit signal generating circuit of presetting bit signal and being connected to the RS latch cicuits of the sense amplifier and the presetting bit signal generating circuit output terminal；The presetting bit signal generating circuit makes the RS latch export signal " 1 " in advance, and when the input signal of the sense amplifier is " 0 ", the output signal of the RS latch is signal " 0 " by signal " 1 " saltus step；When the input signal of the sense amplifier is " 1 ", the output signal of the RS latch remains signal " 1 ".The SRAM output latch circuits of the present invention reduce the time of output " 1 ", achieve the purpose that to reduce SRAM overall access times, and then lift the performance of SRAM by increasing a presetting bit signal.
Description
Technical field
The present invention relates to technical field of semiconductor memory, more particularly to a kind of SRAM output latch circuits.
Background technology
SRAM (Static Random Access Memory) i.e. Static RAM, it is that one kind has static deposit
Take the memory of function, it is not necessary to which refresh circuit can preserve the data of its storage inside, and fast with speed, work efficiency height etc. is excellent
Point.SRAM generally comprises memory cell array and peripheral circuit, wherein, memory cell array is the core of SRAM, for storing
Data, are arranged in rows by storage unit and formed；Peripheral circuit includes address decoder, and sense amplifier, control circuit, delays
Punching/drive circuit；Storage unit wherein in control circuit control address decoder select storage unit array, and by the unit
The data of middle storage are amplified by sense amplifier to be read.
It is SRAM output latch circuits 1 of the prior art as shown in Figure 1, the SRAM output latch circuits 1 include spirit
Quick amplifier 11 and RS latch cicuits 12, the sense amplifier 11 are double-width grinding both-end export structure, its input terminal connects
One group of bit line (Bit line)：First bit line BL and the second bit line BLB, the first bit line BL and the second bit line BLB transmission
Signal is one group of data-signal negated, and the data-signal is read out and inputs institute from the memory cell array of SRAM
State sense amplifier 11.Due to storage unit finite capacity, so the performance of its output voltage is small-signal, the sense amplifier
11 are amplified to rapidly the small-signal received from bit line signal and the output of full voltage range, it is not necessary to the small letter in equipotential line
Number the logic gate that can trigger next stage is gone straight down to, then carry out the signal processing of next step, access speed can be improved with this.
The RS latch cicuits 12 are connected to the output terminal of the sense amplifier 11, for the letter exported to the sense amplifier 11
Number latched.The SRAM output latch circuits 1 can complete the amplification and output to reading signal in memory cell array.
But the SRAM output latch circuits of this structure have a problem that, when the signal of the first bit line BL inputs is
" 0 ", the signal of the second bit line BLB inputs is when be " 1 ", and input signal relatively and obtains signal " 0 " after amplification, and signal " 0 " is passed
The defeated reset terminal to RS latch cicuits, due to the characteristic of NAND gate, has " 0 " to go out " 1 ", so no matter why another signal is worth,
NAND gate output is " 1 ", then the value exported by inverter output Q is " 0 "；But when the signal of the first bit line BL inputs
For " 1 ", when the signal of the second bit line BLB inputs be " 0 ", input signal relatively and obtains signal " 1 ", signal " 1 " quilt after amplification
Be transferred to the reset terminal of RS latch cicuits after amplification, the signal " 1 " of reset terminal it is to be output must etc. set end signal " 0 " it is logical
NAND gate output " 1 " is crossed, which is input to NAND gate by cross-couplings together with the signal " 1 " of reset terminal again, then multiple
The signal " 1 " at position end needs the signal " 0 " of set end to coordinate realization output.Due to RS latch cicuit characteristics, transmission signal " 1 "
Time grows 1~2 grade of gate delay time than the time of transmission signal " 0 ".
The waveform diagram of the SRAM output latch circuits of said structure is illustrated in figure 2, when making for sense amplifier 11
Can signal SA_Enable effectively (from low transition to high level) when, sense amplifier 11 is by the data on the first bit line BL
It is compared with the data on the second bit line BLB, and is exported after comparative result is amplified to the first output terminal DOUT, comparative result
Inverted signal export to the second output terminal DOUTB, final data passes through the output terminal Q outputs of RS latch cicuits, output signal " 1 "
When time delay it is longer.
As CMOS technology size reduction is even lower to 40nm, influences of the SRAM to system design performance is increasingly heavier
Will, SRAM has become the critical path of system for restricting design sequential.Therefore, for any small in SRAM access times
Lifting all seems increasingly important, how to reduce the time of the time, especially transmission signal " 1 " of SRAM data transmission, and lifting is whole
The access time of a SRAM is to optimize the performance of SRAM, it has also become one of those skilled in the art's urgent problem to be solved.
The content of the invention
In view of the foregoing deficiencies of prior art, it is an object of the invention to provide a kind of SRAM output latch circuits,
Access time for solving the problems, such as SRAM in the prior art is long.
In order to achieve the above objects and other related objects, the present invention provides a kind of SRAM output latch circuits, the SRAM
Output latch circuit includes at least：
Sense amplifier, presetting bit signal generating circuit, RS latch cicuits；
The sense amplifier is connected to SRAM memory cell, for the data letter that will be exported in the SRAM memory cell
Amplify after number, easy to identification of the subsequent conditioning circuit to the data-signal；
The presetting bit signal generating circuit produces presetting bit signal, the RS latch cicuits is exported high level letter in advance
Number；
The RS latch cicuits are connected to the sense amplifier and the presetting bit signal generating circuit, for latch and
Transmit the signal of the sense amplifier output.
Preferably, the presetting bit signal generating circuit includes the first NAND gate of the first phase inverter and two inputs, described
The output terminal of first phase inverter is connected to an input terminal of first NAND gate, the input terminal of first phase inverter and institute
Another input terminal for stating the first NAND gate is connected.
Preferably, the presetting bit signal generating circuit makes the RS latch export signal " 1 " in advance, when described sensitive
When the input signal of amplifier is " 0 ", the output signal of the RS latch is signal " 0 " by signal " 1 " saltus step；When the spirit
When the input signal of quick amplifier is " 1 ", the output signal of the RS latch remains signal " 1 ".
Preferably, the input terminal of the sense amplifier connects the bit line that one group of data-signal negates.
Preferably, the enable signal of the sense amplifier is high effectively.
Preferably, the input signal of the presetting bit signal generating circuit is clock signal.
Preferably, the presetting bit signal is low level pulse.
Preferably, the RS latch cicuits include the second NAND gate, the 3rd NAND gate and the second phase inverter, described second with
NOT gate and the input terminal and output terminal of the 3rd NAND gate difference cross-couplings, second phase inverter are connected to the described 3rd
The output terminal of NAND gate.
It is highly preferred that second NAND gate and the 3rd NAND gate are two input nand gates.
Preferably, the output terminal of the sense amplifier is connected to the reset terminal of the RS latch cicuits, the presetting bit
The output terminal of signal generating circuit is connected to the set end of the RS latch cicuits.
As described above, the SRAM output latch circuits of the present invention, have the advantages that：
The SRAM output latch circuits of the present invention reduce the time of output " 1 ", reach by increasing a presetting bit signal
The purpose of SRAM overall access times is reduced, and then lifts the performance of SRAM.
Brief description of the drawings
Fig. 1 is shown as SRAM output latch circuits schematic diagram of the prior art.
Fig. 2 is shown as the waveform diagram of SRAM output latch circuits of the prior art.
Fig. 3 is shown as the SRAM output latch circuit schematic diagrames in the present invention.
Fig. 4 is shown as the waveform diagram of the SRAM output latch circuits in the present invention.
Fig. 5 is shown as the waveform diagram of the presetting bit signal generating circuit in the present invention.
Component label instructions
1 SRAM output latch circuits
11 sense amplifiers
12 RS latch cicuits
2 SRAM output latch circuits
21 sense amplifiers
22 presetting bit signal generating circuits
221 first phase inverters
222 first NAND gates
23 RS latch cicuits
231 second NAND gates
232 the 3rd NAND gates
233 second phase inverters
The enable signal of SA_Enable sense amplifiers
The first bit lines of BL
The second bit lines of BLB
The first output terminals of OUT
The second output terminals of OUTB
The output terminal of Q RS latch cicuits
SET presetting bit signals
Int_clk clock signals
Int_clkb clock signals
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Refer to Fig. 3~Fig. 5.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, then only the display component related with the present invention rather than package count during according to actual implementation in schema
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
As shown in figure 3, the present invention provides a kind of SRAM output latch circuits, the SRAM output latch circuits 2 at least wrap
Include：
Sense amplifier 21, presetting bit signal generating circuit 22, RS latch cicuits 23；
The sense amplifier 21 is connected to SRAM memory cell, for the data that will be exported in the SRAM memory cell
Signal amplifies output more afterwards, in order to identification of the subsequent conditioning circuit to the data-signal, the input of the sense amplifier 21
The bit line that end one group of data-signal of connection negates, the sense amplifier 21 are controlled by enable signal SA_Enable, and enabled letter
Number SA_Enable high is effective.
As shown in figure 3, the sense amplifier 21 is double-width grinding Single-end output structure, its input terminal is connected to SRAM and deposits
One group of bit line (Bit line) of storage unit, as shown in figure 3, respectively the first bit line BL and the second bit line BLB, described first
The signal of line BL and the second bit line BLB transmission is one group of data-signal negated read out from SRAM memory cell.
SA_Enable is the enable signal of the sense amplifier 21, as shown in figure 4, when the sense amplifier 21
When enable signal SA_Enable saltus steps are high level, the sense amplifier 21 is started to work.
The first bit line BL and the second bit line BLB data-signals transmitted are compared simultaneously by the sense amplifier 21
Comparative result is amplified and is exported, the signal of the amplification of sense amplifier 21 output is the signal of full voltage range, after being lifted
Reading speed of the continuous circuit to signal.
Data in data on first bit line BL and the second bit line BLB are compared by the sense amplifier 21, and
Output is to the first output terminal DOUT after comparative result is amplified, and the inverted signal of comparative result is exported to the second output terminal DOUTB, such as
Shown in Fig. 4, DOUT and DOUTB negate signal for one group.In the present embodiment, as shown in figure 3, the sense amplifier 21 it is defeated
Outlet is the first output terminal DOUT, and the second output terminal DOUTB of the sense amplifier 21 is unreferenced in subsequent conditioning circuit.
The presetting bit signal generating circuit 22 is connected to the input terminal of the RS latch cicuits 23, for producing the RS
The presetting bit signal SET of latch cicuit 23.
The presetting bit signal generating circuit 22 includes the first NAND gate 222 of the first phase inverter 221 and two inputs, described
The output terminal of first phase inverter 221 is connected to an input terminal of first NAND gate 222, first phase inverter 221
Input terminal is connected with another input terminal of first NAND gate 222.
As shown in figure 3, the output terminal of first phase inverter 221 is connected to the B ends of first NAND gate 222, it is described
The input terminal of first phase inverter 221 is connected with the A ends of first NAND gate 222, forms the presetting bit signal generating circuit
22, its input signal is clock signal Int_clk.
The presetting bit signal generating circuit 22 is low level pulse generation circuit, is illustrated in figure 5 the presetting bit letter
The waveform diagram of number generation circuit 22, clock signal Int_clk and Int_clkb do NAND operation, and Int_clkb is clock letter
Inverted signal after number Int_clk delay.The input of NAND gate complete " 1 " output is " 0 ", and the output of remaining situation is " 1 ", so
The presetting bit signal SET gone out is low level pulse one by one.
The RS latch cicuits 23 are connected to the defeated of the sense amplifier 21 and the presetting bit signal generating circuit 22
Outlet, the RS latch cicuits 23 are used to latching and transmitting the data-signal that the sense amplifier 21 exports.Wherein, the spirit
The output terminal of quick amplifier 21 is connected to the reset terminal of the RS latch cicuits 23, the presetting bit signal generating circuit 22 it is defeated
Outlet is connected to the set end of the RS latch cicuits 23.
The RS latch cicuits 23 can be realized by different circuit structures, and RS can be built using NAND gate and latches electricity
Road, can also realize identical RS latch functions by nor gate, and the RS latch cicuits 23 can any can realize that RS locks
The circuit of function is deposited, structure is unlimited.
In the present embodiment, the RS latch cicuits 23 are formed using NAND gate, as shown in figure 3, the RS latch cicuits
23 include the second NAND gate 231, the 3rd NAND gate 232 and the second phase inverter 233, second NAND gate 231 and the described 3rd
NAND gate 232 is the input terminal and output terminal of two input nand gates, second NAND gate 231 and the 3rd NAND gate 232
Cross-couplings, second phase inverter 233 are connected to the output terminal of the 3rd NAND gate 232 respectively.Wherein, described second with
Another input terminal of NOT gate 231 is the set end of the RS latch cicuits 23, and another of the 3rd NAND gate 232 inputs
Hold as the reset terminal of the RS latch cicuits 23.
The operation principle of the SRAM output latch circuits 2 of the present invention is as follows：
When SRAM detects effective clock signal Int_clk, clock signal Int_clk is input to the presetting bit letter
Number generation circuit 22, does NAND operation by clock signal Int_clk and its inverted signal Int_clkb after postponing, produces one
Low level pulse signal SET.
As shown in figure 5, by the NAND operation of Int_clk and Int_clkb signals, input signal obtains at the same time when being " 1 "
Signal " 0 ", other situations obtain signal " 1 ", and presetting bit signal SET is cycle equal low level pulse signal.
The low level pulse signal SET that the presetting bit signal generating circuit 22 exports is transferred to the RS latch cicuits
23 set end, as presetting bit signal, low level pulse signal SET exports " 1 " by the second NAND gate 231, the signal " 1 "
The output terminal Q of the RS latch cicuits 23 is output to by the 3rd NAND gate 232 and the second phase inverter 233 again, the RS is latched
The output terminal Q of circuit 23 is by set.
As shown in figure 4, when presetting bit signal SET jumps to low level from high level, the RS latch cicuits 23 it is defeated
The subsequent saltus steps of outlet Q are signal " 1 ", and set is completed, before starting from data transfer due to the set signal, because referred to herein as preset
Position signal.
Since the presetting bit signal SET is low level pulse, the time that low level maintains is shorter, when the RS is latched
For the output terminal Q of circuit 23 by after set, the presetting bit signal SET revocations, revert to high level.
As shown in figure 4, presetting bit signal SET the RS latch cicuits 23 output terminal Q by set after, from low level
High level is returned in saltus step.
The enable signal SA_Enable of the sense amplifier 21 works (from low transition to high level), the spirit
Quick amplifier 21 is started to work, and sense amplifier 21 will transmit in the data transmitted on first bit line BL and the second bit line BLB
Data are compared, and are exported after comparative result is amplified defeated to the first output terminal DOUT, the inverted signal of the first output terminal DOUT
Go out to the second output terminal DOUTB, as shown in figure 3, in the present embodiment, DOUTB is not by subsequent conditioning circuit application, therefore signal does not draw
Go out.
When the data on the first bit line BL are less than the data on the second bit line BLB, the first output terminal DOUT outputs are compared
As a result " 0 "；When the data on the first bit line BL are more than the data on the second bit line BLB, the first output terminal DOUT outputs are compared
As a result " 1 ".
As shown in figure 4, the signal of the first output terminal DOUT and the second output terminal DOUTB outputs negates signal for one group, this
Though not drawing the second output terminal DOUTB signals exported by port in embodiment, remain to be somebody's turn to do by instrument monitoring
The oscillogram of point.
If as shown in figure 3, the signal of the first output terminal DOUT outputs of the sense amplifier 21 is " 0 ", the signal
" 0 " must be exported as signal " 1 " by the 3rd NAND gate 232, then is exported by the second phase inverter 233 to output terminal Q, export signal
For " 0 "；If the signal of the first output terminal DOUT outputs of the sense amplifier 21 is " 1 ", due to the RS latch cicuits
It is in advance " 1 " by output terminal Q set via presetting bit signal SET, output terminal Q is constant, is still " 1 ".
As shown in figure 4, the enable signal SA_Enable of the sense amplifier 21 is from low transition to high level, this
When the first output terminal DOUT output signal be " 1 ", so the RS latch cicuits 23 output terminal Q export signal it is constant,
Still it is " 1 ".
It can be seen from the above that compared with the sense amplifier 11 of the prior art, sense amplifier 21 of the invention exports
The time of signal " 0 " is identical with the time of prior art output signal " 0 "；And for the output of signal " 1 ", believed by presetting bit
The set function of number SET shifts to an earlier date the time for exporting signal " 1 " significantly, there is larger lifting compared to the prior art, this
The small shortening for exporting signal " 1 " time is of great significance for lifting the access time of whole SRAM.
In conclusion the present invention provides a kind of SRAM output latch circuits, the SRAM output latch circuits include at least：
Sense amplifier, presetting bit signal generating circuit, RS latch cicuits；The sense amplifier is connected to SRAM memory cell, uses
Amplify output more afterwards in the data-signal that will be exported in the SRAM memory cell, easy to subsequent conditioning circuit to the data-signal
Identification；The presetting bit signal generating circuit is connected to the input terminal of the RS latch cicuits, is latched for producing the RS
The presetting bit signal of circuit；The presetting bit signal generating circuit includes the first NAND gate of the first phase inverter and two inputs, institute
The output terminal for stating the first phase inverter is connected to an input terminal of first NAND gate, the input terminal of first phase inverter with
Another input terminal of first NAND gate is connected；The RS latch cicuits are connected to the sense amplifier and described preset
The output terminal of position signal generating circuit, for latching and transmitting the data-signal of the sense amplifier output.The present invention's
SRAM output latch circuits increase a presetting bit signal SET by presetting bit signal generating circuit to RS latch cicuits, work as spirit
Quick amplifier output signal shortens its output time when being " 1 ", to achieve the purpose that lifting whole SRAM access times.So
The present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (9)
1. a kind of SRAM output latch circuits, it is characterised in that the SRAM output latch circuits include at least：
Sense amplifier, presetting bit signal generating circuit, RS latch cicuits；
The sense amplifier is connected to SRAM memory cell, for the data-signal ratio that will be exported in the SRAM memory cell
After amplify, easy to identification of the subsequent conditioning circuit to the data-signal；
The presetting bit signal generating circuit produces presetting bit signal, the RS latch cicuits is exported high level signal in advance；
The RS latch cicuits are connected to the sense amplifier and the presetting bit signal generating circuit, for latching and transmitting
The signal of the sense amplifier output；
When the input signal of the sense amplifier is " 0 ", the output signal of the RS latch is letter by signal " 1 " saltus step
Number " 0 "；When the input signal of the sense amplifier is " 1 ", the output signal of the RS latch remains signal " 1 ".
2. SRAM output latch circuits according to claim 1, it is characterised in that：The presetting bit signal generating circuit bag
The first NAND gate of the first phase inverter and two inputs is included, the output terminal of first phase inverter is connected to first NAND gate
One input terminal, the input terminal of first phase inverter are connected with another input terminal of first NAND gate.
3. SRAM output latch circuits according to claim 1, it is characterised in that：The input terminal of the sense amplifier connects
Connect the bit line that one group of data-signal negates.
4. SRAM output latch circuits according to claim 1, it is characterised in that：The enable signal of the sense amplifier
It is high effectively.
5. SRAM output latch circuits according to claim 1, it is characterised in that：The presetting bit signal generating circuit
Input signal is clock signal.
6. SRAM output latch circuits according to claim 1, it is characterised in that：The presetting bit signal is low level arteries and veins
Punching.
7. SRAM output latch circuits according to claim 1, it is characterised in that：The RS latch cicuits include second with
NOT gate, the 3rd NAND gate and the second phase inverter, the input terminal and output terminal point of second NAND gate and the 3rd NAND gate
Other cross-couplings, second phase inverter are connected to the output terminal of the 3rd NAND gate.
8. SRAM output latch circuits according to claim 7, it is characterised in that：Second NAND gate and the described 3rd
NAND gate is two input nand gates.
9. SRAM output latch circuits according to claim 1, it is characterised in that：The output terminal of the sense amplifier connects
The reset terminal of the RS latch cicuits is connected to, the output terminal of the presetting bit signal generating circuit is connected to the RS latch cicuits
Set end.
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| CN201410216693.8A CN105097016B (en) | 2014-05-21 | 2014-05-21 | A kind of SRAM output latch circuits |
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| CN105097016B true CN105097016B (en) | 2018-04-17 |
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| CN106205686B (en) * | 2016-06-29 | 2017-06-06 | 湖南恒茂高科股份有限公司 | Memory matched line dynamic latching circuit |
| CN108288480B (en) * | 2018-01-05 | 2020-12-04 | 佛山市顺德区中山大学研究院 | Data latching and reading sensitive amplifier based on magnetic tunnel junction |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1469550A (en) * | 2002-06-03 | 2004-01-21 | 松下电器产业株式会社 | Semiconductor integrated circuit |
| CN102013271A (en) * | 2009-09-08 | 2011-04-13 | 中国科学院上海微系统与信息技术研究所 | Fast reading device and method of phase change memory |
| CN102290096A (en) * | 2010-06-18 | 2011-12-21 | 黄效华 | decoding and logic control circuit of static random access memory |
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2014
- 2014-05-21 CN CN201410216693.8A patent/CN105097016B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1469550A (en) * | 2002-06-03 | 2004-01-21 | 松下电器产业株式会社 | Semiconductor integrated circuit |
| CN102013271A (en) * | 2009-09-08 | 2011-04-13 | 中国科学院上海微系统与信息技术研究所 | Fast reading device and method of phase change memory |
| CN102290096A (en) * | 2010-06-18 | 2011-12-21 | 黄效华 | decoding and logic control circuit of static random access memory |
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