CN101656097B - Sensitive amplifier circuit applied to semiconductor memory and work method thereof - Google Patents
Sensitive amplifier circuit applied to semiconductor memory and work method thereof Download PDFInfo
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- CN101656097B CN101656097B CN200910034400A CN200910034400A CN101656097B CN 101656097 B CN101656097 B CN 101656097B CN 200910034400 A CN200910034400 A CN 200910034400A CN 200910034400 A CN200910034400 A CN 200910034400A CN 101656097 B CN101656097 B CN 101656097B
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Abstract
The invention discloses a sensitive amplifier circuit applied to a semiconductor memory, with high speed, low voltage and low power consumption. The sensitive amplifier circuit comprises a high sensitive latch amplifying circuit, a precharge circuit and a rapid selective write-back circuit. A memory cell bit line is precharged to a proper electric potential by the precharge circuit, different states of the information in a memory can result in rapid response of bit line electric potential when reading data, and stored information is amplified to carry out subsequent treatment by the amplification of a high sensitivity sensitive amplifier. The circuit can also write information into the memory cell by selective write operation. The sensitive amplifier circuit of the invention can be applied to various memory chips, and has simple circuit structure, low voltage, low power consumption, high sensitivity and high work reliability.
Description
Technical field
The present invention relates to a kind of sensitive amplifier circuit and working method thereof that is applied to the high sensitivity low-voltage and low-power dissipation that has selectivity write-back control mode of semiconductor memory.
Background technology
Semiconductor memory is widely used among the various electronic products.Along with the development of technology, the size of storer is more and more littler, and density is also increasingly high, and the speed of storage access data is also more and more faster.Sense amplifier is an important component part of semiconductor memory chips, and it directly has influence on reading of semiconductor memory and writing speed.Sense amplifier is judged through level ratio through to the intelligence sample on the storage unit bit line, after amplification, is obtained high and low level (logic state " 1 " or " 0 ") signal.Along with the raising of memory density and the increase of capacity; The quantity of the storage unit that is connected on every bit line in the storage array is also increasing; Stray capacitance on the single bit line is also increasing, has so just reduced the reading speed of sense amplifier and has increased delay of signals.Therefore, also increasingly high to the requirement of sense amplifier.Low-voltage Low-power, at a high speed, the design of the sense amplifier of high stability is very important.
Be applied to traditional sense amplifier of semiconductor memory, generally adopt digital differential comparer or latch structure, like Fig. 1 a, shown in the 1b.Foregoing circuit is applied to being used for the data-signal of amplifying and storage unit array in dynamic RAM (DRAM) and SRAM (SRAM) circuit, and passes to output state to data.But sensitive amplifier structure traditional shown in Fig. 1 a is more than the sense amplifier complicacy that Fig. 1 b latchs structure, can not be written back to data input pin to data simultaneously; Though and the traditional latch cicuit shown in Fig. 1 b is simple, if the storage unit number is more on the bit line, can cause every bit lines stray capacitance excessive, thereby make data access speed slack-off.Therefore in the array that the unit is a lot of on single bit line, this circuit structure needs further to improve.
In addition, the write back operations of the sense amplifier shown in Fig. 1 b is positive feedback, and not being suitable for needs degenerative storer.In order to address the above problem, the present invention proposes a kind of novel sense amplifier, to adapt to the different needs of different memory.
Summary of the invention
The technical matters that the present invention will solve is: under the situation that stray capacitance is bigger on the bit line under low supply voltage; Design a kind of sense amplifier through circuit design and sequential control with quick amplifying power; Corresponding to different semiconductor memories, realize a kind of control circuit of write-back flexibly simultaneously.
The object of the invention is realized through following technical scheme:
A kind of sensitive amplifier circuit that is applied to semiconductor memory; Comprise pre-charge circuit, high sensitivity latchs amplifying circuit, and fast selective write-back circuit independently; Said pre-charge circuit; High sensitivity latchs amplifying circuit, and fast selective write-back circuit all is connected on the bit line BL of storage array circuit of semiconductor memory
Said pre-charge circuit comprises precharge the one a NMOS pipe M1, and its grid meets precharge control signal PRE; Its drain electrode or source electrode meet preliminary filling datum V1, and correspondingly, source electrode or drain electrode meet storage array bit line BL;
Said fast selective write-back circuit is made up of the 2nd NMOS pipe M4 and PMOS pipe M3; The grid of said the 2nd NMOS pipe M4 and PMOS pipe M3 joins, draining to link to each other constitutes an inverter structure; The high sensitivity of receiving said grid latchs the first data terminal D end of amplifying circuit; Output terminal is received the bit line BL of said storage array, and said the 2nd NMOS pipe M4 and PMOS pipe M3 source terminal take back write control signal WRB0 end and WRB1 end respectively;
It is that structure is latched in positive feedback that said high sensitivity latchs amplifying circuit; Also comprise the potential balance circuit simultaneously; Amplification control circuit and reference voltage transmit control circuit, and two continuous second, third PMOS pipe M7, the 3rd, the 4th NMOS pipe M11, M12 that M8 links to each other with two; The grid of said second, third PMOS pipe M7, M8 is connected respectively to its drain electrode or source electrode, and correspondingly, the source electrode of this second, third PMOS pipe M7, M8 or drain electrode are connected to high sensitivity and latch first of amplifying circuit and relatively hold C0; The grid of said the 3rd, the 4th NMOS pipe M11, M12 is connected respectively to its drain electrode or source electrode, and correspondingly, the 3rd, the 4th NMOS pipe M11, M12 source electrode or drain electrode are connected to high sensitivity and latch second of amplifying circuit and relatively hold C1; The high sensitivity that is connected to the drain electrode of the 2nd PMOS pipe M7 and the 3rd NMOS pipe M11 or source electrode latchs the first data terminal D end of amplifying circuit; The high sensitivity that is connected to the drain electrode of the 3rd PMOS pipe M8 and the 4th NMOS pipe M12 or source electrode latchs the second data terminal D* end of amplifying circuit;
After the balanced voltage of the balance control signal end LOADON that bit-line voltage on the said bit line BL and high sensitivity latch amplifying circuit compares; Its signal latchs amplifying circuit through said high sensitivity and amplifies and latch, and carries out the selectivity write back operations of location contents then through said this signal of fast selective write-back circuit control.
Preferably, said sensitive amplifier circuit also comprises data the 5th nmos switch M2 that samples, and its grid meets sampling control signal FI; Its drain electrode or source electrode meet the bit line BL of storage array, and correspondingly, source electrode or drain electrode connect the first data terminal D end that high sensitivity latchs amplifying circuit.
Preferably; Said potential balance circuit is composed in series by the 4th PMOS pipe M9 and the 5th PMOS pipe M10; Be connected in series and a little receive high sensitivity and latch amplifying circuit judgment standard voltage VEQ; Four, an other end of the 5th PMOS pipe is received first, second data terminal D, the D* end that high sensitivity latchs amplifying circuit respectively, simultaneously said the 4th, the 5th PMOS pipe M9, and the grid of M10 links together and meets balance control signal end LOADON.
Preferably, the pipe of the PMOS in the said potential balance circuit can be managed with NMOS and replaced.
Preferably, said reference voltage transmission control circuit is made up of the 6th NMOS pipe M14 and the 6th PMOS pipe M5; The grid of said the 6th NMOS pipe M14 and the 6th PMOS pipe M5 is connected to reference voltage write signal WR end and NWR end respectively; Said the 6th PMOS pipe M5 source electrode or drain electrode meet the judgment standard current potential VEQ that high sensitivity latchs amplifying circuit, and be corresponding, and drain electrode or source electrode are connected to high sensitivity and latch first of amplifying circuit and relatively hold C0; Source electrode or the drain electrode of said the 6th NMOS pipe M14 meet the judgment standard current potential VEQ that high sensitivity latchs amplifying circuit, and be corresponding, and drain electrode or source electrode are connected to high sensitivity and latch second of amplifying circuit and relatively hold C1.
Preferably, said amplification control circuit is made up of the 7th PMOS pipe M6 and the 7th NMOS pipe M13; The grid of the grid of said the 7th PMOS pipe M6 and said the 7th NMOS pipe M13 is connected to reference voltage write signal WR end and NWR end respectively; Source electrode or the drain electrode of said the 7th PMOS pipe M6 connect the VSA signal end, and be corresponding, and drain electrode or source electrode are connected to high sensitivity and latch first of amplifying circuit and relatively hold C0; Source electrode or the grounded drain 6ND of said the 7th NMOS pipe M13, corresponding, drain electrode or source electrode are connected to high sensitivity and latch second of amplifying circuit and relatively hold C1.
Preferably; Said sensitive amplifier circuit is shared by two or more memory cell arrays, and the bit line of two or more storage arrays is connected to first, second data terminal D, the D* end that said high sensitivity latchs amplifying circuit through data sampling the 5th nmos switch M2 respectively.
A kind of working method that is applied to the sensitive amplifier circuit of semiconductor memory; Entire circuit work is divided into 5 stages to be carried out, and is respectively the level preliminary filling stage, the storage array induction of signal stage; The sense amplifier sample phase latchs amplification stage and write back operations stage; Wherein be specially:
The level preliminary filling stage: the preliminary filling control signal is effective, and sampling control signal, write back operations control signal are invalid, and sense amplifier is in equilibrium state, and the sensitive amplifier circuit built-in potential equates everywhere and is judgment standard current potential VEQ;
The storage array induction of signal stage: preliminary filling, sampling, write back operations control signal are all invalid, and sense amplifier still is in equilibrium state;
The sense amplifier sample phase: sampling control signal is effective, and preliminary filling, write back operations control signal are invalid, and sense amplifier internal work level is set up, but it still is in equilibrium state;
Sense amplifier latchs amplification stage: preliminary filling, sampling, write back operations control signal are all invalid, and sense amplifier is inner to be amplified control signal and operation level to transmit signal effective, and sampled signal is effectively amplified;
The write back operations stage: preliminary filling, sampling control signal are invalid, and the write-back control signal is effective, through said fast selective write-back circuit write-back information needed on the storage unit bit line.
Beneficial effect of the present invention is mainly reflected in: 1 through simple, effectively sequential cooperation, can under voltage under the low supply voltage, carry out rapid and reliable to memory content and read, and configurable flexibly write back operations is all effective to all types of storeies simultaneously; 2 can be applicable in the various semiconductor memory chips, and circuit structure is simple, low-voltage, low-power consumption, high sensitivity and functional reliability are high.
Description of drawings
Fig. 1 a: prior art differential comparator circuit figure.
Fig. 1 b: prior art latchs sensitive amplifier circuit figure.
Fig. 2: the circuit diagram of the sense amplifier that the present invention proposes.
Fig. 3: the sense amplifier control signal sequential synoptic diagram that the present invention proposes.
Fig. 4: the sense amplifier data amplification that the present invention proposes and the simulation result of write back operations.
Fig. 5: the sense amplifier functions expanding synoptic diagram that the present invention proposes.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation.As shown in Figure 2, the sense amplifier among the present invention comprises three parts: pre-charge circuit 101, high sensitivity induction amplifying circuit 103 and fast selective write-back circuit 102 independently.
As shown in Figure 2, pre-charge circuit 101 is made up of a metal-oxide-semiconductor M1.Precharge level is set according to the sense amplifier datum.When the preliminary filling signal is effective, be charged to a certain current potential V1 to the bit line current potential rapidly.The preliminary filling operating process was not counted in the access time, therefore can not cause bigger influence to the access time of whole memory unit, so just can make circuit under the bigger situation of bit line capacitance, still read fast.
Based on the signal amplifier structure of latch, added balancing circuitry and amplifier working control signal, make amplifier can be rapidly to the amplification of signal.Through simple sequential control, realize write-back control operation flexibly.The write-back mode can be configured through control signal, makes this sense amplifier use more flexibly with extensive.
High sensitivity induction amplifying circuit 103, traditional locks is deposited big circuit by metal-oxide-semiconductor M7 in this circuit, M8, M11, M12 forms, amplification data when latching bit line data.This moment balancing circuitry PMOS pipe M9, the control signal no longer valid of M10, and the coherent signal that control signal is amplified is effective makes and latchs amplifier and begin to latch amplification.And be amplified to VSA or GND to the logical signal of original storer correlative position line, promptly be enlarged into strong logic level " 1 " " 0 ".
Write-back circuit 102, this write-back circuit is made up of the structure of a similar CMOS phase inverter type of attachment.Write-back mode can be written back to " 1 " in the latch or " 0 " in the storer according to the difference that triggers the write-back signal very easily.
Further, said precharge NMOS pipe M1, its grid meets precharge control signal PRE; Its drain electrode or source electrode meet preliminary filling datum V1, and correspondingly, source electrode or drain electrode meet storage array bit line BL.Said fast selective write-back circuit is made up of a NMOS pipe M4 and a PMOS pipe M3; The grid of said NMOS pipe M4 and PMOS pipe M3 joins, draining to link to each other constitutes an inverter structure; Said grid is received the data I/O end D end of sense amplifier; Output terminal is received the bit line BL of said storage array, and said NMOS pipe M4 and PMOS pipe M3 source terminal take back write control signal WRB0 end and WRB1 end respectively.Said sensitive amplifier circuit also comprises a data sampling nmos switch M2, and its grid meets sampling control signal FI; Its drain electrode or source electrode meet the bit line BL of storage array, and correspondingly, source electrode or drain electrode connect the data I/O end D end of sense amplifier.
Further; Said high sensitivity latchs amplifying circuit and adopts the positive feed-back latch structure; Also comprise the potential balance circuit simultaneously, amplification control circuit and reference voltage transmit control circuit, and two continuous PMOS pipe M7, NMOS pipe M11, M12 that M8 links to each other with two; The grid of said two PMOS pipe M7, M8 is connected respectively to its drain electrode or source electrode, correspondingly, and these two PMOS pipes M7, the source electrode of M8 or relatively end C0 that drain electrode is connected to sense amplifier; The grid of said two NMOS pipe M11, M12 is connected respectively to its drain electrode or source electrode, correspondingly, these two NMOS pipe M11, M12 source electrode or drain electrodes be connected to sense amplifier another relatively hold C1; The drain electrode of one of them PMOS pipe M7 and one of them NMOS pipe M11 or one of them data terminal D end that source electrode is connected to sense amplifier; Another PMOS pipe M8 and the drain electrode of another NMOS pipe M12 or one of them data terminal D* end that source electrode is connected to sense amplifier.
Said potential balance circuit is by two PMOS pipe M9; M10 is composed in series; Be connected in series and a little receive sense amplifier judgment standard voltage VEQ; Two outer ends of two PMOS pipes are received two data terminal D, the D* end of sense amplifier respectively, simultaneously said two PMOS pipe M9, and the grid of M10 links together and meets balance control signal end LOADON.Further, the pipe of the PMOS in the said potential balance circuit can be managed with NMOS and replaced.
Said reference voltage transmits control circuit and is made up of a NMOS pipe M14 and a PMOS pipe M5; The grid of a said NMOS pipe M14 and a PMOS pipe M5 is connected to reference voltage write signal WR end and NWR end respectively; Said PMOSM5 pipe source electrode or drain electrode meet sense amplifier judgement reference potential VEQ, and corresponding, drain electrode or source electrode are connected to the relatively end C0 of sense amplifier; The source electrode of said NMOS pipe M14 or drain electrode meet sense amplifier judgement reference potential VEQ, and be corresponding, drain electrode or source electrode be connected to sense amplifier another relatively hold C1.
Said amplification control circuit is made up of a PMOS pipe M6 and a NMOSM13; The grid of the grid of said PMOS pipe M6 and said NMOS pipe M13 is connected to reference voltage write signal WR end and NWR end respectively; Source electrode or the drain electrode of said PMOS pipe M6 connect the VSA signal end, and corresponding, drain electrode or source electrode are connected to the relatively end C0 of sense amplifier; Source electrode or the grounded drain GND of said NMOS pipe M13, corresponding, drain electrode or source electrode be connected to sense amplifier another relatively hold C1.
Wherein, preliminary filling amplifier 101 is through the effect of preliminary filling control signal, bit line BL preliminary filling to set potential.If memory cell circuits 100 contents change, can make rapidly that the bit line current potential changes, amplify thereby utilize sense amplifier to carry out data.As shown in Figure 3, PRE is effective when the preliminary filling control signal, reaches necessary potential behind the bit line BL current potential elapsed time t1.Generally speaking, this level latchs amplifier 103 greater than subsequent improved decision level VEQ is set.
Behind the preliminary filling EO, the content of memory cell circuits 100 is extracted.When memory content was " 1 ", precharge level began discharge through the stray capacitance of bit line BL, and the result makes bit line BL current potential descend.Behind the elapsed time t2, bit line BL current potential road is to a certain level V1, and this level is less than the improved amplifier 103 decision level VEQ that latch.On the contrary, if be " 0 " in the storer, this BL level does not have obvious variation so, still is higher than VEQ in precharge level behind the elapsed time t2.As shown in Figure 3, elapsed time t2 just can demonstrate to improve on BL and latch the input signal that amplifier 102 can correctly be adjudicated when the CELL signal extraction of memory cell 100 was effective.
Behind the DSR on the bit line BL, the control signal FI of data sampling switch is effective, latchs the signal sampling on the storage array bit line BL to improvement the data induction end of amplifier 103.Like Fig. 3 and shown in Figure 4, FI carry out data sampling before, latch amplifier and carry out balancing run, promptly LOADON and NWR are low levels, wherein NWR and WR opposite signal each other.This moment, M5 and M14 transmitted VEQ latch amplifier amplification control end, and signal LOADON moves its data terminal D and D* to fixed level VEQ.Therefore during balance, M7, M8, M11, each terminal potential of M12 equates, all equals judgment standard current potential VEQ.In case FI is effective, when carrying out the operation of BL data sampling, latchs amplifier D end and can sense the upward corresponding current potential size of BL; Compare with judgment standard current potential VEQ then; Amplify control signal NWR and become low level this moment, and the WR bar becomes high level, and the balance control signal saltus step is a high level simultaneously.When FI is effective, latch the effective operation level of amplifier and should set up, promptly VSA becomes the amplifier operation level.Therefore, when the effective working control signal of amplifier is effective, wherein WR is a high level, and sense amplifier can be rapidly obtains the induction of D end to such an extent that data are amplified and latched.
When sensitivity latchs amplifier after the amplification of the information of storage unit and latching, can carry out effective write-back to these data through the triggering that writes back signal, its sequential signal is as shown in Figure 3.This write-back circuit can be respectively to " 0 ", and write-back is carried out in " 1 ".Simultaneously can also realize to " 0 " the complementary write-back of " 1 " signal.When D end data position " 1 ", NMOS pipe M4 is opened in the write-back circuit, if this moment, WRB1 just can return one writing to BL for " 1 ", otherwise one 0 of write-back; In like manner, when the D end data is " 0 ", the PMOS pipe is opened, and can accomplish similar write back operations.
The sense amplifier functions expanding synoptic diagram that Fig. 5 proposes for the present invention.In storage chip,, can there be sense amplifier a plurality of storage arrays to share in order to reduce area.The sense amplifier that the present invention proposes can be shared with 201* by two storage arrays 201.Two data of the sense amplifier 200 that the present invention proposes relatively hold D and D* to receive respectively on two complementary bit lines BL and the BL*, and write-back circuit 202 writes back the bit line of storage array separately to information through the sense amplifier amplifying signal to two ends respectively with 202* under the effect of write-back control signal.
Although foregoing description is very detailed, this only is the explanation of the principle of the invention, and the present invention is not limited to this embodiment that this paper discloses and explains obviously.Therefore, do not exceed and to make suitable variation in design of the present invention and the scope and all will be included in the further embodiment of the present invention.
Claims (8)
1. sensitive amplifier circuit that is applied to semiconductor memory; Comprise pre-charge circuit (101), high sensitivity latchs amplifying circuit (103), and fast selective write-back circuit (102) independently; It is characterized in that: said pre-charge circuit (101); High sensitivity latchs amplifying circuit (103), and fast selective write-back circuit (102) all is connected on the bit line (BL) of storage array circuit of semiconductor memory
Said pre-charge circuit (101) comprises precharge the one a NMOS pipe (M1), and its grid connects precharge control signal (PRE); Its drain electrode or source electrode connect preliminary filling datum (V1), and correspondingly, source electrode or drain electrode connect storage array bit line (BL);
Said fast selective write-back circuit (102) is made up of the 2nd NMOS pipe (M4) and PMOS pipe (M3); Said the 2nd NMOS pipe (M4) joins with the grid of PMOS pipe (M3), draining to link to each other constitutes an inverter structure; The high sensitivity of receiving said grid latchs first data terminal (D end) of amplifying circuit (103); Output terminal is received the bit line (BL) of said storage array, said the 2nd NMOS pipe (M4) and PMOS pipe
(M3) source terminal takes back write control signal WRB0 end and WRB1 end respectively;
It is that structure is latched in positive feedback that said high sensitivity latchs amplifying circuit; Also comprise the potential balance circuit simultaneously; Amplification control circuit and reference voltage transmit control circuit, and two the 3rd, the 4th NMOS pipes (M11, M12) that second, third continuous PMOS pipe (M7, M8) links to each other with two; The grid of said second, third PMOS pipe (M7, M8) is connected respectively to its drain electrode or source electrode, and correspondingly, the source electrode of this second, third PMOS pipe (M7, M8) or drain electrode are connected to first end (C0) relatively that high sensitivity latchs amplifying circuit (103); The grid of said the 3rd, the 4th NMOS pipe (M11, M12) is connected respectively to its drain electrode or source electrode, and correspondingly, the 3rd, the 4th NMOS pipe (M11, M12) source electrode or drain electrode are connected to second end (C1) relatively that high sensitivity latchs amplifying circuit (103); The drain electrode or the source electrode of the 2nd PMOS pipe (M7) and the 3rd NMOS pipe (M11) are connected to first data terminal (D end) that high sensitivity latchs amplifying circuit (103); The drain electrode or the source electrode of the 3rd PMOS pipe (M8) and the 4th NMOS pipe (M12) are connected to second data terminal (D* end) that high sensitivity latchs amplifying circuit (103);
After the balanced voltage that bit-line voltage on the said bit line (BL) and high sensitivity latch the balance control signal end (LOADON) of amplifying circuit (103) compares; Its signal latchs amplifying circuit (103) through said high sensitivity and amplifies and latch, and controls the selectivity write back operations that this signal carries out location contents through said fast selective write-back circuit (102) then.
2. the sensitive amplifier circuit that is applied to semiconductor memory as claimed in claim 1 is characterized in that: said sensitive amplifier circuit also comprises data the 5th nmos switch (M2) of sampling, and its grid connects sampling control signal (FI); Its drain electrode or source electrode connect the bit line (BL) of storage array, and correspondingly, source electrode or drain electrode connect first data terminal (D end) that high sensitivity latchs amplifying circuit (103).
3. the sensitive amplifier circuit that is applied to semiconductor memory as claimed in claim 1; It is characterized in that: said potential balance circuit manages (M9) by the 4th PMOS and the 5th PMOS pipe (M10) is composed in series; Be connected in series and a little receive high sensitivity and latch amplifying circuit (103) judgment standard voltage (VEQ); Four, an other end of the 5th PMOS pipe is received first, second data terminal (D, D* end) that high sensitivity latchs amplifying circuit (103) respectively; (M9, grid M10) link together and connect balance control signal end (LOADON) simultaneously said the 4th, the 5th PMOS pipe.
4. the sensitive amplifier circuit that is applied to semiconductor memory as claimed in claim 3 is characterized in that: the PMOS pipe in the said potential balance circuit can be managed with NMOS and replaced.
5. the sensitive amplifier circuit that is applied to semiconductor memory as claimed in claim 1 is characterized in that: said reference voltage transmission control circuit manages (M14) by the 6th NMOS and the 6th PMOS pipe (M5) is formed;
The grid of said the 6th NMOS pipe (M14) and the 6th PMOS pipe (M5) is connected to reference voltage write signal WR end and NWR end respectively;
Said the 6th PMOS pipe (M5) source electrode or drain electrode connect the judgment standard current potential (VEQ) that high sensitivity latchs amplifying circuit (103), and be corresponding, and drain electrode or source electrode are connected to first end (C0) relatively that high sensitivity latchs amplifying circuit (103);
The source electrode or the drain electrode of said the 6th NMOS pipe (M14) connect the judgment standard current potential (VEQ) that high sensitivity latchs amplifying circuit (103), and be corresponding, and drain electrode or source electrode are connected to second end (C1) relatively that high sensitivity latchs amplifying circuit (103).
6. the sensitive amplifier circuit that is applied to semiconductor memory as claimed in claim 1 is characterized in that: said amplification control circuit manages (M6) by the 7th PMOS and the 7th NMOS pipe (M13) is formed;
The grid of the grid of said the 7th PMOS pipe (M6) and said the 7th NMOS pipe (M13) is connected to reference voltage write signal WR end and NWR end respectively;
The source electrode or the drain electrode of said the 7th PMOS pipe (M6) connect the VSA signal end, and be corresponding, and drain electrode or source electrode are connected to first end (C0) relatively that high sensitivity latchs amplifying circuit (103);
The source electrode or the grounded drain (GND) of said the 7th NMOS pipe (M13), corresponding, drain electrode or source electrode are connected to second end (C1) relatively that high sensitivity latchs amplifying circuit (103).
7. the sensitive amplifier circuit that is applied to semiconductor memory as claimed in claim 1; It is characterized in that: said sensitive amplifier circuit is shared by two or more memory cell arrays, and the bit line of two or more storage arrays is connected to first, second data terminal (D, D* end) that said high sensitivity latchs amplifying circuit (103) through data sampling the 5th nmos switch (M2) respectively.
8. working method that is applied to the sensitive amplifier circuit of semiconductor memory as claimed in claim 1; It is characterized in that: entire circuit work is divided into 5 stages and carries out; Be respectively the level preliminary filling stage; In the storage array induction of signal stage, the sense amplifier sample phase latchs amplification stage and write back operations stage; Wherein be specially,
The level preliminary filling stage: the preliminary filling control signal is effective, and sampling control signal, write back operations control signal are invalid, and sense amplifier is in equilibrium state, and the sensitive amplifier circuit built-in potential equates everywhere and is judgment standard current potential (VEQ);
The storage array induction of signal stage: preliminary filling, sampling, write back operations control signal are all invalid, and sense amplifier still is in equilibrium state;
The sense amplifier sample phase: sampling control signal is effective, and preliminary filling, write back operations control signal are invalid, and sense amplifier internal work level is set up, but it still is in equilibrium state;
Sense amplifier latchs amplification stage: preliminary filling, sampling, write back operations control signal are all invalid, and sense amplifier is inner to be amplified control signal and operation level to transmit signal effective, and sampled signal is effectively amplified;
The write back operations stage: preliminary filling, sampling control signal are invalid, and the write-back control signal is effective, through said fast selective write-back circuit write-back information needed on the storage unit bit line.
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| CN102385899B (en) * | 2010-08-27 | 2014-05-21 | 中芯国际集成电路制造(上海)有限公司 | Latching amplification circuit applied to memory and reading method |
| CN102169717B (en) * | 2011-05-06 | 2013-03-13 | 西安华芯半导体有限公司 | Memory device with data processing function |
| CN104464806A (en) * | 2014-08-27 | 2015-03-25 | 北京中电华大电子设计有限责任公司 | Sense amplifier applicable to EEPROM and FLASH |
| CN106205713B (en) * | 2016-06-29 | 2019-11-26 | 上海电机学院 | A kind of high-speed induction amplifier |
| CN108282153B (en) * | 2017-12-15 | 2021-09-24 | 普冉半导体(上海)股份有限公司 | Sensitive amplifier circuit with low-voltage bilateral amplification |
| WO2022016476A1 (en) * | 2020-07-23 | 2022-01-27 | 华为技术有限公司 | Bit line read circuit and memory |
| CN113436661B (en) * | 2021-07-06 | 2023-10-27 | 无锡中微亿芯有限公司 | Data read-write control circuit for flash type programmable logic device |
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| CN101373627A (en) * | 2007-08-20 | 2009-02-25 | 天津南大强芯半导体芯片设计有限公司 | Sensitive amplifier circuit of semiconductor memory and operating method and application thereof |
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| CN101656097A (en) | 2010-02-24 |
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