CN113436661B - Data read-write control circuit for flash type programmable logic device - Google Patents
Data read-write control circuit for flash type programmable logic device Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
Abstract
The application discloses a data read-write control circuit for a flash type programmable logic device, which relates to the field of programmable logic devices, wherein a data selection module gates a configuration data channel to write configuration data into a data latch module for latching when the data is written, then outputs corresponding configuration data through a data driving module, and transmits the configuration data at the output end of the data driving module to a data trimming module for trimming to obtain trimming configuration data when the data read-write control circuit carries out data write-back, and the data selection module gates the trimming configuration data to write the trimming configuration data into the data latch module for latching and then outputs the trimming configuration data through the data driving module.
Description
Technical Field
The application relates to the field of programmable logic devices, in particular to a data read-write control circuit for a flash type programmable logic device.
Background
The programmable logic device is designed based on a repeatedly configured storage technology, and can complete the modification of the circuit by re-downloading programming, and has the advantages of short development period, low cost, small risk, convenience in maintenance and upgrading of an electronic system and the like, so that the programmable logic device becomes the mainstream of an integrated circuit chip.
The configuration memory architecture of the existing programmable logic device is shown in fig. 1, and mainly comprises a read-write control circuit, a data shift register DSR, an address decoder ASR and a memory array formed by memory cells FlashCell, and the configuration memory architecture is widely distributed and extends over the whole chip, and the specific cascade stage number and the chip capacity are related. In the zero clearing stage, all memory cell FlashCell outputs are 0, in the configuration data stage, the read-write control circuit configures bit stream to load to the data shift register DSR, through address decoder ASR reconfigurated to memory cell FlashCell, the existing read-write control circuit mainly realizes the function of basic configuration of memory function, the function is comparatively single, and many complex integrated circuit chips in the prior art need to load configuration information after the chip resets, or reload appointed configuration information in the working state, the read-write control circuit in the existing configuration memory is difficult to meet the function requirement.
Disclosure of Invention
The present inventors have proposed a data read-write control circuit for a flash programmable logic device, which is directed against the above problems and technical needs, and the technical scheme of the present application is as follows:
the data read-write control circuit comprises a data selection module, a data latch module, a data driving module, a read-back control module and a data trimming module, wherein the data selection module comprises a configuration data channel and a write-back data channel, the input end of the configuration data channel is used as the data end of the data read-write control circuit to acquire configuration data, the output end of the configuration data channel is connected with the output end of the write-back data channel and is connected with the input end of the data latch module, the output end of the data latch module is connected with the input end of the data driving module, the output end of the data driving module is used as the output end of the data read-write control circuit to be connected with a flash memory unit, the output end of the data driving module is also connected with the input end of the data trimming module through the read-back control module, and the output end of the data trimming module is connected with the input end of the write-back data channel;
when the data read-write control circuit writes data, the data selection module gates the configuration data channel to write the configuration data into the data latch module for latching, and then the data drive module outputs the corresponding configuration data and writes the configuration data into the flash memory unit;
when the data read-write control circuit performs data write-back, the read-back control module transmits the configuration data of the output end of the data driving module to the data trimming module to trim the data to obtain trimmed configuration data, the data selection module gates the write-back data channel to write the trimmed configuration data into the data latch module for latching, and then the configuration data is output through the data driving module and written into the flash memory unit.
The beneficial technical effects of the application are as follows:
the application discloses a data read-write control circuit for a flash type programmable logic device, which can realize stable data configuration, data write-back and data verification, can realize the basic configuration of a conventional storage function, can realize the functions of writing configuration data and verifying configuration data according to the application requirements of users, does not occupy additional register units, is flexible to realize, and is suitable for large-scale programmable devices.
Drawings
Fig. 1 is a diagram of a configuration memory architecture of a conventional programmable logic device.
FIG. 2 is a circuit diagram of one embodiment of the disclosed data read/write control circuit.
FIG. 3 is a circuit diagram of a data verification module included in another embodiment of the data read/write control circuit disclosed in the present application.
Fig. 4 is a schematic diagram of a partial signal waveform when the data read/write control circuit disclosed in the present application performs data writing.
Fig. 5 is a schematic diagram of partial signal waveforms when the data read-write control circuit disclosed by the application performs data read-back and read-back verification.
Detailed Description
The following describes the embodiments of the present application further with reference to the drawings.
The application discloses a data read-write control circuit for a flash type programmable logic device, referring to fig. 2, the data read-write control circuit comprises a data selection module, a data latch module, a data driving module, a read-back control module and a data trimming module. The data selection module comprises a configuration data channel and a write-back data channel, wherein the input end of the configuration data channel is used as a data end D of the data read-write control circuit to acquire configuration data. The output end of the configuration data channel is connected with the output end of the write-back data channel and is connected with the input end of the data latch module, and the data sel_d acquired by the input end of the data latch module is the selected data. The output end of the data latch module is connected with the input end of the data driving module, and the output end BL of the data driving module serving as the output end of the data read-write control circuit is connected with a flash memory cell (flashcell). The output end of the data driving module is also connected with the input end of the data trimming module through the readback control module, and the output end of the data trimming module is connected with the input end of the readback data channel to provide trimming configuration data read_data. In one embodiment, as shown in fig. 2, the read-back control module is a ninth NMOS transistor N9, N9 controlled by the read-back enable signal read_ctrl1, and the source electrode is connected to the output terminal of the data driving module, and the drain electrode is connected to the input terminal of the data trimming module.
When the data read-write control circuit writes data, the data selection module gates the configuration data channel to write the configuration data input by the D end into the data latch module for latching, and then the data drive module outputs the configuration data at the BL end and writes the configuration data into the flash memory unit.
When the data read-write control circuit performs data write-back, the read-back control module transmits configuration data of the output end of the data driving module to the data trimming module to trim the data to obtain trimmed configuration data read_data, the data selection module gates the write-back data channel to write the trimmed configuration data read_data into the data latch module to latch, and the data driving module outputs the trimmed configuration data read_data at the BL end and writes the trimmed configuration data read_data into the flash memory unit. The data trimming module can adopt the existing data trimming circuit to realize the function of trimming data, and the circuit structure of the data trimming module is not limited by the application.
Therefore, based on the structure disclosed by the application, the data read-write control circuit not only can realize a stable data configuration function, but also can realize a data write-back function, thereby meeting the use requirement. It should be noted that, in the process of reaching the BL end, the configuration data input by the D end is subjected to processing such as level conversion, so strictly speaking, the configuration data output by the BL end and the configuration data input by the D end are not identical, but the present application focuses on selectively outputting the two different content data, namely the original configuration data and the modified configuration data, so that they are collectively called configuration data.
In one embodiment, as shown in fig. 2, the configuration data channel in the data selection module includes a zeroth NMOS transistor N0, a first NMOS transistor N1, and a second NMOS transistor N2. The drain electrode of the zeroth NMOS tube N0 is used as a data end D of the data read-write control circuit, the source electrode of the zeroth NMOS tube N0 is connected with the drain electrode of the first NMOS tube N1, the source electrode of the first NMOS tube N1 is connected with the drain electrode of the second NMOS tube N2, and the source electrode of the second NMOS tube N2 is used as an output end of the configuration data channel. The gate of the zeroth NMOS transistor N0 is controlled by a second control signal row2, the gate of the first NMOS transistor N1 is controlled by a first control signal row1, and the gate of the second NMOS transistor N2 is controlled by a shift enable signal shift_en. When the first control signal row1, the second control signal row2 and the shift enable signal shift_en are all high level, the data selection module gates the configuration data channel.
The write-back data channel in the data selection module comprises a third NMOS tube N3 and a fourth NMOS tube N4. The drain electrode of the third NMOS tube N3 is used as the input end of the write-back data channel, the source electrode is connected with the drain electrode of the fourth NMOS tube N4, and the source electrode of the fourth NMOS tube N4 is used as the output end of the write-back data channel. The gate of the third NMOS transistor N3 is controlled by a write-back control signal read_ctrl0, and the gate of the fourth NMOS transistor N4 is controlled by a write-back shift enable signal read_shift_en. When the write back control signal read_ctrl0 and the write back shift enable signal read_shift_en are both high, the data selection module gates the write back data channel.
The data selecting module further comprises a fourteenth NMOS tube N14 connected with the output ends of the configuration data channel and the write-back data channel through a drain electrode, and the source electrode of the fourteenth NMOS tube N14 is grounded and the grid electrode is controlled by an initial value enabling signal shiftn_en. The N14 is mainly used for providing an initial value for the data latch module, and when data writing and data writing back are performed, the initial value enable signal shiftn_en is low to disconnect the N14.
In another embodiment, as shown in fig. 2, in the data driving module, a source of the fifth PMOS transistor P5 is connected to the working power supply VDD, a drain of the fifth PMOS transistor P6 is connected to a source of the sixth PMOS transistor P6, a drain of the sixth PMOS transistor P6 is connected to a drain of the eighth NMOS transistor N8, a source of the eighth NMOS transistor N8 is connected to a drain of the seventh NMOS transistor N7, and a source of the seventh NMOS transistor N7 is grounded. The grid electrode of the fifth PMOS tube P5 is connected with the grid electrode of the eighth NMOS tube N8 and is used as the input end of the data driving module to be connected with the data latching module. The grid electrode of the seventh NMOS tube N7 is controlled by a first drive enabling signal program_en, the grid electrode of the sixth PMOS tube P6 is controlled by a second drive enabling signal program_en, and the common end of the sixth PMOS tube P6 and the eighth NMOS tube N8 is used as the output end of the data driving module to be connected with the BL end. When the first driving enable signal program_en is at a high level and the second driving enable signal program_en is at a low level, the data driving module outputs the data latched by the data latching module.
In another embodiment, the data read-write control circuit can also realize a read-back verification function during write-back, and then the data read-write control circuit further comprises a data verification module, wherein the data verification module is connected with the data latch module to obtain configuration data and the configuration data after trimming for comparison and output a verification result.
The data latch module comprises a first-stage latch and a second-stage latch which are connected, wherein the first-stage latch is connected with the data selection module, the second-stage latch is connected with the data driving module, and the two-stage latches are both connected with the data verification module. When the data read-write control circuit writes data, the data selection module gates the configuration data channel to latch the configuration data to the first-stage latch of the data latch module, then latches the configuration data in the first-stage latch to the second-stage latch, and the data driving module outputs the configuration data latched by the second-stage latch. When the data read-write control circuit performs data write-back, the second-stage latch of the data latch module keeps latching the configuration data, and the data selection module gates the write-back data channel to latch the modified configuration data read_data to the first-stage latch of the data latch module. The modified configuration data read_data in the first-stage latch and the configuration data in the second-stage latch are transmitted to the data verification module for comparison.
Then, as shown in fig. 2, in one embodiment, the data latch module having a two-stage latch structure includes a first-stage latch formed by a second inverter T2 and a first inverter T1 connected in reverse, and a second-stage latch formed by a fourth inverter T4 and a third inverter T3 connected in reverse, wherein:
the output end of the second inverter T2 is connected to the input end of the first inverter T1 and to the drain electrode of the fifth NMOS transistor N5, and the gate electrode of the fifth NMOS transistor N5 is controlled by the zeroth control signal row0. The source electrode of the fifth NMOS tube N5 is connected with the drain electrode of the fifteenth NMOS tube N15, the source electrode of the fifteenth NMOS tube N15 is grounded, and the grid electrode of the fifteenth NMOS tube N15 is used as the input end of the data latch module to acquire the data sel_d selected by the data selection module. The input end of the second inverter T2 is connected to the output end of the first inverter T1 and to the drain electrode of the sixth NMOS transistor N6, the source electrode of the sixth NMOS transistor N6 is grounded, and the gate electrode of the sixth NMOS transistor N6 is controlled by the first reset signal rst.
The output end of the fourth inverter T4 is connected with the input end of the third inverter T3 and is connected to the drain electrode of the zeroth PMOS tube P0, the source electrode of the zeroth PMOS tube P0 is connected with the working power supply VDD, and the grid electrode is controlled by the second reset signal nrst. The input end of the fourth inverter T4 is connected with the output end of the third inverter T3 and is used as the output end of the data latch module to be connected with the data driving module.
The output end of the fourth inverter T4 is also connected with the drain electrode of a third PMOS tube P3, the source electrode of the third PMOS tube P3 is connected with the drain electrode of the first PMOS tube P1, the grid electrode of the third PMOS tube P3 is connected with the output end of the second inverter T2, the source electrode of the first PMOS tube P3 is connected with the working power supply VDD, and the grid electrode of the P1 is controlled by a write-back latch signal read_nrst. The input end of the fourth inverter T4 is connected with the drain electrode of the fourth PMOS tube P4, the source electrode of the fourth PMOS tube P4 is connected with the drain electrode of the second PMOS tube P2, the grid electrode of the fourth PMOS tube P4 is connected with the output end of the first inverter T1, the source electrode of the second PMOS tube P2 is connected with the working power supply VDD, and the grid electrode of the second PMOS tube P2 is controlled by the write-in latch signal write_nrst.
In another embodiment, as shown in fig. 3, in the data verification module, the gates of the seventh PMOS transistor P7 and the tenth NMOS transistor N10 are connected and controlled by the configuration data latched by the second stage latch, and in combination with the circuit of fig. 2, that is, the gates of P7 and N10 are connected to the output terminal q1 of T4. The source electrode of the seventh PMOS tube P7 is connected with the working power supply VDD, the source electrode of the tenth NMOS tube N10 is grounded, the drain electrodes of the seventh PMOS tube P7 and the tenth NMOS tube N10 are connected and connected with the grid electrodes of the ninth PMOS tube P9 and the twelfth NMOS tube N12, the drain electrodes of the ninth PMOS tube P9 and the twelfth NMOS tube N12 are connected and connected with the grid electrode of the thirteenth NMOS tube N13, the source electrode of the ninth PMOS tube P9 is connected with the grid electrode of the eleventh NMOS tube N11 and controlled by the modified configuration data latched by the first-stage latch, and the circuit of FIG. 2, namely, the source electrode of the P9 and the grid electrode of the N11 are connected to the output end q of the T1. The source electrode of the eleventh NMOS tube N11 is connected with the source electrode of the eighth PMOS tube P8 and is connected with the drain electrode of the seventh PMOS tube P7, the drain electrode of the eleventh NMOS tube N11 is connected with the drain electrode of the eighth PMOS tube P8 and is connected with the grid electrode of the thirteenth NMOS tube N13, the grid electrode of the eighth NMOS tube P8 and the source electrode of the twelfth NMOS tube N12 are controlled by the same signal and are opposite to the signal of the modified configuration data latched by the first-stage latch, and the circuit of FIG. 2 is combined, namely, the source electrode of the N12 and the grid electrode of the P8 are connected with the input end qn of the T1. The source electrode of the thirteenth NMOS tube N13 is grounded, the drain electrode is used for outputting a verification result verify_d, and when the configuration data after trimming latched by the first-stage latch is identical to the configuration data latched by the second-stage latch, namely q is identical to q1, the verification result output by the data verification module is high level and indicates that verification is passed. Otherwise, the checking result output by the data checking module is low level and indicates that the checking is not passed.
Based on the circuit diagrams shown in fig. 2 and 3, the waveforms of the main signals of the data read-write control circuit when writing data are shown in fig. 4, the waveforms of the main signals when writing data back and verifying are shown in fig. 5, and the working process is as follows:
when the data read-write control circuit performs data writing, the first reset signal rst is controlled to be in a high level to reset the first-stage latch, so that the output end q of the first inverter T1 is in a low level, and the input end qn is in a high level. The data selection module gates the configuration data channels to write configuration data into the data latch module, and the configuration data is latched at the output q of the first inverter T1 when the control zeroth control signal row0 is high. The second reset signal nrst is controlled to be high to reset the second-stage latch, the output terminal q1 of the fourth inverter T4 is controlled to be high, the input terminal qn1 is controlled to be low, and when the write latch signal write_nrst is controlled to be low, the configuration data of the output terminal q of the first inverter T1 is latched to the output terminal q1 of the fourth inverter T4. Then, the first driving enable signal program_en is controlled to be high level, the second driving enable signal program_en is controlled to be low level, and the data of the output terminal q1 of the fourth inverter T4 is outputted through the data driving module.
When the data read-write control circuit performs data write-back and verification, the output end q1 of the fourth inverter T4 is kept to latch configuration data, and the first reset signal rst is controlled to be high level to reset the first-stage latch, so that the output end q of the first inverter T1 is low level, and the input end qn is high level. And controlling the read_ctrl1 to be at a high level, and reading back the configuration data of the BL end to the data trimming module to carry out data trimming and then outputting trimmed configuration data read_data. The data selection module gates back the write data channel to write the modified configuration data read_data into the data latch module by controlling the read_ctrl0 and the read_shift_en to be high and the shift_n to be low. When the zeroth control signal row0 is controlled to be at a high level, the trimming configuration data read_data is latched at the output q of the first inverter T1. The output q1 of the first inverter T1 and the output q1 of the fourth inverter T4 are transmitted to the data verification module for comparison. After verification, the write-back latch signal read_nrst is controlled to be at a low level, and the modified configuration data read_data of the output end q of the first inverter T1 is latched to the output end q1 of the fourth inverter T4. The first driving enable signal program_en is controlled to be at a high level, the second driving enable signal program_en is controlled to be at a low level, and the modified configuration data read_data of the output end q1 of the fourth inverter T4 is output through the data driving module.
When the data read-write control circuit is practically applied, the data read-write control circuit comprises a plurality of parallel basic units, each basic unit respectively comprises a data selection module, a data latch module, a data driving module, a read-back control module and a data trimming module, and the circuit structure is formed, so that the plurality of basic units form the control circuit of the flash memory cell array in parallel, and the data read-write control circuit is suitable for large-scale programmable logic devices.
The above is only a preferred embodiment of the present application, and the present application is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present application are deemed to be included within the scope of the present application.
Claims (10)
1. The data read-write control circuit for the flash type programmable logic device is characterized by comprising a data selection module, a data latch module, a data driving module, a read-back control module and a data trimming module, wherein the data selection module comprises a configuration data channel and a read-back data channel, the input end of the configuration data channel is used as the data end of the data read-write control circuit to acquire configuration data, the output end of the configuration data channel is connected with the output end of the read-back data channel and is connected with the input end of the data latch module, the output end of the data latch module is connected with the input end of the data driving module, the output end of the data driving module is used as the output end of the data read-write control circuit to be connected with a flash storage unit, the output end of the data driving module is also connected with the input end of the data trimming module through the read-back control module, and the output end of the data trimming module is connected with the input end of the read-back data channel;
when the data read-write control circuit writes data, the data selection module gates the configuration data channel to write configuration data into the data latch module for latching, and then the data drive module outputs corresponding configuration data and writes the configuration data into the flash memory unit;
when the data read-write control circuit performs data write-back, the configuration data of the output end of the data driving module is transmitted to the data trimming module through the read-back control module to be trimmed so as to obtain trimmed configuration data, the write-back data channel is gated by the data selection module, the trimmed configuration data is written into the data latch module to be latched, and then the trimmed configuration data is output through the data driving module and written into the flash memory unit.
2. The data read-write control circuit according to claim 1, further comprising a data verification module, wherein the data verification module is connected to the data latch module to obtain configuration data and to compare the configuration data after trimming and output a verification result.
3. The data read-write control circuit according to claim 2, wherein the data latch module comprises a first stage latch and a second stage latch connected to each other, the first stage latch is connected to the data selection module, the second stage latch is connected to the data driving module, and both stages of latches are connected to the data verification module;
when the data read-write control circuit performs data writing, the data selection module gates the configuration data channel to latch configuration data to a first-stage latch of the data latch module, then latches the configuration data in the first-stage latch to a second-stage latch, and the data driving module outputs the configuration data latched by the second-stage latch;
when the data read-write control circuit performs data write-back, the second-stage latch of the data latch module keeps latching configuration data, and the data selection module gates the write-back data channel to latch the trimmed configuration data to the first-stage latch of the data latch module;
and the trimmed configuration data in the first-stage latch and the configuration data in the second-stage latch are transmitted to the data verification module for comparison.
4. The data read-write control circuit according to claim 3, wherein the data latch module includes a first stage latch constituted by a second inverter and a first inverter connected in reverse, and a second stage latch constituted by a fourth inverter and a third inverter connected in reverse, wherein:
the output end of the second inverter is connected with the input end of the first inverter and is connected to the drain electrode of a fifth NMOS tube, the grid electrode of the fifth NMOS tube is controlled by a zeroth control signal, the source electrode of the fifth NMOS tube is connected with the drain electrode of the fifteenth NMOS tube, the source electrode of the fifteenth NMOS tube is grounded, and the grid electrode of the fifteenth NMOS tube is used as the input end of the data latch module; the input end of the second inverter is connected with the output end of the first inverter and connected to the drain electrode of a sixth NMOS tube, the source electrode of the sixth NMOS tube is grounded, and the grid electrode of the sixth NMOS tube is controlled by a first reset signal;
the output end of the fourth inverter is connected with the input end of the third inverter and is connected to the drain electrode of the zeroth PMOS tube, the source electrode of the zeroth PMOS tube is connected with a working power supply, the grid electrode of the zeroth PMOS tube is controlled by a second reset signal, and the input end of the fourth inverter is connected with the output end of the third inverter and is used as the output end of the data latch module;
the output end of the fourth phase inverter is also connected with the drain electrode of the third PMOS tube, the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the third PMOS tube is connected with the output end of the second phase inverter, the source electrode of the first PMOS tube is connected with the working power supply, the grid electrode of the first PMOS tube is controlled by a write-back latch signal, the input end of the fourth phase inverter is connected with the drain electrode of the fourth PMOS tube, the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube is connected with the output end of the first phase inverter, the source electrode of the second PMOS tube is connected with the working power supply, and the grid electrode of the second PMOS tube is controlled by a write-in latch signal.
5. The data read/write control circuit according to claim 4, wherein,
when the data read-write control circuit performs data writing, the first reset signal is controlled to be at a high level to reset the first-stage latch, so that the output end of the first inverter is at a low level, the input end of the first inverter is at a high level, the data selection module gates the configuration data channel to write configuration data into the data latch module, and when the zeroth control signal is controlled to be at a high level, the configuration data is latched at the output end of the first inverter; the second reset signal is controlled to be high level to reset the second-stage latch, the output end of the fourth inverter is high level, the input end of the fourth inverter is low level, when the write latch signal is controlled to be low level, the configuration data of the output end of the first inverter is latched to the output end of the fourth inverter, and the data of the output end of the fourth inverter is output through the data driving module;
when the data read-write control circuit performs data read-back and verification, the output end of the fourth inverter is kept to be locked with the configuration data, the first reset signal is controlled to be high level to reset the first-stage latch, the output end of the first inverter is enabled to be low level, the input end of the first inverter is enabled to be high level, the read-back enabling signal is controlled to be high level, the configuration data at the output end of the data driving module is read back to the data trimming module to output trimming configuration data after trimming, the write-back control signal and the write-back shift enabling signal are controlled to be high level, the initial value enabling signal is controlled to be low level, the data selecting module gates the trimming configuration data into the data latch module through the write-back data channel, and the trimming configuration data is latched at the output end of the first inverter when the zeroth control signal is controlled to be high level; and the output end of the first inverter and the output end of the fourth inverter are transmitted to the data verification module for comparison, after verification is passed, the write-back latch signal is controlled to be low level, the trimming configuration data of the output end of the first inverter is latched to the output end of the fourth inverter, and the trimming configuration data of the output end of the fourth inverter is output through the data driving module.
6. The data read-write control circuit according to claim 4, wherein in the data verification module, a seventh PMOS tube is connected to a gate of a tenth NMOS tube and is controlled by configuration data latched by the second stage latch, a source of the seventh PMOS tube is connected to a working power supply, a source of the tenth NMOS tube is grounded, a drain of the seventh PMOS tube is connected to a drain of the tenth NMOS tube and is connected to a gate of a ninth PMOS tube and is connected to a drain of the twelfth NMOS tube, a drain of the ninth PMOS tube is connected to a gate of a thirteenth NMOS tube, a source of the ninth PMOS tube is connected to a gate of an eleventh NMOS tube and is controlled by configuration data latched by the first stage latch, a source of the eleventh NMOS tube is connected to a source of the eighth PMOS tube and is connected to a drain of the seventh PMOS tube, a drain of the eleventh NMOS tube is connected to a drain of the eighth PMOS tube and is connected to a gate of the thirteenth NMOS tube, and a gate of the eighth NMOS tube and is connected to a gate of the thirteenth NMOS tube and is controlled by a latch of the same configuration data latched by the first stage latch and the same PMOS signal as the twelfth NMOS tube;
and the source electrode of the thirteenth NMOS tube is grounded, the drain electrode of the thirteenth NMOS tube is used for outputting a verification result, and when the trimming configuration data latched by the first-stage latch is the same as the configuration data latched by the second-stage latch, the verification result output by the data verification module is high level and indicates that verification passes, otherwise, the verification result output by the data verification module is low level and indicates that verification does not pass.
7. The data read-write control circuit according to any one of claims 1 to 6, wherein,
the configuration data channel in the data selection module comprises a zeroth NMOS tube, a first NMOS tube and a second NMOS tube, wherein the drain electrode of the zeroth NMOS tube is used as the data end of the data read-write control circuit, the source electrode of the zeroth NMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is used as the output end of the configuration data channel; the grid electrode of the zeroth NMOS tube is controlled by a second control signal, the grid electrode of the first NMOS tube is controlled by a first control signal, and the grid electrode of the second NMOS tube is controlled by a shift enabling signal;
the write-back data channel in the data selection module comprises a third NMOS tube and a fourth NMOS tube, wherein the drain electrode of the third NMOS tube is used as the input end of the write-back data channel, the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube is used as the output end of the write-back data channel; the grid electrode of the third NMOS tube is controlled by a write-back control signal, and the grid electrode of the fourth NMOS tube is controlled by a write-back shift enabling signal;
the data selection module further comprises a fourteenth NMOS tube connected with the output ends of the configuration data channel and the write-back data channel through a drain electrode, wherein the source electrode of the fourteenth NMOS tube is grounded, the grid electrode of the fourteenth NMOS tube is controlled by an initial value enabling signal, and when data writing and data write-back are performed, the initial value enabling signal is in a low level;
when the first control signal, the second control signal and the shift enable signal are all high-level, the data selection module gates the configuration data channel; when the write back control signal and the write back shift enable signal are both high, the data selection module gates the write back data channel.
8. The data read-write control circuit according to any one of claims 1 to 6, wherein in the data driving module, a source electrode of a fifth PMOS tube is connected to a working power supply, a drain electrode of the fifth PMOS tube is connected to a source electrode of a sixth PMOS tube, a drain electrode of the sixth PMOS tube is connected to a drain electrode of an eighth NMOS tube, a source electrode of the eighth NMOS tube is connected to a drain electrode of a seventh NMOS tube, a source electrode of the seventh NMOS tube is grounded, a gate electrode of the fifth PMOS tube is connected to a gate electrode of the eighth NMOS tube and is used as an input end of the data driving module, a gate electrode of the seventh NMOS tube is controlled by a first driving enable signal, a gate electrode of the sixth PMOS tube is controlled by a second driving enable signal, and a common end of the sixth PMOS tube and the eighth NMOS tube is used as an output end of the data driving module;
when the first driving enabling signal is in a high level and the second driving enabling signal is in a low level, the data driving module outputs the data latched by the data latching module.
9. The data read-write control circuit according to any one of claims 1 to 6, wherein the data read-write control circuit comprises a plurality of parallel basic units, each of which comprises the data selection module, the data latch module, the data driving module, the read-back control module and the data trimming module, respectively.
10. The data read-write control circuit according to any one of claims 1 to 6, wherein the read-back control module is a ninth NMOS controlled by a read-back enable signal, a source of the ninth NMOS is connected to an output of the data driving module, and a drain of the ninth NMOS is connected to an input of the data trimming module.
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| CN101656097A (en) * | 2009-08-28 | 2010-02-24 | 苏州东微半导体有限公司 | Sensitive amplifier circuit applied to semiconductor memory and work method thereof |
| CN111489774A (en) * | 2020-04-09 | 2020-08-04 | 无锡中微亿芯有限公司 | Improved data relay structure for configuration memory of programmable logic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101656097A (en) * | 2009-08-28 | 2010-02-24 | 苏州东微半导体有限公司 | Sensitive amplifier circuit applied to semiconductor memory and work method thereof |
| CN111489774A (en) * | 2020-04-09 | 2020-08-04 | 无锡中微亿芯有限公司 | Improved data relay structure for configuration memory of programmable logic device |
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