CN114171090A

CN114171090A - Hierarchical word line preprocessing circuit of flash type FPGA

Info

Publication number: CN114171090A
Application number: CN202111469888.XA
Authority: CN
Inventors: 曹正州; 张艳飞; 何小飞; 祝洁; 徐玉婷; 耿杨
Original assignee: Wuxi Zhongwei Yixin Co Ltd
Current assignee: Wuxi Zhongwei Yixin Co Ltd
Priority date: 2021-12-03
Filing date: 2021-12-03
Publication date: 2022-03-11

Abstract

The invention discloses a hierarchical word line preprocessing circuit of a flash type FPGA, which relates to the field of the FPGA.A decoding circuit connected with a word line is controlled by a plurality of control circuits forming a hierarchical corresponding structure, each decoding unit is controlled by a read-write signal, an erasing signal and a selection signal respectively output by the corresponding control unit of each level, and accordingly, the word line control signal is pulled up to a variable positive voltage or pulled down to a negative voltage to provide a grid voltage required for executing programming, erasing, programming and reading operations for a storage unit controlled by the connected word line; the hierarchical management mode simplifies a decoding circuit, reduces the resource overhead of hardware logic, can reduce the interference between different control units during the operation of the storage unit, and plays a key role in the rapid integration of the flash type FPGA.

Description

Hierarchical word line preprocessing circuit of flash type FPGA

Technical Field

The invention relates to the field of FPGA, in particular to a hierarchical word line preprocessing circuit of a flash type FPGA.

Background

The flash type FPGA is based on a flash storage technology capable of being configured repeatedly, and changes the logic relation in a circuit by reprogramming a flash storage unit, so that different logic functions of a user are realized. The flash memory unit belongs to nonvolatile memory, and information cannot be lost when the chip is restarted after power failure, so that the flash memory unit becomes the mainstream of a programmable logic device and is widely applied to the field of signal processing and control. The configuration of a memory cell (flash cell) in a flash type FPGA is a premise of logic application of a programmable logic device, wherein a Word Line (WL) is connected to a grid electrode of the flash cell, corresponding voltage needs to be given to the flash cell in the erasing, programming and reading processes of the flash cell, and how to prepare for realizing the function efficiently plays a key role in the rapid integration of the flash type FPGA.

Disclosure of Invention

The invention provides a hierarchical word line preprocessing circuit of a flash type FPGA aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:

a hierarchical word line preprocessing circuit of a flash type FPGA comprises a K-layer control circuit and a decoding circuit, wherein K is more than or equal to 2;

the first layer control circuit comprises a plurality of first control units, each K-1 control unit in the K-1 layer control circuit corresponds to a plurality of kth control units in the kth layer control circuit, K is a parameter, K is more than or equal to 2 and less than or equal to K, and each kth control unit in the kth layer control circuit corresponds to one decoding unit in the decoding circuit; each decoding unit leads out a word line control signal and is connected with one word line in the FPGA;

each decoding unit is controlled by a read-write signal, an erase signal and a word line gating signal, wherein the word line gating signal comprises a word line gating signal formed by K-path selection signals respectively output by K control units of different levels corresponding to the decoding units, the decoding units are used for pulling up the word line control signal to a variable positive voltage according to the acquired signal, providing a gate voltage required by the execution of read-write operation for the storage units controlled by the connected word lines, and pulling down the word line control signal to a negative voltage according to the acquired signal and providing a gate voltage required by the execution of erase operation for the storage units controlled by the connected word lines.

The beneficial technical effects of the invention are as follows:

the application discloses a hierarchical word line preprocessing circuit of a flash FPGA, which provides word line signals for a storage unit array during erasing, programming and reading operations of storage units in the flash FPGA in a hierarchical management mode, simplifies a decoding circuit, reduces resource overhead of hardware logic, and can reduce interference among different control units during the operation of the storage units. Meanwhile, addresses of the flash type FPGA are continuous when the flash type FPGA operates the memory cell array, and 1 is automatically added by an address counter. Each group control unit feeds back a completion signal to the previous stage after completing the read-write operation until all group control units complete the read-write operation, and the signal feedback from bottom to top flexibly realizes the selection of a flash cell array block (corresponding to a block control unit Bank), and especially plays a key role in the rapid integration of large-scale flash type programmable devices.

Drawings

Fig. 1 is a schematic diagram showing a correspondence relationship between control circuits of different levels in a case where 9216 word lines are formed in three levels of control circuits.

Fig. 2 is a schematic circuit diagram of a block control unit and its corresponding group control unit in one embodiment.

Fig. 3 is a schematic circuit diagram of each address latch unit corresponding to one group control unit and its corresponding block control unit, group control unit and decoding unit in one embodiment.

Detailed Description

The following further describes the embodiments of the present invention with reference to the drawings.

The application discloses hierarchical word line preprocessing circuit of flash type FPGA, the inside memory cell (flash cell) that includes a plurality of constitution determinant structure of flash type FPGA, each word line WL controls the grid of a plurality of memory cell, specifically, generally connects the grid of a plurality of memory cell of same row. Each group of bit lines BL/BLN controls the drains and sources of a number of memory cells, typically connected in the same column. The word line and the bit line are matched together to realize read-write and erase operations on the memory cell array, in the process, the word line needs to provide a needed grid voltage for the memory cell, and the hierarchical word line preprocessing circuit is used for realizing the function.

The word line preprocessing circuit comprises a K-layer control circuit and a decoding circuit, wherein K is more than or equal to 2. The first layer control circuit comprises a plurality of first control units, each K-1 control unit in the K-1 layer control circuit corresponds to a plurality of K control units in the K layer control circuit, K is a parameter, and K is more than or equal to 2 and less than or equal to K. Each Kth control unit in the Kth layer control circuit corresponds to one decoding unit in the decoding circuit. Each decoding unit leads out a word line control signal and is connected with one word line in the FPGA.

The control units of the next level corresponding to any two control units in the same level are not overlapped, and the control units of the next level corresponding to all the control units in the same level cover all the control units of the next level. The number of control units of each level is determined according to the number of word lines actually included in the flash type FPGA, or the layout structure of the memory cells and the word lines is sometimes considered.

Optionally, the number of the control units of the next hierarchy corresponding to any two control units located in the same hierarchy is the same or different. For example, one first control unit corresponds to 12 second control units, another second control unit may also correspond to 12 second control units, and then two first control units correspond to the same number of second control units respectively. Or, another second control unit corresponds to 16 second control units, and then the two first control units correspond to different numbers of second control units respectively. However, in general, a regular structure is adopted in which any two control units correspond to the same number of control units of the next hierarchy.

In one embodiment, K is 3, the hierarchical word line preprocessing circuit includes three layers of control circuits, the first layer of control circuit includes a plurality of block control units (banks) as first control units, the second layer of control circuit includes a plurality of Group control units (banks) as second control units, and the third layer of control circuit includes a plurality of address Latch units (latches) as third control units, which is a relatively common architecture in practice.

Based on this architecture, assuming that the flash FPGA includes 9216 word lines in total, a specific implementation manner of the hierarchical word line preprocessing circuit is as follows, referring to fig. 1: the first-layer control circuit comprises 16 block control units which are respectively recorded as Bank 0-Bank 15, wherein the block control unit Bank0 corresponds to 12 Group control units of the second-layer control circuit and is respectively recorded as Group 0-Group 11, and the Group control unit Group0 corresponds to 48 address Latch units of the third-layer control circuit and is respectively recorded as Latch 0-Latch 47. The address Latch units Latch 0-Latch 47 correspond to one decoding unit and are respectively marked as Decode 0-Decode 47, and each decoding unit is used for leading out a word line control signal and is connected with one word line in the FPGA and is respectively marked as WL <0> to WL <47 >. The remaining block control units, group control units, and address latch units are similar.

It can be seen that, based on the structure of the present application, each decoding unit corresponds to K control units of different levels, that is, the kth control unit corresponding to the decoding unit and other levels respectively have corresponding control units, specifically, the kth control unit corresponding to the decoding unit, the kth-1 control unit … … of the previous layer corresponding to the kth control unit corresponding to the decoding unit, and so on until the first control unit. Each decoding unit acquires K paths of selection signals respectively output by the corresponding K control units of different levels, and records the K paths of selection signals as word line gating signals. For example, when K is 3, each decoding unit obtains a word line gating signal formed by three selection signals output by the corresponding address latch unit, the group control unit and the block control unit respectively.

Each decoding unit is controlled by a read-write signal PG _ RD _ b, an ERASE signal ERASE and a received word line gating signal, and pulls up a word line control signal to a variable positive voltage VPC according to the three acquired signals so as to provide a gate voltage required for executing read-write operation for the storage unit controlled by the connected word line. And the decoding unit is also used for pulling down the word line control signal to a negative voltage VGC according to the three acquired signals and providing a gate voltage required by the execution of the erasing operation for the memory cells controlled by the connected word line.

Optionally, the read-write operation performed on the memory cell controlled by the word line includes a programming operation and a read operation, and then: the decoding unit pulls up the extracted word line control signal to a variable positive voltage having a voltage value of a program voltage value to provide a gate voltage required to perform a program operation for the memory cells controlled by the connected word line. Alternatively, the decoding unit pulls up the extracted word line control signal to a variable positive voltage whose voltage value is a read voltage value to supply a gate voltage required for performing a read operation to the memory cell controlled by the connected word line. The programming voltage is greater than the read voltage, which is generally equal to the core voltage by 1.5V, the programming voltage is high voltage, such as 12.5V, and the negative voltage VGC is preferably-16.5V.

In the erasing process of the memory cells, all the decoding units acquire a read-write signal PG _ RD _ b with an invalid level and an erasing signal ERASE with an effective level, all the decoding units acquire a word line gating signal for indicating to gate a connected word line and pull down the led word line control signal to a negative voltage VGC, so that the memory cells controlled by all the word lines are provided with gate voltages required by executing erasing operation, and all the memory cells of the whole chip are erased together.

In the process of reading and writing the storage units, all the decoding units acquire a read-write signal PG _ RD _ b with an effective level and an ERASE signal ERASE with an invalid level, and all the decoding units sequentially acquire word line gating signals for indicating to gate the connected word lines and pull up the led word line control signals to variable positive voltages so as to sequentially provide gate voltages required by executing read-write operations to the storage units controlled by all the word lines, so that all the storage units of the whole chip sequentially read and write according to the word line gating signals of the connected word lines.

In the above process, when each decoding unit acquires K effective selection signals output by each corresponding control unit, it is confirmed that a word line gating signal for instructing to gate a connected word line is received, that is, it is confirmed that a valid word line gating signal is received. For example, when K is 3, the word line gating signal acquired by each decoding unit for instructing to gate the connected word line includes three effective selection signals respectively output by the corresponding address latch unit, the group control unit, and the block control unit. Specifically, taking the typical embodiment with K being 3 as an example, each block control unit in the hierarchical word line preprocessing circuit sequentially outputs an effective selection signal; when one block control unit outputs an effective selection signal, each corresponding group control unit is controlled to sequentially output the effective selection signal; and when one group control unit outputs an effective selection signal, controlling each corresponding address latch unit to sequentially output the effective selection signal, so that each decoding unit sequentially acquires a word line gating signal for indicating to gate the connected word line.

Referring to the specific circuit diagrams shown in fig. 2 and fig. 3, each Group control unit is implemented based on a D flip-flop, the D flip-flops in the Group control units Group0 to Group47 are respectively denoted as DFF0 to DFF47, a Q terminal of each D flip-flop in each Group control unit corresponding to the same block control unit is connected to a D terminal of a D flip-flop in the next stage to form a cascade structure, a D terminal of a D flip-flop in the first stage is connected to a shift enable signal shift _ EN, and a Q terminal of a D flip-flop in each stage also outputs a selection signal of the Group control unit to which the D flip-flop belongs. In the process of reading and writing the storage unit, a shift enabling signal shift _ EN is at a high level, the CP end of each D trigger is connected with a sampling clock CP, and after the sampling clock CP is changed into the high level, the Q end of the output end of the D trigger is at the high level, so that an effective selection signal is output. Specifically, the Q terminal of each stage of D flip-flop outputs the selection signal of the belonging group control unit sequentially through the buffer supplied with the configuration voltage VCC and the ground terminal and the buffer supplied with the variable positive voltage VPC and the negative voltage VGC. Optionally, a path of the selection signal output by each control unit of each layer of control circuit includes a first signal and a second signal that are opposite in phase, so that each path of the valid selection signal actually includes the first signal and the second signal that are respectively at an active level. For example, as shown in fig. 2, the selection signal output by one Group control unit Group0 includes a first signal Group <0> and its inverted second signal Group _ b <0>, the first signal is active high, the second signal is active low, the active selection signal output by Group0 includes the first signal high and the second signal low, and so on.

Each Group control unit further comprises a pull-down NMOS tube, and the pull-down NMOS tubes in the Group control units from Group0 to Group47 are respectively marked as G _ N0 to G _ N47. The source electrode of the pull-down NMOS tube is grounded, and the grid electrode of the pull-down NMOS tube is connected with the Q end of the D trigger in the group control unit. The drains of the pull-down NMOS tubes in each group of control units corresponding to the same block control unit are connected to the feedback end of the block control unit. When any one group control unit outputs an effective selection signal, namely when the Q end of the D trigger in any one group control unit is at a high level, the pull-down NMOS tube is pulled down to the ground, and the block control unit receives a feedback signal Fb of the effective level through the feedback end, namely receives a low level. When the block selection signal receives an active block selection signal WL _ SEL and receives an active level feedback signal Fb through the feedback terminal, the block control unit outputs the active selection signal.

Referring to fig. 2, each block control unit includes a PMOS inverter P0 and NMOS transistors N0, N1 and N2, the source of P0 is connected to the core voltage, the drain is connected to the drain of N0, the source of N0 is grounded, the gate of P0 is connected to the gate of N0 and is connected to the low-level active configuration enable signal CFG _ B, the common terminal of P0 and N0 is connected to the output select signal sequentially through an inverter and a buffer, the inverter is powered by the configuration voltage VCC and the ground, and the buffer is powered by the variable positive voltage VPC and the ground. The configuration voltage VCC is 3.3V. The common end of P0 and N0 is also connected with the drain of N2, the source of N2 is connected with the drain of N1, and the source of N1 is grounded. The block select signal WL _ SEL connects the gates of N2. The block select signal WL _ SEL is also connected to the gate of N1 through an inverter powered by the core voltage VDD and ground. The common terminal of N1 and N2 is used as the feedback terminal of the block control unit to acquire the feedback signal Fb. When the block control unit acquires a block selection signal WL _ SEL that is active at a high level and simultaneously receives a feedback signal Fb that is active at a low level, an active selection signal is output. Similarly, the path of selection signal output by the block control unit also includes a first signal and a second signal with opposite phases. For example, as shown in fig. 2, the selection signal output by one block control unit Bank0 includes a first signal Bank <0> and an inverted second signal Bank _ b <0>, the first signal is active high, the second signal is active low, the active selection signal output by Bank0 includes a first signal high and a second signal low, and so on for the other block control units.

Each address Latch unit is constructed based on latches, as shown in FIG. 3, the address Latch units corresponding to one Group control unit Group0 are respectively marked as Latch 0-Latch 47, and the D end of each Latch acquires corresponding address signals respectively marked as A <0> -A <47 >. Meanwhile, address signals are continuous when reading and writing operations are carried out on the array formed by the memory units, and 1 is automatically added by an address counter. The CP end of the latch acquires a sampling clock, after the sampling clock CP is changed into a high level, the address latch unit is opened, the address signal takes effect, and the latch outputs the high level through the Q end and outputs the low level through the QN end. Similarly, the one-path selection signal output by the address latch unit also comprises a first signal and a second signal which are opposite in phase. For example, as shown in fig. 3, the selection signal output by one address Latch unit Latch0 includes a first signal Addr <0> output through the Q terminal of the Latch and an inverted second signal Addr _ d <0> output through the QN terminal of the Latch, the first signal is active high, the second signal is active low, the active selection signal output by the address Latch unit Latch0 includes a first signal high and a second signal low, and so on for the other block control units.

Each decoding unit comprises a pull-up component and a pull-down component which are connected in series, the decoding unit is connected with a variable positive voltage VPC through the pull-up component and is connected with a negative voltage VGC through the pull-down component, and word line control signals led out from the common ends of the pull-up component and the pull-down component are respectively connected to word lines WL <0> to WL <47 >. The pull-up component of the decoding unit is controlled by the read-write signal PG _ RD _ b and K second signals respectively output by K control units of different levels corresponding to the decoding unit, and the pull-down component is controlled by the ERASE signal ERASE and K first signals respectively output by K control units of different levels corresponding to the decoding unit. When the decoding unit receives a first signal of K-way active level and a second signal of K-way active level, it is determined that a word line strobe signal for instructing to strobe a connected word line is received.

Specifically, the circuit structures of the decoding units are the same, taking decoding unit Decode0 as an example: the pull-up component comprises four PMOS tubes, namely W _ P0, W _ P1, W _ P2 and W _ P3, the source electrode of the W _ P3 is connected with the variable positive voltage VPC, the drain electrode of the W _ P3 is connected with the source electrode of the W _ P2, the drain electrode of the W _ P2 is connected with the source electrode of the W _ P1, and the drain electrode of the W _ P1 is connected with the source electrode of the W _ P0. The drain of W _ P0 is used to connect the pull-down element and to pull out the word line control signal. The gate of W _ P3 is controlled by the active low read/write signal PG _ RD _ b. The gate of W _ P0 is controlled by the second signal Bank _ b <0> outputted by the block control unit corresponding to the decoding unit, the gate of W _ P1 is controlled by the second signal Group _ b <0> outputted by the Group control unit corresponding to the decoding unit, the gate of W _ P2 is controlled by the second signal Latch _ b <0> outputted by the address Latch unit corresponding to the decoding unit, and the three second signals are all active at low level.

The pull-down component comprises four NMOS transistors which are respectively W _ N0, W _ N1, W _ N2 and W _ N3, the source electrode of the W _ N0 is connected with the negative voltage VGC, the drain electrode of the W _ N1 is connected with the source electrode of the W _ N1, the drain electrode of the W _ N1 is connected with the source electrode of the W _ N2, the drain electrode of the W _ N2 is connected with the source electrode of the W _ N3, the drain electrode of the W _ N3 is used for connecting the pull-down component and leading out a word line control signal, and the grid electrode of the W _ N0 is controlled by an effective ERASE signal ERASE with high level. The grid of W _ N3 is controlled by the first signal Bank <0> output by the block control unit corresponding to the decoding unit, the grid of W _ N2 is controlled by the first signal Group <0> output by the Group control unit corresponding to the decoding unit, the grid of W _ N1 is controlled by the first signal Latch <0> output by the address Latch unit corresponding to the decoding unit, and the three first signals are all high level and effective.

It is determined that a word line gating signal for instructing to gate the connected word line is received when the decoding unit receives the three-way high-level first signal and the three-way low-level second signal.

Based on the circuits shown in fig. 2 and fig. 3, the operation process of the hierarchical word line preprocessing circuit is as follows:

in the erasing process of the memory unit, all the decoding units acquire an invalid high-level read-write signal PG _ RD _ b and an effective high-level erasing signal ERASE, so that W _ P3 is turned off, and W _ N0 is turned on. All the block control units output a first signal Bank < > of high level and a second signal Bank _ b < >, all the Group control units output a first signal Group < > of high level and a second signal Group _ b < >, all the address Latch units output a first signal Latch < > of high level and a second signal Latch _ b < >, and all the decoding units receive word line strobe signals respectively corresponding to the word lines for indicating strobe of the connected word lines. In each decoding unit, the PMOS transistor W _ P3 is turned off, the PMOS transistors W _ P0, W _ P1 and W _ P2 are turned on, the NMOS transistors W _ N0, W _ N1, W _ N2 and W _ N3 are all turned on, the decoding unit pulls down the extracted word line control signal to a negative voltage VGC, and simultaneously provides the gate voltage required for executing the erasing operation to the memory cells controlled by each word line, so that all the memory cells of the whole chip are erased together.

In the process of reading and writing the memory cell, the reading and writing processes are similar, only the voltage value of VPC is different, and therefore, only the programming process of the memory cell is taken as an example. All decoding units acquire an effective low-level read-write signal PG _ RD _ b and an ineffective low-level ERASE signal ERASE, so that W _ P3 is turned on and W _ N0 is turned off. After the D terminal of DFF0 goes high and the CP terminal goes high, the Q terminal of DFF0 goes high, so that Group <0> goes high, Group _ b <0> goes low, and Group0 is selected. Meanwhile, the feedback terminal of the block control cell Bank0 (i.e., the drain terminal of N1) is low due to the pull-down of G _ N0. Bank0 is selected when WL _ SEL is active high, in conjunction with the low at the drain of N1, so that Bank <0> is high and Bank _ b <0> is low. After Group0 is selected, Latch0 is turned on, address A <0> is asserted, Addr <0> is high, and Addr _ b <0> is low. In the Decode0 circuit, the PMOS transistors W _ P0, W _ P1, W _ P2 and W _ P3 are all turned on, the NMOS transistor W _ N0 is turned off, the NMOS transistors W _ N1, W _ N2 and W _ N3 are turned on, and the Decode0 pulls up the word line control signal to a variable positive voltage, so that the gate voltage required for performing the read/write operation is provided to the memory cell controlled by the word line WL <0 >. Latch1 is then turned on, address A <1> is asserted, causing Decode1 to pull up the pulled-out word line control signal to a variable positive voltage, similar to that described above, causing the gate voltage required to perform read and write operations to be provided to the memory cells controlled by word line WL <1 >. According to the above process, Latch 0-Latch 47 are sequentially opened, and addresses A <0> to A <47> are sequentially activated. After all address latch cell traversals corresponding to Group0 are completed. And the Group1 and the following groups are selected in sequence and traversed according to the process, and each Group can provide a feedback signal to the upper-level block control unit after completing the read-write operation until all groups complete the read-write operation, so that the realization is flexible. According to the circulation process, the grid voltage required by the read-write operation is sequentially provided for the storage units controlled by each word line, so that all the storage units of the whole chip are sequentially read and written according to the word line gating signals of the connected word lines.

What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims

1. A hierarchical word line preprocessing circuit of a flash type FPGA is characterized by comprising a K-layer control circuit and a decoding circuit, wherein K is more than or equal to 2;

each decoding unit is controlled by a read-write signal, an erase signal and a word line gating signal, wherein the word line gating signal comprises a word line gating signal formed by K paths of selection signals respectively output by K control units of different levels corresponding to the decoding units, the decoding units are used for pulling up the word line control signal to a variable positive voltage according to the acquired signal, providing a gate voltage required by executing read-write operation for the storage units controlled by the connected word lines, and pulling down the word line control signal to a negative voltage according to the acquired signal and providing a gate voltage required by executing erase operation for the storage units controlled by the connected word lines.

2. The hierarchical word line pre-processing circuit of claim 1,

all decoding units acquire a read-write signal of an effective level and an erase signal of an ineffective level, and all decoding units sequentially acquire a word line gating signal for indicating to gate a connected word line and pull up an extracted word line control signal to a variable positive voltage so as to sequentially provide a gate voltage required for executing read-write operation to a storage unit controlled by each word line;

or all the decoding units acquire the read-write signal of an invalid level and the erase signal of an effective level, and all the decoding units acquire the word line gating signal for indicating to gate the connected word lines and pull down the drawn word line control signal to a negative voltage so as to simultaneously provide the gate voltage required for executing the erase operation to the storage units controlled by the word lines.

3. The hierarchical word line preprocessing circuit of claim 1 or 2, wherein the read and write operations performed on the word line controlled memory cells include a program operation and a read operation, then:

the decoding unit pulls up the extracted word line control signal to a variable positive voltage with a voltage value being a programming voltage value so as to provide a gate voltage required for executing a programming operation for the memory cell controlled by the connected word line;

or the decoding unit pulls up the extracted word line control signal to a variable positive voltage with the voltage value being the read voltage value so as to provide the grid voltage required by the read operation for the memory cell controlled by the connected word line;

the programming voltage value is greater than the read voltage value.

4. The hierarchical word line preprocessing circuit of claim 2, wherein K is 3, the hierarchical word line preprocessing circuit comprises a three-layer control circuit, the first layer control circuit comprises a plurality of block control units as first control units, the second layer control circuit comprises a plurality of group control units as second control units, and the third layer control circuit comprises a plurality of address latch units as third control units; the word line gating signals acquired by each decoding unit and used for indicating to gate the connected word lines comprise three effective selection signals respectively output by the corresponding address latch unit, the group control unit and the block control unit;

each block control unit in the hierarchical word line preprocessing circuit sequentially outputs effective selection signals; when one block control unit outputs an effective selection signal, each corresponding group control unit is controlled to sequentially output the effective selection signal; and when one group control unit outputs an effective selection signal, controlling each corresponding address latch unit to sequentially output the effective selection signal, so that each decoding unit sequentially acquires a word line gating signal for indicating to gate the connected word line.

5. The hierarchical word line preprocessing circuit of claim 4, wherein each group control unit is implemented based on D flip-flops, and a Q terminal of each D flip-flop in each group control unit corresponding to the same block control unit is connected to a D terminal of a D flip-flop of a next stage to form a cascade structure, the D terminal of the D flip-flop of a first stage is connected to a shift enable signal, and the Q terminal of the D flip-flop of each stage further outputs a selection signal of the group control unit to which the D flip-flop of the first stage belongs.

6. The hierarchical word line preprocessing circuit of claim 5, wherein each group control unit further comprises a pull-down NMOS transistor, a source of the pull-down NMOS transistor is grounded, and a gate of the pull-down NMOS transistor is connected to a Q terminal of a D flip-flop in the group control unit; the drain electrodes of the pull-down NMOS tubes in each group control unit corresponding to the same block control unit are connected and connected to the feedback end of the block control unit, and when any one group control unit outputs an effective selection signal, the block control unit receives a feedback signal of an effective level through the feedback end; when the block selection signal receives an effective block selection signal and receives a feedback signal of an effective level through a feedback terminal, the block control unit outputs the effective selection signal.

7. The hierarchical word line preprocessing circuit of claim 6, wherein each block control unit comprises a PMOS inverse ratio transistor P0 and NMOS transistors N0, N1 and N2, the source of P0 is connected to the core voltage, the drain is connected to the drain of N0, the source of N0 is grounded, the gate of P0 is connected to the gate of N0 and is connected to a configuration enable signal, and the common terminal of P0 and N0 is connected to an output selection signal through an inverter and a buffer in turn; the common terminal of P0 and N0 is also connected with the drain of N2, the source of N2 is connected with the drain of N1, the source of N1 is grounded, the block selection signal is connected with the gate of N2, the block selection signal is connected with the gate of N1 through an inverter, and the common terminal of N1 and N2 is used as the feedback terminal of the block control unit.

8. The hierarchical word line preprocessing circuit of claim 4, wherein a selection signal output by each control unit of each layer of control circuit comprises a first signal and a second signal with opposite phases, each decoding unit comprises a pull-up component and a pull-down component connected in series, the decoding unit is connected with the variable positive voltage through the pull-up component and connected with the negative voltage through the pull-down component, and a word line control signal is extracted from a common terminal of the pull-up component and the pull-down component; the pull-up assembly of the decoding unit is controlled by a read-write signal and K paths of second signals respectively output by K different levels of control units corresponding to the decoding unit, and the pull-down assembly is controlled by an erase signal and K paths of first signals respectively output by K different levels of control units corresponding to the decoding unit; when the decoding unit receives a first signal of K-way active level and a second signal of K-way active level, it is determined that a word line strobe signal for instructing to strobe a connected word line is received.

9. The hierarchical wordline preprocessing circuit of claim 8, wherein, for each decode unit:

the pull-up assembly comprises four PMOS tubes, namely W _ P0, W _ P1, W _ P2 and W _ P3, the source of the W _ P3 is connected with the variable positive voltage, the drain of the W _ P3 is connected with the source of the W _ P2, the drain of the W _ P2 is connected with the source of the W _ P1, the drain of the W _ P1 is connected with the source of the W _ P0, the drain of the W _ P0 is used for connecting the pull-down assembly and leading out a word line control signal, the gate of the W _ P3 is controlled by a low-level effective read-write signal, the gate of the W _ P0 is controlled by a second signal output by a block control unit corresponding to the decoding unit, the gate of the W _ P1 is controlled by a second signal output by a group control unit corresponding to the decoding unit, the gate of the W _ P2 is controlled by a second three-way signal output by an address latch unit corresponding to the decoding unit, and the second signals are all low-level effective;

the pull-down component comprises four NMOS transistors, namely W _ N0, W _ N1, W _ N2 and W _ N3, the source of the W _ N0 is connected with the negative voltage, the drain of the W _ N0 is connected with the source of the W _ N1, the drain of the W _ N1 is connected with the source of the W _ N2, the drain of the W _ N2 is connected with the source of the W _ N3, the drain of the W _ N3 is used for connecting the pull-down component and leading out a word line control signal, the grid of the W _ N0 is controlled by an erasing signal which is effective at a high level, the grid of the W _ N3 is controlled by a first signal output by a block control unit corresponding to the decoding unit, the grid of the W _ N2 is controlled by a first signal output by a group control unit corresponding to the decoding unit, the grid of the W _ N1 is controlled by a first signal output by an address latch unit corresponding to the decoding unit, and the three first signals are all effective at a high level;

10. The hierarchical word line preprocessing circuit of claim 1, wherein the number of the control units in the next level corresponding to any two control units in the same level is the same or different.