CN113436661A - Data read-write control circuit for flash type programmable logic device - Google Patents
Data read-write control circuit for flash type programmable logic device Download PDFInfo
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- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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Abstract
The invention discloses a data read-write control circuit for a flash type programmable logic device, which relates to the field of programmable logic devices, when the data read-write control circuit writes data, a data selection module gates a configuration data channel to write the configuration data into a data latch module for latching, and then a data driving module outputs corresponding configuration data, when the data read-write control circuit writes back the data, the data selection module transmits the configuration data at the output end of the output control module to a data trimming module for data trimming to obtain the trimmed configuration data, the data selection module gates the write-back data channel to write the trimmed configuration data into the data latch module for latching, and then the data is output by the data driving module, the data read-write control circuit can realize stable data configuration and data write-back, and does not occupy an additional register unit, the method is flexible to realize and is suitable for large-scale programmable devices.
Description
Technical Field
The invention relates to the field of programmable logic devices, in particular to a data read-write control circuit for a flash type programmable logic device.
Background
The programmable logic device is designed based on a storage technology of repeated configuration, can complete the modification of a circuit by downloading and programming again, and has the advantages of short development period, low cost, small risk, convenience for the maintenance and the upgrade of an electronic system and the like, thereby becoming the mainstream of an integrated circuit chip.
The configuration memory architecture of the existing programmable logic device is shown in fig. 1, and mainly includes a read-write control circuit, a data shift register DSR, an address decoder ASR, and a memory array formed by a memory cell FlashCell. In the zero clearing stage, all the storage unit FlashCell outputs are 0, in the data configuration stage, the read-write control circuit configures bit streams to be loaded to the data shift register DSR and then to be configured to the storage unit FlashCell through the address decoder ASR, the existing read-write control circuit mainly realizes the basic configuration function of the storage function, the function is single, many existing complex integrated circuit chips need to load configuration information after the chips are reset, or appointed configuration information is reloaded in the working state, and the read-write control circuit in the existing configuration memory is difficult to meet the function requirement.
Disclosure of Invention
The present inventor provides a data read-write control circuit for flash type programmable logic device aiming at the above problems and technical requirements, and the technical scheme of the present invention is as follows:
a data read-write control circuit for flash type programmable logic device comprises a data selection module and a data latch module, the data selection module comprises a configuration data channel and a write-back data channel, the input end of the configuration data channel is used as the data end of the data read-write control circuit to acquire configuration data, the output end of the configuration data channel is connected with the output end of the write-back data channel and is connected with the input end of the data latch module, the output end of the data latch module is connected with the input end of the data drive module, the output end of the data drive module is used as the output end of the data read-write control circuit and is connected with the flash storage unit, the output end of the data drive module is also connected with the input end of the data trimming module through the read-back control module, and the output end of the data trimming module is connected with the input end of the write-back data channel;
when the data read-write control circuit writes data, the data selection module gates the configuration data channel to write the configuration data into the data latch module for latching, and then the data drive module outputs corresponding configuration data and writes the configuration data into the flash storage unit;
when the data read-write control circuit writes back data, the configuration data at the output end of the output control module are transmitted to the data trimming module through the read-back control module to be trimmed and trimmed to obtain trimmed configuration data, the data selection module gates the write-back data channel to write the trimmed configuration data into the data latch module to be latched, and the data are output through the data driving module and written into the flash storage unit.
The beneficial technical effects of the invention are as follows:
the data read-write control circuit can realize stable data configuration, data write-back and data verification, can realize the basic configuration of a conventional storage function, can also realize the functions of configuration data writing and configuration data verification according to the application requirements of a user, does not occupy an additional register unit, is flexible to realize, and is suitable for large-scale programmable devices.
Drawings
Fig. 1 is a configuration memory architecture diagram of a conventional programmable logic device.
Fig. 2 is a circuit diagram of one embodiment of a data read-write control circuit disclosed in the present application.
Fig. 3 is a circuit diagram of a data verification module included in another embodiment of the data read/write control circuit disclosed in the present application.
Fig. 4 is a schematic diagram of a partial signal waveform when the data read/write control circuit disclosed in the present application writes data.
Fig. 5 is a schematic diagram of partial signal waveforms when the data read-write control circuit disclosed in the present application performs data write-back and read-back verification.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
Referring to fig. 2, the data read-write control circuit includes a data selection module, a data latch module, a data driving module, a read-back control module, and a data trimming module. The data selection module comprises a configuration data channel and a write-back data channel, and the input end of the configuration data channel is used as the data end D of the data read-write control circuit to acquire configuration data. The output end of the configuration data channel is connected with the output end of the write-back data channel and is connected with the input end of the data latch module, and the data sel _ d acquired by the input end of the data latch module is the selected data. The output end of the data latch module is connected with the input end of the data drive module, and the output end of the data drive module is used as the output end BL of the data read-write control circuit and is connected with a flash memory unit (flash cell). The output end of the data driving module is also connected with the input end of the data trimming module through the read-back control module, and the output end of the data trimming module is connected with the input end of the write-back data channel to provide trimmed configuration data read _ data. In one embodiment, as shown in fig. 2, the read-back control module is a ninth NMOS transistor N9 controlled by a read-back enable signal read _ ctrl1, and the source of N9 is connected to the output terminal of the data driving module and the drain is connected to the input terminal of the data trimming module.
When the data read-write control circuit writes data, the data selection module gates the configuration data channel to write the configuration data input by the D end into the data latch module for latching, and then the data drive module outputs the configuration data at the BL end and writes the configuration data into the flash storage unit.
When the data read-write control circuit writes back data, the configuration data at the output end of the output control module are transmitted to the data trimming module through the read-back control module to be trimmed and trimmed to obtain trimmed configuration data read _ data, the data selection module gates the write-back data channel to write the trimmed configuration data read _ data into the data latch module to be latched, and the trimmed configuration data read _ data is output at the BL end through the data drive module and written into the flash storage unit. The data trimming module can adopt the existing data trimming circuit to realize the function of data trimming, and the circuit structure of the data trimming module is not limited in the application.
Therefore, based on the structure disclosed by the application, the data read-write control circuit can not only realize a stable data configuration function, but also realize a data write-back function, and meets the use requirement. It should be noted that, the configuration data input at the D terminal is processed by level conversion and the like in the process of reaching the BL terminal for output, so strictly speaking, the configuration data output at the BL terminal and the configuration data input at the D terminal are not completely the same data, but the present application focuses on selectively outputting two different contents of the original configuration data and the modified configuration data, and therefore the two different contents are collectively referred to as configuration data.
In one embodiment, as shown in fig. 2, the configuration data channel in the data selection module includes a zeroth NMOS transistor N0, a first NMOS transistor N1, and a second NMOS transistor N2. The drain of the zeroth NMOS transistor N0 is used as the data terminal D of the data read-write control circuit, the source is connected to the drain of the first NMOS transistor N1, the source of the first NMOS transistor N1 is connected to the drain of the second NMOS transistor N2, and the source of the second NMOS transistor N2 is used as the output terminal for configuring the data channel. The gate of the zeroth NMOS transistor N0 is controlled by the second control signal row2, the gate of the first NMOS transistor N1 is controlled by the first control signal row1, and the gate of the second NMOS transistor N2 is controlled by the shift enable signal shift _ en. When the first control signal row1, the second control signal row2 and the shift enable signal shift _ en are all at high level, the data selection module gates the configuration data channel.
The writeback data path in the data selection module includes a third NMOS transistor N3 and a fourth NMOS transistor N4. The drain of the third NMOS transistor N3 is used as the input end of the writeback data path, the source is connected to the drain of the fourth NMOS transistor N4, and the source of the fourth NMOS transistor N4 is used as the output end of the writeback data path. The gate of the third NMOS transistor N3 is controlled by the write-back control signal read _ ctrl0, and the gate of the fourth NMOS transistor N4 is controlled by the write-back shift enable signal read _ shift _ en. When both the write-back control signal read _ ctrl0 and the write-back shift enable signal read _ shift _ en are high, the data selection block gates the write-back data path.
The data selection module further comprises a fourteenth NMOS transistor N14 connected with the output ends of the configuration data channel and the write-back data channel through a drain, wherein a source of the fourteenth NMOS transistor N14 is grounded, and a gate of the fourteenth NMOS transistor is controlled by an initial value enable signal shiftn _ en. N14 is mainly used to provide an initial value for the data latch module, and when data writing and data write-back are performed, the initial value enable signal shiftn _ en is low to turn off N14.
In another embodiment, as shown in fig. 2, in the data driving module, a source of the fifth PMOS transistor P5 is connected to the operating power VDD, a drain of the fifth PMOS transistor P6 is connected to a source of the sixth PMOS transistor P6, a drain of the sixth PMOS transistor P6 is connected to a drain of the eighth NMOS transistor N8, a source of the eighth NMOS transistor N8 is connected to a drain of the seventh NMOS transistor N7, and a source of the seventh NMOS transistor N7 is grounded. The grid electrode of the fifth PMOS pipe P5 is connected with the grid electrode of the eighth NMOS pipe N8 and is used as the input end of the data driving module to be connected with the data latch module. The gate of the seventh NMOS transistor N7 is controlled by the first driving enable signal program _ en, the gate of the sixth PMOS transistor P6 is controlled by the second driving enable signal program _ en, and the common terminal of the sixth PMOS transistor P6 and the eighth NMOS transistor N8 serves as the output terminal of the data driving module and is connected to the BL terminal. When the first driving enable signal program _ en is at a high level and the second driving enable signal program _ en is at a low level, the data driving module outputs the data latched by the data latch module.
In another embodiment, the data read-write control circuit may further implement a read-back verification function when writing back, and the data read-write control circuit further includes a data verification module, where the data verification module is connected to the data latch module to obtain the configuration data and compare the configuration data after trimming and output a verification result.
In order to realize the read-back verification function, the data latch module comprises a first-stage latch and a second-stage latch which are connected, the first-stage latch is connected with the data selection module, the second-stage latch is connected with the data driving module, and the two-stage latches are both connected with the data verification module. When the data read-write control circuit writes data, the data selection module gates the configuration data channel to latch the configuration data into the first-stage latch of the data latch module, then latches the configuration data in the first-stage latch into the second-stage latch, and the data drive module outputs the configuration data latched by the second-stage latch. When the data read-write control circuit writes back data, the second-stage latch of the data latch module keeps latching the configuration data, and the data selection module gates the write-back data channel to latch the modified configuration data read _ data into the first-stage latch of the data latch module. And transmitting the modified configuration data read _ data in the first-stage latch and the configuration data in the second-stage latch to a data verification module for comparison.
As shown in fig. 2, in one embodiment, the data latch module having a two-stage latch structure includes a first-stage latch formed of a second inverter T2 and a first inverter T1 connected in an opposite direction, and a second-stage latch formed of a fourth inverter T4 and a third inverter T3 connected in an opposite direction, wherein:
the output terminal of the second inverter T2 is connected to the input terminal of the first inverter T1 and to the drain of the fifth NMOS transistor N5, and the gate of the fifth NMOS transistor N5 is controlled by the zero control signal row 0. The source of the fifth NMOS transistor N5 is connected to the drain of the fifteenth NMOS transistor N15, the source of the fifteenth NMOS transistor N15 is grounded, and the gate of the fifteenth NMOS transistor N15 is used as the input terminal of the data latch module to obtain the data sel _ d selected by the data selection module. The input end of the second inverter T2 is connected to the output end of the first inverter T1 and to the drain of the sixth NMOS transistor N6, the source of the sixth NMOS transistor N6 is grounded, and the gate of the sixth NMOS transistor N6 is controlled by the first reset signal rst.
The output end of the fourth inverter T4 is connected to the input end of the third inverter T3 and is connected to the drain of the zeroth PMOS transistor P0, the source of the zeroth PMOS transistor P0 is connected to the working power VDD, and the gate is controlled by the second reset signal nrst. An input terminal of the fourth inverter T4 is connected to an output terminal of the third inverter T3 and to the data driving block as an output terminal of the data latch block.
The output end of the fourth inverter T4 is further connected with the drain electrode of a third PMOS tube P3, the source electrode of a third PMOS tube P3 is connected with the drain electrode of the first PMOS tube P1, the gate electrode of the third PMOS tube P3 is connected with the output end of the second inverter T2, the source electrode of a third PMOS tube P3 is connected with the working power supply VDD, and the gate electrode of the P1 is controlled by the write-back latch signal read _ nrst. The input end of the fourth inverter T4 is connected with the drain electrode of the fourth PMOS tube P4, the source electrode of the fourth PMOS tube P4 is connected with the drain electrode of the second PMOS tube P2, the grid electrode of the fourth PMOS tube P4 is connected with the output end of the first inverter T1, the source electrode of the second PMOS tube P2 is connected with the working power supply VDD, and the grid electrode of the second PMOS tube P2 is controlled by the write latch signal write _ nrst.
In another embodiment, as shown in fig. 3, in the data verification module, the gates of the seventh PMOS transistor P7 and the tenth NMOS transistor N10 are connected and controlled by the configuration data latched by the second stage latch, and in conjunction with the circuit of fig. 2, i.e., the gates of P7 and N10 are connected to the output terminal q1 of T4. The source of the seventh PMOS transistor P7 is connected to the working power VDD, the source of the tenth NMOS transistor N10 is grounded, the drains of the seventh PMOS transistor P7 and the tenth NMOS transistor N10 are connected to the gates of the ninth PMOS transistor P9 and the twelfth NMOS transistor N12, the drains of the ninth PMOS transistor P9 and the twelfth NMOS transistor N12 are connected to the gate of the thirteenth NMOS transistor N13, the source of the ninth PMOS transistor P9 is connected to the gate of the eleventh NMOS transistor N11 and controlled by the modified configuration data of the first-stage latch, in combination with the circuit of fig. 2, that is, the source of P9 and the gate of N11 are connected to the output q of T1. The source of the eleventh NMOS transistor N11 is connected to the source of the eighth PMOS transistor P8 and to the drain of the seventh PMOS transistor P7, the drain of the eleventh NMOS transistor N11 is connected to the drain of the eighth PMOS transistor P8 and to the gate of the thirteenth NMOS transistor N13, and the gate of the eighth PMOS transistor P8 and the source of the twelfth NMOS transistor N12 are controlled by the same signal and opposite to the signal of the modified configuration data latched by the first-stage latch, i.e., the source of N12 and the gate of P8 are connected to the input qn of T1, in conjunction with the circuit of fig. 2. The thirteenth NMOS transistor N13 has a grounded source and a drain for outputting a verification result verify _ d, and when the modified configuration data latched by the first-stage latch is the same as the configuration data latched by the second-stage latch, i.e., q is equal to q1, the verification result output by the data verification module is high and indicates that verification passes. Otherwise, the verification result output by the data verification module is low level and indicates that the verification is not passed.
Based on the circuit diagrams shown in fig. 2 and 3, the waveform diagrams of the main signals of the data read-write control circuit when data is written are shown in fig. 4, and the waveform diagrams of the main signals when data is written back and verified are shown in fig. 5, and the working process is as follows:
when data writing is performed, the data read-write control circuit controls the first reset signal rst to be at a high level to reset the first-stage latch, so that the output end q of the first inverter T1 is at a low level and the input end qn is at a high level. The control row2, row1 and shift _ en are high level, the shift _ en is low level, the data selection module gates the configuration data channel to write the configuration data into the data latch module, and the configuration data is latched at the output terminal q of the first inverter T1 when the zeroth control signal row0 is controlled to be high level. The second reset signal nrst is controlled to be high to reset the second stage latch, the output terminal q1 of the fourth inverter T4 is controlled to be high, the input terminal qn1 is controlled to be low, and when the write latch signal write _ nrst is controlled to be low, the configuration data of the output terminal q of the first inverter T1 is latched to the output terminal q1 of the fourth inverter T4. Then, the first driving enable signal program _ en is controlled to be at a high level, the second driving enable signal program _ en is controlled to be at a low level, and data at the output terminal q1 of the fourth inverter T4 is output through the data driving module.
When the data read-write control circuit performs data write-back and verification, the data read-write control circuit keeps the output end q1 of the fourth inverter T4 latched with configuration data, controls the first reset signal rst to be at a high level to reset the first-stage latch, and enables the output end q of the first inverter T1 to be at a low level and the input end qn to be at a high level. And controlling the read _ ctrl1 to be at a high level, and reading the configuration data at the BL end back to the data trimming module to perform data trimming and then outputting the trimmed configuration data read _ data. And controlling read _ ctrl0 and read _ shift _ en to be at a high level and shift _ en to be at a low level, and enabling the write-back data channel to be gated by the data selection module to write the trimmed configuration data read _ data into the data latch module. When the zeroth control signal row0 is controlled to be high, the trimmed configuration data read _ data is latched at the output terminal q of the first inverter T1. The output q of the first inverter T1 and the output q1 of the fourth inverter T4 are transmitted to the data check module for comparison. After the verification is passed, the write-back latch signal read _ nrst is controlled to be at a low level, and the modified configuration data read _ data at the output terminal q of the first inverter T1 is latched to the output terminal q1 of the fourth inverter T4. And controlling the first drive enable signal program _ en to be at a high level and the second drive enable signal program _ en to be at a low level, and outputting the modified configuration data read _ data of the output end q1 of the fourth inverter T4 through the data driving module.
In practical application, the data read-write control circuit comprises a plurality of parallel basic units, each basic unit comprises a data selection module, a data latch module, a data driving module, a read-back control module and a data trimming module respectively and forms the circuit structure, and the plurality of basic units form the control circuit of the flash memory cell array in parallel, so that the control circuit is suitable for large-scale programmable logic devices.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.
Claims (10)
1. A data read-write control circuit for a flash type programmable logic device is characterized by comprising a data selection module, a data latch module, a data driving module, a read-back control module and a data trimming module, wherein the data selection module comprises a configuration data channel and a write-back data channel, the input end of the configuration data channel is used as the data end of the data read-write control circuit to acquire configuration data, the output end of the configuration data channel is connected with the output end of the write-back data channel and is connected with the input end of the data latch module, the output end of the data latch module is connected with the input end of the data driving module, the output end of the data driving module is used as the output end of the data read-write control circuit and is connected with a flash storage unit, and the output end of the data driving module is also connected with the input end of the data trimming module through the read-back control module, the output end of the data trimming module is connected with the input end of the write-back data channel;
when the data read-write control circuit writes data, the data selection module gates the configuration data channel to write the configuration data into the data latch module for latching, and then the data drive module outputs corresponding configuration data and writes the configuration data into the flash storage unit;
when the data read-write control circuit writes back data, the configuration data at the output end of the output control module are transmitted to the data trimming module through the read-back control module to perform data trimming to obtain trimmed configuration data, the data selection module gates the write-back data channel to write the trimmed configuration data into the data latch module to latch, and the data are output through the data driving module and written into the flash storage unit.
2. The data read-write control circuit of claim 1, further comprising a data verification module, wherein the data verification module is connected to the data latch module to obtain the configuration data and the modified configuration data for comparison and outputting a verification result.
3. The data read-write control circuit according to claim 2, wherein the data latch module comprises a first-stage latch and a second-stage latch which are connected, the first-stage latch is connected with the data selection module, the second-stage latch is connected with the data driving module, and both the two-stage latches are connected with the data verification module;
when the data read-write control circuit writes data, the data selection module gates the configuration data channel to latch configuration data into a first-stage latch of the data latch module, then latches the configuration data in the first-stage latch into a second-stage latch, and the data drive module outputs the configuration data latched by the second-stage latch;
when the data read-write control circuit writes back data, a second-stage latch of the data latch module keeps latching configuration data, and the data selection module gates the write-back data channel to latch the modified configuration data into a first-stage latch of the data latch module;
and transmitting the modified configuration data in the first-stage latch and the configuration data in the second-stage latch to the data verification module for comparison.
4. The data read-write control circuit of claim 3, wherein the data latch module comprises a first stage latch formed by a second inverter and a first inverter which are connected in an inverted manner, and a second stage latch formed by a fourth inverter and a third inverter which are connected in an inverted manner, wherein:
the output end of the second phase inverter is connected with the input end of the first phase inverter and is connected to the drain electrode of a fifth NMOS transistor, the grid electrode of the fifth NMOS transistor is controlled by a zero control signal, the source electrode of the fifth NMOS transistor is connected with the drain electrode of a fifteenth NMOS transistor, the source electrode of the fifteenth NMOS transistor is grounded, and the grid electrode of the fifteenth NMOS transistor is used as the input end of the data latch module; the input end of the second phase inverter is connected with the output end of the first phase inverter and is connected to the drain electrode of a sixth NMOS tube, the source electrode of the sixth NMOS tube is grounded, and the grid electrode of the sixth NMOS tube is controlled by a first reset signal;
the output end of the fourth phase inverter is connected with the input end of the third phase inverter and is connected to the drain electrode of a zeroth PMOS tube, the source electrode of the zeroth PMOS tube is connected with a working power supply, the grid electrode of the zeroth PMOS tube is controlled by a second reset signal, and the input end of the fourth phase inverter is connected with the output end of the third phase inverter and serves as the output end of the data latch module;
the output end of the fourth phase inverter is further connected with the drain electrode of a third PMOS (P-channel metal oxide semiconductor) tube, the source electrode of the third PMOS tube is connected with the drain electrode of a first PMOS tube, the grid electrode of the third PMOS tube is connected with the output end of the second phase inverter, the source electrode of the third PMOS tube is connected with the working power supply, the grid electrode of the third PMOS tube is controlled by a write-back latch signal, the input end of the fourth phase inverter is connected with the drain electrode of the fourth PMOS tube, the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the fourth PMOS tube is connected with the output end of the first phase inverter, the source electrode of the second PMOS tube is connected with the working power supply, and the grid electrode of the second PMOS tube is controlled by a write-in latch signal.
5. The data read-write control circuit of claim 4,
when the data read-write control circuit writes data, the first-stage latch is reset by controlling the first reset signal to be at a high level, so that the output end of the first phase inverter is at a low level, the input end of the first phase inverter is at a high level, the data selection module gates the configuration data channel to write configuration data into the data latch module, and the configuration data is latched at the output end of the first phase inverter when the zeroth control signal is controlled to be at a high level; controlling the second reset signal to be at a high level to reset the second-stage latch, controlling the output end of the fourth inverter to be at a high level and the input end to be at a low level, and when controlling the write-in latch signal to be at the low level, latching the configuration data at the output end of the first inverter to the output end of the fourth inverter, and outputting the data at the output end of the fourth inverter through the data driving module;
when the data read-write control circuit performs data write-back and verification, the output end of the fourth inverter is kept locked with the configuration data, the first reset signal is controlled to be at a high level to reset the first-stage latch, so that the output end of the first inverter is at a low level and the input end of the first inverter is at a high level, the data selection module gates the write-back data channel to write the modified configuration data into the data latch module, and when the zeroth control signal is controlled to be at a high level, the modified configuration data is locked at the output end of the first inverter; the output end of the first phase inverter and the output end of the fourth phase inverter are transmitted to the data verification module for comparison, after verification is passed, the write-back latch signal is controlled to be at a low level, the configuration data after the output end of the first phase inverter is modified are latched to the output end of the fourth phase inverter, and the data at the output end of the fourth phase inverter is output through the data driving module.
6. The data read-write control circuit according to claim 3, wherein in the data verification module, gates of a seventh PMOS transistor and a tenth NMOS transistor are connected and controlled by the configuration data latched by the second-stage latch, a source of the seventh PMOS transistor is connected to a working power supply, a source of the tenth NMOS transistor is grounded, a drain of the seventh PMOS transistor and the tenth NMOS transistor is connected to gates of a ninth PMOS transistor and a twelfth NMOS transistor, drains of the ninth PMOS transistor and the twelfth NMOS transistor are connected to a gate of a thirteenth NMOS transistor, a source of the ninth PMOS transistor is connected to a gate of an eleventh NMOS transistor and controlled by the modified configuration data latched by the first-stage PMOS latch, a source of the eleventh NMOS transistor is connected to a source of an eighth transistor and to a drain of the seventh PMOS transistor, a drain of the eleventh NMOS transistor and a drain of the eighth PMOS transistor are connected to a gate of the thirteenth NMOS transistor, the grid electrode of the eighth PMOS tube and the source electrode of the twelfth NMOS tube are controlled by the same signal and are opposite to the signal of the modified configuration data latched by the first-stage latch;
and the source electrode of the thirteenth NMOS tube is grounded, the drain electrode of the thirteenth NMOS tube is used for outputting a verification result, when the modified configuration data latched by the first-stage latch is the same as the configuration data latched by the second-stage latch, the verification result output by the data verification module is high level and indicates that verification is passed, otherwise, the verification result output by the data verification module is low level and indicates that verification is not passed.
7. The data read-write control circuit according to any one of claims 1 to 6,
the configuration data channel in the data selection module comprises a zero NMOS tube, a first NMOS tube and a second NMOS tube, wherein the drain electrode of the zero NMOS tube is used as the data end of the data read-write control circuit, the source electrode of the zero NMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, and the source electrode of the second NMOS tube is used as the output end of the configuration data channel; the grid electrode of the zeroth NMOS tube is controlled by a second control signal, the grid electrode of the first NMOS tube is controlled by a first control signal, and the grid electrode of the second NMOS tube is controlled by a shift enable signal;
the data selection module comprises a data selection module, a data write-back channel and a data selection module, wherein the data write-back channel in the data selection module comprises a third NMOS tube and a fourth NMOS tube, the drain electrode of the third NMOS tube is used as the input end of the data write-back channel, the source electrode of the third NMOS tube is connected with the drain electrode of the fourth NMOS tube, and the source electrode of the fourth NMOS tube is used as the output end of the data write-back channel; the grid electrode of the third NMOS tube is controlled by a write-back control signal, and the grid electrode of the fourth NMOS tube is controlled by a write-back shift enabling signal;
the data selection module further comprises a fourteenth NMOS tube connected with the configuration data channel and the output end of the write-back data channel through a drain, wherein a source of the fourteenth NMOS tube is grounded, a grid of the fourteenth NMOS tube is controlled by an initial value enabling signal, and the initial value enabling signal is at a low level when data writing and data write-back are carried out;
when the first control signal, the second control signal and the shift enable signal are all high levels, the data selection module gates the configuration data channel; and when the write-back control signal and the write-back shift enable signal are both high level, the data selection module gates the write-back data channel.
8. The data read-write control circuit according to any one of claims 1 to 6, wherein in the data driving module, a source of a fifth PMOS transistor is connected to a working power supply, a drain of the fifth PMOS transistor is connected to a source of a sixth PMOS transistor, a drain of the sixth PMOS transistor is connected to a drain of an eighth NMOS transistor, a source of the eighth NMOS transistor is connected to a drain of a seventh NMOS transistor, a source of the seventh NMOS transistor is grounded, a gate of the fifth PMOS transistor is connected to a gate of the eighth NMOS transistor and serves as an input terminal of the data driving module, a gate of the seventh NMOS transistor is controlled by a first driving enable signal, a gate of the sixth PMOS transistor is controlled by a second driving enable signal, and a common terminal of the sixth PMOS transistor and the eighth NMOS transistor serves as an output terminal of the data driving module;
and when the first drive enabling signal is at a high level and the second drive enabling signal is at a low level, the data drive module outputs the data latched by the data latch module.
9. The data read-write control circuit according to any one of claims 1 to 6, wherein the data read-write control circuit comprises a plurality of parallel basic units, and each basic unit comprises the data selection module, the data latch module, the data driving module, the read-back control module and the data trimming module.
10. The data read-write control circuit according to any one of claims 1 to 6, wherein the read-back control module is a ninth NMOS transistor controlled by a read-back enable signal, a source of the ninth NMOS transistor is connected to the output terminal of the data driving module, and a drain of the ninth NMOS transistor is connected to the input terminal of the data trimming module.
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| CN101656097A (en) * | 2009-08-28 | 2010-02-24 | 苏州东微半导体有限公司 | Sensitive amplifier circuit applied to semiconductor memory and work method thereof |
| CN111489774A (en) * | 2020-04-09 | 2020-08-04 | 无锡中微亿芯有限公司 | Improved data relay structure for configuration memory of programmable logic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656097A (en) * | 2009-08-28 | 2010-02-24 | 苏州东微半导体有限公司 | Sensitive amplifier circuit applied to semiconductor memory and work method thereof |
| CN111489774A (en) * | 2020-04-09 | 2020-08-04 | 无锡中微亿芯有限公司 | Improved data relay structure for configuration memory of programmable logic device |
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