TW419891B - Asynchronous sensing differential logic (ASDL) circuit - Google Patents

Abstract

An asynchronous sensing differential logic circuit using a charge-recycling technique includes a control block carrying out a logical operation on a request signal from a preceding stage and a request signal for a succeeding stage, and outputting a first or second input enable signal and a first or second clock signal, a functional block carrying out an operation on an input data according to the first or second input enable signals and the first or second clock signals from the control block, and outputting a first or second output enable signal and an output data, and a latch block triggered by an acknowledge signal from the succeeding stage, and outputting a request signal for the succeeding stage and a final output data by carrying out an operation on the first or second output enable signals and the output data from the functional block.

Description

Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 -419.89j__B7 _____ V. Description of the Invention (1-) Background of the Invention 1. Field of the Invention The present invention relates to a non-synchronous circuit, and in particular relates to a non-synchronous sense using _ charge cycle technology. Measuring differential logic (A s DL) circuit. 2. Description of background technology Generally speaking, when designing semiconductor circuits, the advantage of non-synchronous design technology is that because the universal clock signal is not used, clock skew will not occur and the overhead of clock signal distribution will not be incurred. Signal transitions are generated only when there is an event, which can reduce power consumption, and because processing time is not determined by the worst-case delay, but by average delay, waiting time can be reduced. In order to use asynchronous signals, the regional function blocks need to communicate smoothly. The two-phase signal exchange scheme or the four-phase signal exchange scheme is mainly used here. In particular, the four-phase signal exchange scheme is easy to implement with a circuit and is therefore generally used. Figure 1 is a schematic block diagram illustrating a conventional asynchronous pipeline configuration, including a function block 102 for performing various logical operations, a completion of the operation of the detector 103 communication function block 102, and a control block 101 for controlling the function block 102. Handshake and a latch block 104 output data according to the operation of the function block 102. A differential series voltage switch (DCVS) logic or a charge cycle differential logic (CRDL) belongs to the differential logic series which is easy to detect from the previous stage and is mainly used as a function block 1. The circuit diagrams are shown in Figures 2 and 3, respectively. Figure 2 is a schematic circuit diagram illustrating a differential series voltage switch (DCVS) logic circuit. As shown in the figure, the one-clock signal CK is applied to two PMOS electronic papers, and the K-degree is applicable to the China National Standard (CNS) A4 specification (210 X 297 mm): · ----------- ------- Order --------- line (please ^ * read back the phonetic of £-'before filling out this page) Printed on 419891 B by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs; 5. Description of the invention (2) The source of the gate of the crystal PM1 'PM2 is the source voltage Vdd. The clock signal CK is applied to the gate of the NMOS transistor NM1, and the source of the NM1 is grounded. The drains of the PMOS transistors PM1 and PM2 are connected to the drain of the NMOS transistor NM1 in common through a series of logic 102-1. The series logic is turned on / off according to the input data. The PMOS transistors PM1, PM2 and the output drain terminals of the serial logic 102-1 are respectively connected to the input terminals of the two inverters XI and X2. The inverters XI and X2 output individual output signals OUT '~~ OUT ο Figure 3 is a schematic circuit diagram illustrating a charge loop differential logic (CRDL) circuit. As shown in the figure, the enable signal Ei is applied to the gate of the NMOS transistor NM15, and the source of the NM15 is grounded. The clock signal CK is connected to the gate of the PMOS transistor PM14, and the source of the PM14 is applied with a power supply voltage Vdd. The gate is connected with a PMOS transistor PM13 with a clock signal CK, which is connected between the gates of the PMOS transistors PM11 and PM12. The individual source of PM11 and PM12 is applied with a power supply voltage Vdd. The gates of the PMOS transistors PM11 and PM13 are respectively connected to the gates of the NMOS transistor NM11 'NM12, the drains of the NMOS transistors NMΠ and NM14, and the output terminals connected to the conducting crystal logic circuit 10-2_2. The common node outputs signals OUT, one. The sources of the NMOS transistors NM11 and NM13 are commonly connected to the drain of the NMOS transistor NM15. The sources of the NMOS transistors NM12 and NM14 are connected to the drain of the PMOS transistor PM14 in common, and the input terminal of the inverter X3 outputs the enable signal Eo of the next stage. The conducting crystal logic 102.2 can ground the output signals OUT, —out according to the data input signal DATAIN. This paper size applies to China National Standard (CNS) A4 (_2Ι0 X 297 mm) --.------- i --- ί '^ -------- ^ ----- ---- (please ^ read me back ^-the meaning of the river 箅 箅 fill in this page) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 419891 a? _________B7__ V. Description of the invention (3) It's Miller C element It is often used as a signal exchange circuit for asynchronous systems because of its delay insensitivity. When the two input values are equal, the output value is the same as the input value. If the two input values are different, the previous value is retained. The control block 101 configured in Figure 1 is mainly implemented by using Miller C elements for signal exchange control. In addition, the 'latch block 104 may be a conventional flow-latch type or Miller c element. However, the flow-latch does not have a delay insensitivity 'and therefore most of the Miller c elements are used. As shown in the example in FIG. 4, in the latch block 104, the confirmation signal ACK from the next stage is commonly applied to the gate of the PMOS transistor PM22, the source of the PM22 is applied with the power supply voltage vdd, and the NMOS transistor is commonly applied. The source of the NM22 gate body is grounded, and the input signal (Din, mainly OUT or Ot / 71) is commonly applied to the gate body of the PMOS transistor PM21. The source of the PM21 is connected to the drain of the PMOS transistor PM22, and In addition to the gate of the NMOS transistor NM21, the source of the NM21 is connected to the drain of the NMOS transistor NM22. The latch block 104 includes two circuits attached. The latch 104-1 is composed of two inverters X4 and X5 connected in anti-parallel and parallel. The latch is composed of a PMOS transistor PM21 and an NMOS transistor.

The signal output by the node of NM21, and the latched signal DATAOUT.

Generally speaking, the completion detector 103 configured in FIG. 1 includes a NAND gate or a NOR gate, and performs logic operations on the two output signals OUT from the function block 102 and generates operation completion signals. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I —r ^ ίι--in I n-I.-Γ [* n II ϋ 0 «an I nn η I line 丨-丨(Please read the back; please fill out this page)

419891 Description of the invention (4) Now, the conventional asynchronous system operation will be described. (Please read the notes on the back and fill in this page again.) When the confirmation signal ACOUT from the next stage is low, if the request signal REQIN from the previous stage is low, the clock signal CK output by the control block 101 Becomes high, the function block 102 enters the evaluation period, and evaluates the output values OUT and -Oi / r 'and the completion detector 103 performs logic operations on the output values ουτ, 0 [/ Γ to generate a high output value β. The output value of the detector 103 is high, and the turn-out value is transmitted as the request signal REQOUT of the next stage and the acknowledgement signal ACKIN of the previous stage. Then when the request signal REQIN from the previous stage is high, the output signal from the control block 101 maintains its previous output state. When the confirmation signal ACOUT from the next stage is high, the clock signal CK output by the control block becomes low, so the function block 102 enters the precharge period. In this way, the output signal from the completion detector 103 is generated low, so that the acknowledgement signal ACKIN transmitted to the previous stage and the request signal REQOUT transmitted to the next stage become low. In other words, the logical operation of the function block 102 is performed by repeating the foregoing process. The composition of the π function block 102 produced by the Intellectual Property Bureau of the Intellectual Property Bureau of the Ministry of Economic Affairs can be described as shown in Figure 2 or 3, and described as follows. If implemented as shown in Figure 2, when the clock signal CK is low, the PMOS circuit The crystals PM1 and PM2 are turned on, so that the internal output terminals, that is, the input terminals of the inverters XI, X2, are precharged to a high level. The inverters XI and X2 that received the high signal from the internal output terminal discharge the external output respectively. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). Clothing 419891 A7 _____B7_ V. Description of the invention (5) Child OUT, ~ Ί9ί / Γ to a low level. Subsequently, when the clock signal changes from low to high, the NMOS transistor NM1 is turned on, so that the logic 102-1 is connected in series to the operating state. At this time, the serial connection logic 102-1 discharges one of the internal output terminals, that is, one of the input terminals of the inverters XI, X2, to a low level according to the input value DATAIN. Here, it is assumed that, for example, the input terminal of the inverter XI is discharged. As a result, the input terminal of inverter XI is discharged to a low level, the output terminal OUT of the inverter becomes high, and the input terminal of the inverter is charged to a high level. \ Keep low. Then, when the clock signal CK changes from high to low, the data operation is performed in a precharged state by repeating the foregoing process. In addition, the operation of the CRDL circuit in Figure 3 is similar to the circuit in Figure 2, but the pre-charge voltage of the output terminals OUT and -0ϋΓ is r 1 / 2vda "and its swing width is" l / 2Vda ". In other words, the CRDL circuit operation in Figure 3 is classified into a precharge period and an evaluation period. First, "in the precharge period", when the clock signal CK is low, the PMOS transistor PM13 is turned on, so that the output terminal out '-this connection. As a result, the voltage levels of the output terminals OUT and -ϋί / Γ become completely the same according to the charge division effect. At this time, the levels of the output terminals are complementary. In other words, one is often "Vdd" and the other is often "rVss". Therefore, when the output terminals are connected, the voltage level is determined by "Vdd" and "Vss" $. In general, when the parasitic capacitances of the output terminals OUT and —ϋί / Γ are similar, the value is determined as the electrical energy applicable to the Zhongguanjia Standard (CNS) A4 specification ⑵Q χ 297 Chu)-ij — 1'—11 --- Γ Install.I ------ Order -111-111., Line 丨 i-. ≪ Please read the Italian matter on the back before filling this page > A7 A7 419891 B7 _ 5. Description of the invention (6) Half of the source voltage Vdd. If the equalized voltage value is lower than the required value due to the parasitic capacitance mismatch, the cross-coupled PMOS transistor is turned on to PM11 and PM12, and the charge is additionally supplied to the precharge node, so that the voltage is approximately equal to half the power supply voltage Vdd. Subsequently, the PMOS transistors PM11 and PM12 with high threshold voltages have been turned on, so that even if the required voltage value is obtained, the output terminals OUT, Οί / Τ will not be pulled high. The clock signal CK is low, so that the PMOS transistor PM14 is turned on, and the input terminal of the inverter X3 becomes high. In this way, the inverter X3 outputs a low-level enable signal E. Then during the evaluation period, when the clock signal CK goes high, the PMOS transistor PM13 is turned on, so that the output terminals OUT,-are separated from each other. At this time, the conductive crystal logic 102-2 receives the data and grounds one of the output terminals OUT and-. Here, for example, it is estimated that the output terminal ot / r is grounded. As a result, the output terminal OUT is maintained at a high level, and the level of the output terminal ^ becomes low. In addition, the clock signal CK is at a high level, so that the PMOS transistor PM14 is turned off. However, the output terminal OUT is at a high level, so the NMOS transistor NM14 is turned on. As a result, the level of the input terminal of the inverter X3 becomes low. Therefore, the enable signal Eo changes from low to high. In other words, the larger the voltage difference between the output terminals OUT, the faster the NMOS transistor NM14 is turned on. Therefore, the inverter X3 paper size applies to the Chinese National Standard (CNS) A4 specification (2〗 0 X 297 male f) -----------.--! -Order --------- line (please read the back of the page first, and pay attention to this page before filling in this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 9 Printed by the Employees’ Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 419891 V. Description of the invention (7) The input terminal level becomes low. Here, the low-signal inverter X3 outputs the enable signal Eo at a high level for the next stage to actuate the sense amplifier. Subsequently, when the clock signal CK changes from high to low, the data operation is performed in the precharge state by repeating the foregoing process. When the output of the functional block 1 02 as illustrated in Figure 2 or 3 is output, the data OUT, -Ot / Γ are transmitted to the next stage through the latch block 104, and the flash block 104 includes two circuit systems. It is composed of complex transistors pM21, PM22, NM21, NM22 and latch 104-1. As shown in Figure 4, e will now take the output data signal 0υτ from function block 102 as an example to illustrate the operation. When the confirmation signal AC0UT from the next stage is at the low level, if the output data signal from the function block 102 is at the low level, only the PM0S transistors PM2 and PM22 are turned on, and the power supply voltage It is applied to the latch 104-1, so that the latch outputs the low-order data DATAOUT. When the confirmation signal AC0UT is high-order, only the NM0s transistor NM21 ′ NM22 is turned on, so that the input terminal of the latch 104-1 is grounded. As a result, the latch 104-1 outputs the high-level data dataOUT. When the confirmation signal ACOUT is at the low level, if the output data signal OUT from the function block 102 is at the high level, or when the confirmation signal AC0UT is at the high level, if the output data signal from the function block 102 OUT is at a low level, the latch 104 · is maintained before the output level until the two output signal levels become the same. The conventional technology can theoretically guarantee low power consumption and high-speed operation. Actually, its disadvantage is that the comparison system cannot significantly improve performance, because the DCVS logic signal exchange scheme used as a functional block and the paper size are applicable to Zhongguanxian (CNS) A. (Please read the notes on the back before filling this page);. And * φ °-printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Line Economy 419991 A7 ______B7 _ V. Description of the invention (8) It requires additional overhead of the control circuit. In addition, when CRDL is used, although the power consumption is reduced, there is another disadvantage: a high voltage is required, and the threshold voltage Vt of the AC coupled transistor is increased. SUMMARY OF THE INVENTION Therefore, a second object of the present invention is to provide an asynchronous sensing differential logic (ASDL) circuit, which can reduce power consumption by applying a charge cycle to an asynchronous system. In order to achieve the foregoing object of the present invention, an asynchronous system includes a control block, a function block, a completion detector, and a latch block. The function block is provided with a completion detection function. Detect the needs of appointments and become a low-scoring operation. In other words, a non-synchronous pipeline configuration according to the present invention includes: a control block performs logical operations on a request signal from a previous stage and a request signal from a next stage, and outputs a first or second input enable signal and a first or second Two clock signals; a function block that operates on the input data according to the first or second input enable signal and the first or second clock signal from the control block, and outputs the first or second output enable signal And output data; and a latch block which is triggered by a confirmation signal from the previous stage, and operates the first or second output enable signal and output data from the function block 'and rotates to the next stage request signal And final output data. Brief description of the drawings The present invention will be better understood by referring to the drawings. The drawings are for illustration purposes only. This is not a limitation on the present invention. In the drawings: The K degree of this paper is applicable to the Chinese national standard (CN: S) A4 specifications (.210 X 297 g) 11 --T-^-IIIII Γ Chu: ----- i —11 * — — — '' line * '(Please read the note on the back first Matters are refilled on this page) 413991 A7 __B7___ Five 'invention description (9) Figure 1 is a schematic block diagram illustrating the conventional asynchronous pipeline configuration; Figure 2 is a schematic circuit diagram illustrating the first functional block in the configuration of Figure 1— Specific example; Figure 3 is a schematic circuit diagram illustrating the second specific example of the functional block in the configuration of Figure 1; Figure 4 is a schematic circuit diagram illustrating the latch block of the configuration of Figure 1; Figure 5 is a schematic block diagram illustrating this Non-synchronous pipeline configuration of the invention; FIG. 6 is a schematic circuit diagram illustrating a functional block configured according to the first specific example of the present invention in FIG. 5; FIG. 7 is a schematic circuit diagram illustrating a second specific example according to the present invention in FIG. Configuration functional block; Figure 8 is a schematic circuit diagram illustrating Figure 5 according to the present invention Configuration of the latch block; Figure 9 is a schematic circuit diagram illustrating a functional block configured in Figure 5 according to a third specific example of the present invention; Circle 10 is a schematic block diagram illustrating the three bits of a functional block circuit in Figure 9 Chain connection configuration; FIG. 11 is a schematic circuit diagram illustrating a functional block configured in FIG. 5 according to a fourth specific example of the present invention; FIG. 12 is a schematic block diagram illustrating five bits of a functional block circuit in FIG. Chain connection configuration; Figure 13 is a schematic circuit diagram illustrating the functional block configured in Figure 5 according to the fifth specific example of the present invention; Figures 14A to 14D are operation of asynchronous pipelines according to the present invention. The paper dimensions are applicable to Chinese national standards (CNS) A4 specifications (¾ 297 public love) ----- I i II l · II ['11--1 i Order " ----- III (Fill in this page again) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 419391 B7 V. Individual timing diagrams of the invention description (ίο); Detailed description of the invention will now be described with reference to the attached circle for non-synchronous sensing according to the invention Differential logic (ASDL) circuit is fine Figure 5 is a schematic block diagram illustrating the asynchronous pipeline configuration according to the present invention. As shown in the figure, the asynchronous pipeline configuration includes a function block 202 that executes a logical operation to be performed and has a completion detection function therein, and Generate a completion signal for each logical operation; the control block 20I generates a signal cKi / CKib or Ei / Eib 俾 to facilitate the handshake of the control function block 202 when performing operations according to the request signals rEqIN, rEq〇uT; and the latch block 203 stores The data sent by the function block 202 outputs the stored data and simultaneously outputs the request signal REQOUT of the next stage. Here, the control block 201 is composed of a Miller C element. Specific examples of the functional block 202 according to the present invention are shown in Figs. 6, 7, 9, and 13 respectively. Fig. 6 is a schematic circuit diagram illustrating a non-synchronous charge cycle differential logic circuit according to a first specific example of the present invention. As shown in the figure, the asynchronous charge cycle differential logic circuit includes: an inverter X53 inverts the clock signal CKi and outputs an inverted clock signal CKb; an inverter X54 inverts the inverted phase Pulse signal CKib and output non-inverted clock signal CK; a pair of inverters X51, X52 are alternately coupled between output terminals CKb 'CK of inverters X53, X54, and latch output signals q, Qb, respectively; The NMOS transistor NM53 is connected between the output terminals Q and Qb and the output signal Q and Qb are equalized when the output signal CK from the inverter X54 is high; the logic circuit 202-1 is connected to the Chinese national standard according to this paper standard ( CNS) A4 specification (210 * 297 male i) (Please read the precautions on the back before filling this page)-IIII ί II ^ 1!] 1 !! 11 1 Printed clothing by the Intellectual Property Bureau of the Ministry of Economic Affairs, Consumer Consumption Cooperative 13

419S9I A? B7 V. Description of the invention () Input data D ATAIN generates the voltage difference between output terminals Q and Qb; and NMOS transistor NM54 is connected to the logic circuit when the enable signal from control block 201 is internal. 201-1 is grounded. The inverters X51 and X52 are respectively composed of complementary paired transistors (pM5) and NM51 (PM52 and NM52) connected in series between the clock signals CKb and CK. Fig. 7 is a schematic circuit illustrating a non-synchronous charge cycle differential logic circuit according to a second specific example of the present invention. As shown in the figure, the non-synchronous charge cycle differential logic circuit includes: the inverter X64 is composed of transistors PM64 and NM64 connected in series between the power supply voltage Vdd and the ground voltage Vss, and receives the enable signal at its gate respectively. Ei clock signal CKi and clock signal CKb whose drain output is inverted: the inverter X65 is connected in series by the transistor PM65 and NM65 between the power supply voltage Vdd and the ground voltage Vss, and is separately connected to its gate. Receive clock signal CKib and enable signal Eib and output non-inverting clock signal CK; inverters χ61 and χ62 are cross-coupled to clock signals CKb and CK 'and latch output signals q and Qb respectively; NMOS transistor 63 The channel is connected between the output terminals Q and Qb, and the voltage level of the output terminals Q and Qb is equalized when the output from the inverter X65 is high; the signal output unit 202-3 is connected to the power supply voltage Vdd and the output terminal Between Q and Qb, and receive the inverted clock signal CKb and output signals Q, Qb 'and output enable signal Eb; inverter X63 inverts enable signal Eb and outputs enable signal Eo; serial logic The circuit 2〇2_2 generates an output terminal according to the input data DATAm The voltage difference between the sub-Q and Qb; and the nmOS transistor NM68 is connected to the serial logic circuit 2O2 > _2 when the enabling k number is £ 11) is high. The standard of this paper standard (CNS ^ i. (2K) x297). (Please read the back of the page; i-notes before filling out this page) ^ 衣 · ---- I--Order ------ ---, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 14 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 419891 B; 5. Description of the invention (12) Here, the signal output unit 202-3 is inverted The clock signal CKb is applied to the gate of the PMOS transistor PM63. The source of the PM63 is applied with the power supply voltage Vdd. The output signal Q is applied to the gate of the NMOS transistor NM66. The source of the NM66 is applied with the output signal Qb. Qb is applied to the gate of the NMOS transistor NM67, and the source of the NM67 is applied with the output signal Q. As a result, the enable signal Eob is output from the common node of the transistors PM63, NM66, and NM67. The inverters X61 and X62 are respectively The individual complementary transistor pairs (PM61, NM61) (PM62, NM62) are connected in series between the clock terminals CKb 'CK. Section 9 is a schematic circuit diagram illustrating a non-synchronous charge cycle differential according to a third specific example of the present invention. Logic circuit. As the figure illustrates, the asynchronous charge cycle differential logic circuit package : Inverter X83 inverts the inverted enable input signal Eib and outputs the enable signal Eo; Inverter X84 inverts the inverted enable input signal Ei and outputs the inverted enable signal Eob ;-The inverters X81 and X82 are cross-coupled between the output terminals Eo and Eob of the inverters X83 and X84, and the individual output signals Q and Qb are latched; the channel of the NMOS transistor NM83 is connected to the output terminals Q and Qb And when the inverted enabling input signal Eib applied to its gate body is high, the voltage levels of the output terminals Q, Qb are equalized; the serial connection logic circuit 202-4 generates the output terminal Q according to the input data DATAIN The voltage difference between Qb and Qb; and NM0S transistor NM84, which is connected to the series logic 202-4 when the enable input signal Ei is high. The inverters X81 and X82 are connected by individual complementary transistors (PM8 and NM81). ) (PM82, NM82) connected in series to the enable signal Eo'Eob This paper is again applicable to the Chinese National Standard (CNS) A4 specification (2) 0 X 297 male f > 15 II a nn II If nc ^ i I tli — I n 1 ^ 1 I —OJ n ϋ —1 I 1 {Please read the notes on the back before filling this page) 419891 V. Description of the invention (Η) composition. Section 11 is a schematic circuit diagram illustrating a non-synchronous charge cycle differential logic circuit according to a fourth specific example of the present invention. As illustrated in FIG. 11, the non-synchronous charge cycle differential logic circuit includes an inversion Inverter X93 is not inverted, this round breaks into Ei, inverter X94 inverts the output k number from inverter X93, and turns out the enable signal Eo; — crossover to inverters χ91, X92 Connected between the power supply voltage Vdd and the output terminal of the inverter X93, i, and latch the output signals Q, Qb respectively; the channel of the PMOS transistor PM93 is connected between the output terminals Q, Qb, and when applied to its gate When the body enable signal is low, equalize the voltage levels of the output terminals Q and Qb; connect the logic circuit 202_5 to generate the electrical waste difference between the output terminals Q and Qb according to the input data DATA IN; and the NMOS transistor The NM93 is connected to the ground logic circuit 202-5 when the enable signal Ei is high. The inverters X91 and X92 are composed of a complementary transistor pair connected in series with a transistor (pM91, NM91) (PM92, NM92) between the power supply voltage Vdd and the enable input signal Ei. Fig. 13 is a schematic circuit diagram illustrating a non-synchronous charge cycle differential logic circuit according to a fifth specific example of the present invention. As shown in this figure, the asynchronous charge cycle differential logic circuit includes: an inverter composed of a transistor PM104 and NM104 connected in series between the power supply voltage Vdd and the ground voltage Vss, and each of them is received by its gate body. Can input the signal Ei and the completion signal Dni from the previous stage, and output the enable signal Ei; an inverter χΐ〇3 inverts the enable signal Ei 'and outputs the enable signal Eo; the individual inverter Xioi X10 is cross-coupled between the power supply voltage Vdd and the enable signal Ei, and the individual latches output the paper. The paper is suitable for the China National Standard (CNS) A4 specification (210 X 297 mm):-installed --- ( Please ^ -Read the main instructions on the back and fill in this page) Order:-Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 16 A7 413S91 — V. Description of the invention (Η) Signal Q, Qb; — PMOS The channel of the crystal PM103 is connected between the output terminals Q and Qb, and when the enable input signal Ei is low, the output terminals Q and Qb are equalized; the signal output unit 202-7 is connected between the ground and the output terminals q and Qb. 'Receive enable signal E' and output signals Q, Qb, and output as Industry completion signal Dno: —series logic circuit 202-6 outputs data signals to output terminals q and Qb according to variable data input DATAIN; and NMOS transistor NM105 connects series logic when the enable turn-on signal Ei is high Circuit 202-6 is grounded. Here, at the signal output unit 202-7, the enable input signal Ei is added to the gate of the NMOS transistor NM103, the source of the NM103 is grounded, and the output wave Q is applied to the gate of the P MOS transistor PM 105. The source is externally applied with the output signal Qb, and the output signal Qb is externally applied to the gate of the PMOS transistor PM106. The source of the PM106 is externally applied with the output signal Q. Thus, the transistor NM103, PM105, and PM106 are used in common. The job completion signal Dno is output. The inverters XI01 and XI02 are formed by connecting individual complementary transistor pairs (PM1 (H, NM101) (PM102, NM102) in series) between the power supply voltage Vcίd and the enable signal Ei '. As explained in Section 8 (a), the latch Lock block 203 and confirm that the signal ACKIN is applied to the gate of the PMOS transistor PM72, the source of PM72 is connected to the power supply voltage Vdd, and also to the gate of the NMOS transistor NM72, and the source of the NM72 is grounded. Input data signals Din and The output signal OUT or —0ί7Γ from the function block 202 is applied to the gate of the NMOS transistor NM73, the source of the NM73 is connected to the drain of the NMOS transistor NM72, and the paper size applies the Chinese National Standard (CNS) A4 (210 X 297 mm) I—FII · I- ί t, I n tlr i-nn EI nt— nnn tf f I— k 1 1 (Jing-it—read on the back of the book; I will fill in this page if you want to know more) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the employee 17 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the cooperative 419391 A7 B7 V. Description of the invention (u) The enabling signal E0 from the function Fanghun 202 is added to the PMOS transistor The gate of PM7 1 and the source of PM71 are connected to pm〇S power. The body of PM72 is also added to the gate of NMOS transistor NM71. The source of NM71 is connected to the pole of NMOS transistor NM73. The common drain node of transistor pm71 and NM71 is connected to latch 203 -1 input terminals, of which a pair of inverters X72 'X71 are connected in parallel to invert the output signal out, and a delay circuit 203-2 is provided for the output signal Eo' from the function block 202 The request signal REQOUT is generated for the next stage. The operation and effect of the asynchronous pipeline configuration according to the present invention will now be described with reference to Figures 14A to 14D. The request signal REQOUT of the second stage in a state is at a low level when it comes from When the request signal REQIN in the previous stage is at the high level, the output signal Cki or Ei from the control block 201 becomes high. As a result, the function block 202 enters the evaluation period 'evaluation output value' and the enable signal generated at the high level Eo. Here, the enabling signal Eo is output as the acknowledgement signal ACKOUT of the previous stage. Then the 'latching block 203 operates the output data from the function block 202' The delayed enabling signal Eo undergoes a predetermined period And the request signal REQOUT is generated for the next stage, so that the communication latch period operation is completed. Here, when the request signal REQ0UT of the next stage is at a high level and a predetermined period of time elapses, the output signal from the control block 201 CKi or Ei goes low 'and function block 202 returns to the precharge period. In this way, the output terminals Q and Qb of function block 202 are equal to "i / 2Vda". This paper size applies to the national standard (CNS) A4 (210 X297 male cage) 18 I .---------- ^ I install -------- order · -------- line-(Please read the precautions on the back before filling in this page) 41SS91 A7 B7 V. Description of the invention (16) and function block 202 After a predetermined time has elapsed, a low-level enable signal Eo is output. (Please read the cautions on the back before filling this page) In other words, the asynchronous system with pipeline configuration according to the present invention repeats the foregoing process and data operations through the sequence illustrated in Figures 14A to 14D. As a result, the latch block 203 latches out the data 'from the function block 202 and transmits the data to the next stage. On the other hand, the data from the function block 202 is transmitted to the next stage through the latch block 203. The latch block 203 includes the transistor PM71, NM71-NM73, the latch 203-1 and the delay circuit 203-2, as shown in FIG. 8 Instructions. In other words, 'when the confirmation signal ACKIN and the enable signal Eo are at a low level', the high level signal is added to the latch 203_1, so the output data signal DATAOUT is output at a low level. "The confirmation signal ACKIn and the enable signal Eo is in a high level state. When the input data signal Din goes high, the low level k number plus the latch 203-1 'so as to maintain a low level state before the output data signal DATAOUT. In the case where the acknowledgement signal ACKIN and the enable signal are at different levels, the latch 203-1 maintains the previous output level. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs of the Consumer Cooperative Cooperative Association * '1 The delay circuit 203-2 receives the enable signal E0, delays the enable signal £ 0 after a predetermined time, and outputs a sub-phase request signal REQ〇UT. In addition, the function block 202 is composed of a non-synchronized charge-cycle differential logic circuit. The operation of the function block 202 according to a specific example of the present invention will now be explained. 1 * First, the operation of the function block 202 according to the first specific embodiment of the present invention for executing the circuit shown in FIG. 6 will be described. This paper has been scaled to the Chinese National Standard (CNS) A4 (21,297 mm). 19 A7 41GS91 ____B7_____ 5. Description of the invention (Π) When the enable signal Ei from the control block 201 is at a low level, at that time When the pulse signal CKi is at a high level and the clock signal CKib is at a low level, the function block 202 enters a precharge period. The high-level clock signal cKi is inverted by the inverter X53, and thus output as the low-level clock signal CKb. The low-level clock signal CKib is inverted by the inverter X54, so that the output is a high-level clock signal CK. Therefore, the clock signals CK and CKb are at the high and low levels, respectively. Therefore, the cross-coupled inverters X51 and X52 are maintained in the off state with respect to the output terminals Q and Qb. The NMOS transistor NM53, which is an equivalent transistor, is turned on by the high-level clock signal CK, and then the voltage levels of the output terminals Q and Qb are precharged to "l / 2Vda". Here, the enable signal Ei from the control block 201 is at a high level, and the NMOS transistor NM54 is turned on. The logic circuit 202-1 is connected in series. The output terminal q and Qb are generated by performing a logical operation on the input data DATAIN. The voltage difference. The estimated output terminal q is at a high level. Subsequently, the function block 202 of "clock signal CKi changes from high to low" and clock signal CKib changes from low to high "enters the evaluation period. The inverter χ53 inverts the low-level clock signal CKi and outputs the south-level clock signal CKb. The inverter X54 inverts the high-level clock signal CKib 'and outputs a low-level clock signal ck. Therefore, the inverters X5 1, X52 are enabled 'so as to evaluate the data values of the output terminals Q, Qb at a high speed. Since the output terminal Q is estimated to be at a high level, the PMOS transistor PM51 is disconnected and the NMOS transistor NM51 is turned on, so that the inverter X51 pulls down the output terminal Qb to a low level. In addition, the pM〇s transistor PM52 is turned on, and the NMOS transistor NM52 is disconnected. 'So the paper size applies to the Chinese national standard (CN Fiction J specifications (210 x 297 mm > t -------- ---- I ^ -------- ^ --------- 1 (Please read the notes on the back before filling in this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 20 —41 Coffee 1_: ___ 5. Description of the invention (18) The phaser X52 pulls up the output terminal Q to a high level. (Please read the precautions on the back before filling this page) The individual levels of the output terminals Q and Qb are based on the foregoing. The job is transmitted to the next stage, and as a result, the clock signals CK and CKb are also transmitted as the clock signals CKi and CKib. Thereafter, when the clock signal CKi changes from low to high and the clock signal CKib changes from high to low, the function block 202 returns to the precharge period. As a result, the high-level clock signal CKi is inverted by the inverter X53, and is rotated out as the low-level clock signal CKb. In addition, the 'low-level clock signal CKib is inverted by the inverter χ54 The phase and output are used as the high-level clock signal CK. Because the clock signals CK and CKb are at the high and low levels, respectively, the cross-coupled inverter X51 'X52 The output terminals q and Qb are disconnected, and the NMOS transistor NM53 is turned on in response to the high-level clock signal CK, thereby connecting the output terminals Q and Qb. As a result, the output terminals Q and Qb are precharged to "l / "2Vda". In other words, 'the precharge period and the evaluation period are repeated according to the level changes of the clock signals CKi and CKib, so that the input data is sequentially transmitted to the next stage. The Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the first The operation of a specific example in the phase of the function block 202 is extremely effective only with a short delay. Now referring to FIG. 7, the operation of the function block 202 of the circuit of FIG. 7 according to the second example of the present invention will be described. The circuit operation is very similar to the circuit in Fig. 6, except for the enabling sequence of the cross-coupling inverters X61 and X62. Taking the circuit in Fig. 7 as an example, the clock signal CKi is changed to a high level 21 paper standards Applicable to China National Standard (CNS) A4 specification (210x 297 mm) 419891 A7 B7 V. Description of the invention (19) In the state, the cross-coupled inverters X61 and X62 of the current terminal are not enabled until the operation of the previous stage is completed and The enable input signal Ei becomes active. In the asynchronous charge cycle differential logic circuit according to the second specific example of the present invention, when the operation of one stage of the function block 202 is delayed for a relatively long time, the disadvantages caused by the previous evaluation may be Overcome. The operation details will now be explained. 0 When the clock signal Cki is at a high level and the clock signal CKib is at a low level, the enable input signal Ε is at a high level and the input enable signal Eib is at a low level. Bits, and inverters X61, X62 are disabled. At this time, the NMOS transistor NM64 is turned on by the high-level clock signal CCl, and the clock terminal CKb is at a low level. The PMOS transistor PM65 is turned on by the low-level clock signal CKib, and the clock signal CK is at a high level. The clock signals CKb and CK are at the low and high levels respectively, so the cross-coupled inverters X61 and X62 are maintained in the off state. The NMOS transistor NM63 is turned on by the high-level clock signal CK, and the output terminals Q and Qb are precharged to "l / 2Vda". The clock signal CKb is at a low level, so in the signal output unit 202-3, the PMOS transistor PM63 is turned on and the enable signal Eb is output at a high level. The inverter X63 is applied with a high-level enable signal Eob, and the inverter X63 outputs a low-level enable input signal Eo. When the clock signal CKi changes from high to low and the clock signal CKib changes from low to high, if the enable input signal Ei changes from high to low and the input enable signal Eib changes from low to high, the NMOS transistor NM64 and the PMOS transistor PM65 is disconnected, and the paper sizes of PMOS transistor PM64 and NMOS transistor NM65 are applicable to the national standard (CNS) A4 specification (210x 297 g t) I If I— n I— nn ^ 1 *. ^ 1 n 1 JT ·-rf i ί iin 04 ann I— nnn I ^ > 1 (Please read the note on the back; please fill in this page for matters) The Intellectual Property Bureau, Ministry of Economic Affairs, Employee Consumer Cooperatives, Printed Agriculture 22 A7 419S91 B7 V. Invention Explanation (20) Since then it was turned on. (Please read the note on the back first) and then fill out this page) So, the inverted clock signal CKb is at the high level instead of the inverted clock signal CK at the low level. ”As a result, the cross-coupled inverter X61, X62 is put into operation as far as the output terminals Q and Qb are concerned. At this time, when the NMOS transistor NM68 is added to its gate body by the input enable signal Eib and turned on, the series logic circuit 202-2 generates a voltage difference between the wheel output terminals Q and Qb according to the input data DATAIN. Here, for example, it is estimated that the output terminal Q is at a high level. In this way, the PMOS transistor PM61 is disconnected and the NMOS transistor NM61 is turned on by applying a high level signal from the output terminal Q. Therefore, the inverter X61 pulls down the output terminal Qb at a high speed. On the other hand, the PMOS transistor PM62 is turned on, and the NMOS transistor NM62 is disconnected by applying a low level of the output terminal Qb. As a result, the inverter X62 pulls up the level of the output terminal Q at a high speed. Here, in the signal output unit 202-3, the PMOS transistor PM63 is disconnected by applying a high-level clock signal CKb. However, in the above example, it is estimated that the output terminal Q is at a high level, so that the NMOS transistor NM66 is used. Turn on and enable signal Eb goes low. The Ministry of Economic Affairs knows that the Shui Property Bureau employee consumer cooperation Du printed garments So, the inverter X63 reverses the enable signal Eob at a low level, so that the enable signal Eo becomes high. Then, when the clock signal CKi changes from low to high and the clock signal CKib changes from high to low, if the input enable signal Ei transitions from low to high and the input enable signal Eib transitions from high to low, the cross-coupling inverter X61 X62 and X62 are de-energized, and NMOS transistor NM63 is turned on, so the output terminals Q and Qb are again 23. This paper size is applicable to China National Standard (CNS) A4 (210 x 297 mm) A7 419391 B7 _ V. Description of the invention ( 21) Pre-charge to "l / 2Vda". The month's operation is repeated when the levels of the signals Ej / Eib and CKi / CKib generated by the control block 201 are changed. The operation and effect of executing the functional block 202 of the circuit shown in Fig. 9 according to the third specific example of the present invention will now be described. When the inverted input enable signal E ib is at a high level and the non-inverted input enable signal Ei is at a low level, during the equalization period, the high level turn-on enable signal Eib is inverted The inverter X83 is inverted and rotated out as the low-level enable signal E0, and the low-level input enable signal Ei is inverted by the inverter χ84 and output as the south-level enable signal Eob. In this way, the enabling signals Eo and Eob are respectively at the low and high levels, so the cross-consumer inverters X81 and X82 are maintained in the off state with respect to the output terminals Q and Qb. The NMOS transistor NM83, which is an equivalent transistor, is turned on by applying a high-level input enable signal Eib, so the voltage level of the pre-charge output terminals Q and Qb reaches "l / 2Vda". Subsequently, when the input enable signal Eib changes from high to low and the input enable signal Ei changes from low to high, the enable signal Eo goes high and the enable signal Eob goes low, so the sensing / evaluation period starts. At this time, 'in the state where the NM0S transistor NM83 is enabled by an external low level input, the Eib is disconnected, and the NMOS electric body NM84 is enabled by the external high level input enable signal Ei'. Connect the logic circuit 202-4 to the input data. Perform a logic operation to thereby generate a voltage difference between the output terminals Q and Qb. Here, for example, it is estimated that the output terminal Qb is discharged to the ground potential, and thus becomes low. Therefore, the inverters X81 and X82 use the high-speed evaluation output terminals q and Qb of this paper to comply with the Chinese National Standard (CNS) A4 specification (210 x 297 mm t) i ″ ---- II I — I l · I * III I --- «— tilt-- (Please read the notes on the back and fill in this page again) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs? Clothing 24 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 41999i A7 _________B7 _ V. Voltage difference of invention description (22). The previous example assumes that the level of the output terminal Q is high. Therefore, the pM0S transistor PM81 is disconnected and the NMOS transistor NM81 is turned on, so that the inverter X81 pulls down the output terminal Qb to a low level. In addition, the pM0s transistor PM82 is turned on, and the NMOS transistor NM82 is disconnected. In this way, the inverter χ82 pulls up the output terminal Q to a high level. The levels of the output terminals Q and Qb are transmitted to the next stage according to the foregoing operation. The enabling signals 彳 § Eo and Eob are also transmitted as input enabling signals Ei and Eib in the next stage. Subsequently, the input enable signal Ei is changed from high to low, and the enable signal Eib is changed from low to high ', thus starting the equalization period. At this time, the inverter χ83 inverts the high-level input enable signal Eib and outputs a low-level input enable signal E0, and the inverter χ84 inverts the low-level enable signal Ei and outputs a high-level enable signal. E〇b. In this way, the enable signals Eob and Eo are respectively at the high and low levels, so the parent fork-coupled inverters X81 and X82 enter the off state. : The NTMOS transistor NM83 is turned on by the high-level input enable signal Eib ′ and connected to the output terminal q ′ Qb. As a result, the output terminals Q, Qb are precharged to r 1 / 2Vda ”. In other words, according to changes in the input enable signals Ei and Eib levels, the equalization period and the sensing / evaluation period are repeatedly exchanged, so that the input data DATAIN is sequentially transmitted to the next stage. As shown in FIG. 10, the three-bit chain connection configuration of the functional blocks can be implemented by serially connecting the functional block circuits 211-213, and the functional block circuits 211-213 each execute the circuits shown in FIG. 9 to perform the foregoing operations. The operation and effect of executing the functional block 202 of the circuit shown in Fig. 1 丨 according to the fourth specific example of the present invention will now be explained. --- I .----------, · ^ -------- Order --------- line (This page) The paper size applies to the Central Family Standard (CNS) A4 specification (2ιυ x 297 mm) 25 Printed by the Employees ’Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 419991 at _ B7___ V. Description of the invention (23) Enter The energy signal Ei is in the lower order and during the evaluation period. The inverters χ93 and X94 sequentially invert the low-level input enable signal and output the low-level enable signal Eo. At this time, the output signal Ei from the inverter X93 is at a high level, so that the inverter X91 X92 cross-connects with respect to output terminals Q and Qb and forms a pull-up / pull-down circuit into the off state. The PMOS transistor PM93 is turned on by the level input enable signal Ei ', so the level of the pre-charge output terminals q, Qb reaches "l / 2Vda". CMIS inverter X9: 'The individual PMOS transistors PM91 and PM92 of X92 are directly connected to the power supply voltage Vdd', so the pre-charge current is located slightly south of this circuit than the circuit in Fig. 9. Then, when the input enable signal Ei changes from low to high, the sensing / evaluation period starts. At this time, in a state where the PMOS transistor PM93 is disconnected and the NMOS transistor NM93 is turned on by an external high-level enable signal Ei, the serial logic circuit 202-5 performs a logical operation on the data DATAIN, thereby generating an output terminal. The voltage difference between Q and Qb. Here, for example, it is estimated that the output terminal sand is discharged to the ground potential and becomes low. Therefore, the inverters X91 and X92 evaluate the voltage difference between the output terminals q and Qb at high speed. In the above example, the level of the output terminal Q is estimated to be high. Therefore, the PMOS transistor PM91 is disconnected, and the NMOS transistor > ^ 91 is turned on, so that the inverter X91 pulls down the output terminal Qb to a low level. In addition, the pM0s transistor PM92 is turned on, and the NMOS transistor NM92 is disconnected, so that the inverter X92 pulls up the output terminal Q to a high level. This paper is again applicable to China National Standard (CNS) A4 specifications (210 297 mm) (Please read the notice on the back before filling out this page) -· Line 26 419891 A7 __— _ B7 V. Description of the invention (24) According to the aforementioned operation, the level of the output terminal Q'Qb is transferred to another stage. The enable signal E0 is also transmitted as an input enable signal of the next stage. Then, the input 'causes this number Ei to change from high to low, and the evaluation period starts. At this time, the inverters X93 and X94 sequentially invert the low-level input enable signal m, and turn out the low-level enable signal Eo. Therefore, the 'enable k' Eo is at a low level and the cross-consumption inverter 1, X92 is disabled. The PMOS transistor PM93 is enabled by an external low level input " is number Ei is turned on and connected to the output terminals Q, Qb. As a result, the round-out terminals Q, Qb are precharged to about Fi / 2Vda ". In other words, when the level of the input enable signal Ei is changed, the equalization period and the sensing / evaluation period are repeatedly exchanged, thereby sequentially transmitting the input data D ATAIN to another stage. "As shown in Figure 12" Function Block 5 The bit link chain configuration can be implemented through the data terminals of the serial connection function block circuit 22 and 225. 221-225 each executes the circuit shown in (11) for the aforementioned operation. 6 In this case, the input enable signal Ei has a predetermined delay. Time, and is transmitted to the stage after the next stage. For example, the input enable signal of the 'circuit 221 passes through a delay circuit composed of a pair of inverters connected in series, and is input as the enable signal Ei of the circuit 223. As a result, the enable signal Eo and the data signal Q are obtained. Finally, the effect of performing the operation of the function block 202 of the circuit shown in Fig. 13 according to the fifth specific example of the present invention will be described. When the input enable signal Ei is at a low level and the paper size from the previous stage is applicable to the Chinese National Standard (CNS) A4 specification (210 ^ 297 male f) 27-(Please read the precautions on the back before filling (This page) r Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, India ’s Consumer Cooperatives. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs. 1 Printed by the Consumers ’Cooperative 419891 A7. At this time, the PM104 transistor PM104 is turned on and the 'enable signal Ei' becomes high, so that the inverter χιοι 'XI02 is in an off state. At this time, the 'enable signal Ei' is at a high level, so that the signal output unit 202-7 'NMOS transistor NM103 is turned on, and a low-level operation completion signal Dno is output. The inverter XI03 receives the high-level enable signal Ei, and outputs a low-level enable signal Eo. The PMOS transistor PM103 is enabled by an external low-level input enable signal, so that the output terminals Q and Qb are precharged to "i / 2Vda". Thereafter, when the input enable signal Ei transitions from low to high, the pMOS transistor PM103 and PM104 are turned on, the output terminals q and Qb are disconnected from each other 'and the enable signal Ei' is in a high impedance state. At this time, in a state where the NMOS transistor NM105 is turned on by an applied high-level enable signal, the serial logic circuit 202-6 generates a voltage difference between the output terminals Q and Qb by performing an operation on the input data DATAIN. Here, for example, it is estimated that the output terminal Qb becomes high. > When the operation completion signal Dni from the previous stage goes high, the NMOS transistor NM104 is turned on and the enable signal Ei becomes low. As a result, the cross-coupled inverters XI01 and X012 are activated. The inverter X〗 03 inverts the low-level enable signal Ei '' so that the enable signal Eo becomes high. Therefore, according to the high level of the output terminal Q, the PMOS transistor PM101 is disconnected, and the NMOS transistor NM101 is turned on. In this way, the inverter x1 pulls up the level of the output terminal Qb at high speed. According to the low level of the output terminal Qb, the PMOS transistor PM102 can be turned on. The NMOS transistor NM102 is broken. The paper size applies the Chinese National Standard (CNS) A4 specification (210x 297 meals). 28-------- r I -------- ^ -------- 丨 line (please read the Jiang Yi matters on the back before filling out this page) 419891 A7 —… __B? ____ V. Description of the invention (26) In this way, the inverter X102 pulls up the level of the output terminal q at a high speed. (Please read the back of this page first; and then fill in this page.) In addition, at the signal output unit 202-7, because the enable signal Ei is at a low level, the NMOS transistor Zhao NM103 is disconnected. However, the output terminal q is at the upper level 'and the output terminal Qb is at the lower level, so that the pMOS transistor PM106 is turned on, thereby outputting a high-level job completion signal Dn0. Subsequently, when the input enable signal Ei transitions from high to low, if the job completion signal Dni from the previous stage changes from high to low, and thus the PMOS transistor PM104 is turned on, the enable signal Ei becomes high. In this way, the AC and AC inverters 101 and 102 are deenergized, and the 卩 1 ^ 〇8 transistor? 1 ^ 103 is turned on, thereby pre-charging the output terminals Q and Qb again to "〖/ 2Vda". Whenever the transition from the control block 201 to the level of the input enable signal Ei of the function block 202 is transitioned, the foregoing operations are repeatedly performed. According to the foregoing specific example of the present invention, the serial logic circuits 202-2, 202-2 '202-4, 202-5, 202-6 may be replaced by complementary output conduction crystal logic networks. Data is input to output terminals Q and Qb to generate data.

As discussed earlier, unlike the synchronous system, the asynchronous system of the present invention does not use a universal clock signal, so there is no clock skew problem. In addition, the asynchronous system of the present invention performs communication between blocks by using local control signals, and as a result, the clock dispersion can be reduced. When using conventional differential series voltage switch (DCVS) logic, power is significantly consumed. However, the non-synchronous system of the present invention has power-efficient operation characteristics, which can reduce power consumption. According to the present invention, it is not necessary to control the PMOS transistor of the cross-coupled inverter pair. 29 This paper size meets the Chinese National Standard (CNS) A4 specification_ (2〗 0 X 297 meals) 419991 i. The invention's description (27) body threshold Voltage. Therefore, no high voltage is required to control the threshold voltage, and as a result, high-speed processing is achieved without consuming a small amount of power. In addition, it is easy to apply the asynchronous configuration of the present invention to a digital design and the cost can be reduced. Because the present invention can be embodied in several forms without departing from the essence or essential features, it is also necessary to understand that the foregoing specific examples are not limited by any of the details described above unless otherwise specified, and need to be regarded as falling broadly into the accompanying patent application Consumption is within the scope and scope of the boundary, so all the requirements and limits within the scope of patent application and the changes and modifications within the boundary or its equivalent are intended to be included in the scope of the accompanying patent application. --.------------ 'yi .------- order --------- line (please read the note on the back before filling this page) Economy Printed by the Intellectual Property Cooperative of the Ministry of Intellectual Property, π 30 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (2) ϋ X 297 mm) 419S91 A7 B7 _; _ 5. Description of the invention (28) Component reference comparison (please Read the -1¾ item on the back before filling in this page) 101 ... Control block 102 ... Function block 103 ... Complete detector 104 ... Latch block 104-1 ... Latch 2 01 ... Control block 201-1 ... Cascade Logic circuit 202 ... Function block 202_1 ~ 2, 4 ~ 6 ... Cascaded logic circuit 202-3 ... Signal output unit 203 ... Latch block 203-1 ... Latch Printed by employee consumer cooperative of Intellectual Property Bureau, Ministry of Economic Affairs 211 ~ 3 ... functional block circuit 221 ~ 5 ... functional block circuit CK ... clock signal Ei ... input enable signal Ei '... output signal £ 〇 ··· low-order enable signal NM ... NMOS transistor PM ... PMOS transistor Q ... Output terminal Vdd ··· Supply voltage X- ·· Inverter This paper size meets China National Standard (CNS) A4 specification (210 x 297 mm)

Claims (1)

ABCD 419S91 ~, patent application scope 1. A non-synchronous sensing differential logic circuit, comprising: a control block for performing logical operations on the request signal from the previous stage and the request signal from the next stage, and for The operation turns out the first or second input enable signal and the first or second clock signal; a function block is used to according to the first or second input enable signal and the first or second clock from the control block The signal operates on the input data and is used to output the first or second output enable signal and output data; and a latch block, which is triggered by a confirmation signal from the next stage and passes the first from the function block. Or, the second output enable signal and the output data perform an operation to output a request signal for a next stage and a final output data. 2. The circuit of item 1 in the scope of patent application, wherein the first and second inputs are 1½, the first and second clock signals, and the first and second round enable signals are in opposite phases. 3_ The circuit of item 1 in the scope of patent application, wherein the functional block includes: a first inverter for inverting the first clock signal from the control block, and for outputting a third clock signal; a first Two inverters are used to invert the second clock signal from the control block and to output a fourth clock signal; a first PMOS transistor having its source connected to receiving a third clock signal, and its sink The pole is connected to the first round of output nodes, and the interstitial body is connected to the second round of output nodes; (please read the notes on the back before filling in this card) * 1T-printed by the shellfish consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Τ Printed A8 training m_I by the Central Procurement Bureau of the Ministry of Economic Affairs VI. Patent application scope ~--The second PMQS transistor has its source connected to receive the third clock signal 'its drain connected to the The two output nodes and their gates are connected to the first output node; the -th NMOS transistor has its source connected to receive the fourth clock signal, its poles connected to the first output node, and its interstitial connection To the second output node; Two NMOS transistors with their sources connected to receive the fourth clock signal, their drains connected to the second output node, and their gates connected to the first output node; a second NMOS transistor with its source And drain are respectively connected to the individual gates of the second and fourth transistors, and are individually connected to the first and second round-out nodes, and their gate systems are connected to receive the fourth clock signal; a series of logic circuits It is used to initialize the first and second output nodes according to the input data; and a fourth NMOS transistor is used to ground the internal switching elements of the logic circuit in series according to the first input enable signal from the control block. 4. The circuit according to item 3 of the patent application scope, wherein the functional block further includes an output enable signal generating unit including: a second PMOS transistor having a source connected to the receiving power voltage and a drain connected to the An output enable signal output terminal and its gate are connected to receive the third clock signal; and the fifth and sixth NMOS transistors having their drains connected to the drains of the second PMOS transistor are also connected to the receiver The first output enables the paper size of the financial system ^ (CNS) Α ί 2 2 GX297 mm) 33 (Please read the precautions on the back before filling this page) Order the work of the Central Bureau of Standards of the Ministry of Economic Affairs Cooperative cooperative seal «4iGS9.i Manganese C8 — ^ 一 ______ D8 please patent range signal output terminal, its individual source is connected to the first and second output point, and its individual gate system is alternately connected to the first-and the first Second round out of nodes. 5. The circuit according to item 3 of the patent application, wherein the first inverter includes a fourth PMOS transistor having a source connected to receiving a power supply voltage and a gate connected to receiving a first input enable signal; And a seventh NMOS transistor having a drain connected to a drain of the first transistor, a source connected to a receiving ground voltage, and a gate connected to receiving a first clock signal; and a second inverter including : A fifth PMOS transistor has its source connected to the receiving power voltage, and its gate is connected to receive the second clock signal; and an eighth NMOS transistor has its drain connected to the sink of the fifth transistor The source is connected to the receiving ground voltage and the gate is connected to receiving the second input enable signal. 6. For the circuit in the third item of the patent application, wherein the serial logic circuit is replaced by a conducting crystal logic circuit, the network can generate data for the first and second output nodes according to the variable data output. 7. The circuit according to the item in the scope of patent application, wherein the functional block includes: first and second output nodes;-the first inverter is used to invert the first input enable signal from the control block, and is used for output A first output enable signal;-A second inverter is used to invert the second input paper (2iex297H) from the control block 34 (Please read the note ^^ on the back before filling this page), 1T Λ Ministry of Economy The Central Bureau of Standards and Technology, Shellfish Consumer Cooperation, printed 419S91 Shao C8 D8 patent application scope enable signal, and used to output a second output enable signal; a first PMOS transistor has its source connected to the receiving first-output Enable signal, its drain is connected to the first output node, and its body is connected to the second output node;-the first PMOS transistor has its source connected to receive the first output enable signal, its drain connected To the second output node, and its gate body is connected to the first output node; a first NMOS transistor has its source connected to receive the second output enable signal, its drain connected to the first output node, and Brake Connected to a second output node; a NMO S transistor has its source connected to receive a second output enable signal, its drain connected to a second output node, and its gate connected to a first output node; The second NMOS transistor has its source and terminal connected and named. To the individual closed poles of the second and fourth transistors, and alternately connected to the first and second output nodes, respectively, and having a gate body connected to receive a second input enable signal from the control block; a series connected logic circuit It is used for initializing the first and second output nodes according to the input data; and a fourth NMOS transistor is used for grounding and connecting logic internal switching elements according to the first input enable signal from the control domain. 8. The circuit of claim 7 in the patent scope, wherein the series logic circuit is replaced by a conducting crystal logic network, which can generate data for the first and second output nodes according to the variable data output. Private paper standards are applicable to China National Standards (CNS) M specifications (210 > < 297 mm) 35 -----------. 1% ------, 玎 ----- -f. I 4 * (Please read the precautions on the back before filling out this page) Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 衮 419S91 g _____ D8 VI. Patent Application Scope 9 'Circuits such as the first patent application scope The function block includes: first and second output nodes; a first inverter for inverting a first input enable signal from the control block and an output enable signal after inversion; a second The inverter is used to invert the inverted enable signal again and used to output an output enable signal. A first PMOS transistor has a source connected to the receiving power voltage and a drain connected to the first round. The output node and its gate are connected to the second output node; a first PMOS transistor has its source connected to the receiving power voltage, its drain is connected to the second output node, and its gate is connected to the first output Node: a first NMOS transistor having its source connected to receiving a signal from a first inverter The inverted enable signal has its drain connected to the first output node and its gate connected to the second output node; a second NMOS transistor has its source connected to receive the inverted signal from the first inverter. Phase enable signal, its drain is connected to the second output pin, and its closed connection is connected to the first round output node; a third NMOS transistor with its source and drain connected to the third and the third, respectively The individual gates of the four transistors are alternately connected to the first and second output nodes, respectively, and have their gates connected to receive the first input enable signal from the control block; a series of logic circuits are used for Data Initialization—the second and the second output nodes: and the Chinese paper standard (CNS) A4 specification (2) OX29? Mm) 36 1 ^ 1 ^^^ 1 n ^ in ^-ml n — ^ ϋ ^^^ 1 t (please read the precautions on the back before filling in this page) 418891 A8 B8 C8 D8 Central Government Office of the Ministry of Health—Industrial and Consumer Cooperation Du Yin ¾ 、 Patent application scope-second NMOS The transistor is used to ground the logic circuit in series according to the first input enable signal. Switching element portion. W · The circuit of item 9 in the scope of patent application, wherein the functional block further includes an operation completion signal generating unit including: a fourth NMOS transistor having its source connected to the receiving ground voltage, and its sum connected to the operation completion signal The output terminal and its gate are connected to the inverted signal receiving the first enable signal; and the fourth and fifth PMOS transistors have their individual drains connected to the drain of the first transistor and are connected to the operation Complete signal output terminals, and individual sources connected to the first and second output terminals, and their individual gates alternately connected to the first and second output terminals, and their individual gates alternately connected to the first and second output terminals . U • The circuit of item 9 in the scope of patent application, wherein the first inverter includes a sixth PMOS transistor having a source connected to receiving the power supply voltage, and a gate connected to receiving the first input enable signal; And a fifth NMOS transistor has its drain connected to the drain of the sixth pMOS transistor, and the output is an enable signal inverted, the source is connected to the receiving ground voltage, and its gate is connected to Receives an operation completion signal from one of the previous stages. 12. The circuit of item 9 in the scope of patent application, wherein the series logic is replaced by a conducting crystal logic circuit, and the circuit can generate data to the first and second output nodes according to a variable data input. U. The circuit of item 1 in the scope of patent application, wherein the flash lock block contains: This paper size is applicable to CN standards. (Training X plus public Chu) 37 .J 4 ------ 1T- ----- Ϋ, (Please read the notes on the back before filling out this page) 419S91 ABCD VI. Patent application scope ... A data input unit which connects the first and second PMOS transistors and the first to the first The three NMOS transistors are between the power supply voltage and the ground voltage. They receive a confirmation signal at the gates of the first PMOS transistor and the third NMOS transistor, and receive an output enable signal at the second PMOS transistor and the first NMOS transistor. A gate body, and a gate body that receives output data from a function block to a second NMOS transistor; a latch unit having an input terminal connected to a common node between the second PMOS transistor and the first NMOS transistor of the data input unit And is used for latching one of the signals; and a delay unit is used for delaying the output enable signal and generating a request signal for the second stage. (Please read the precautions on the back before filling out this page) Printing policy of the Employees' Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs This paper standard is in accordance with Chinese National Standard (CNS) A4 specification (21 × 47mm)