WO2012120760A1

WO2012120760A1 - Semiconductor device

Info

Publication number: WO2012120760A1
Application number: PCT/JP2012/000247
Authority: WO
Inventors: 山口　良一; 国泰石原
Original assignee: ルネサスエレクトロニクス株式会社
Priority date: 2011-03-09
Filing date: 2012-01-17
Publication date: 2012-09-13

Abstract

An asynchronous circuit (150) which is a first asynchronous circuit starts a process in response to the rising of a permission signal (al), raises a process completion signal (out) when the process is complete, and falls the completion signal (out) in response to the falling of the permission signal (al). A process start signal (satrt) which is an inversion signal of the process completion signal (out) is input to a control circuit (110) together with a clock signal (CLK). When both the start signal (start) and the clock signal (CLK) rise, the control circuit (110) raises the permission signal (al). When both the start signal (start) and the clock signal (CLK) fall, the control circuit (110) falls the permission signal (al). Thereby, while suppressing the increase of a circuit scale, processing speed of the asynchronous circuit can be maintained at a constant rate.

Description

Semiconductor device

The present invention relates to a semiconductor device, specifically, a technique for controlling the processing speed of an asynchronous circuit provided in the semiconductor device.

Accelerating processing and reducing power consumption are two issues that microcomputer developers are always facing, and technologies from various viewpoints have been proposed.

For example, asynchronous design technology is known for digital circuits of semiconductor integrated circuits. In the asynchronous circuit according to this technique, unlike the synchronous circuit that controls the entire circuit with one clock signal (global clock signal), the processing timing is controlled by a handshake signal exchanged between the circuits.

Asynchronous circuits have the advantage of faster processing speed than synchronous circuits because the processing time does not depend on the global clock signal. On the other hand, the amount of processing increases due to desynchronization, which increases power consumption per unit time. There's a problem.

Also, it is known that the processing speed of asynchronous circuits is not constant due to temperature and manufacturing variations. This may cause an operation mismatch depending on a product equipped with an asynchronous circuit, and is a big problem particularly for a microcomputer controlled by software.

Patent Document 1 discloses a technique for keeping the processing speed of an asynchronous circuit constant. This technique utilizes the fact that the processing of the asynchronous circuit becomes faster when the supplied voltage becomes higher and the processing of the asynchronous circuit becomes slower when the supplied voltage becomes lower. Specifically, the processing speed of the asynchronous circuit is measured, and the voltage is lowered when the processing speed is faster than the target speed, and the voltage is raised when the processing speed is slower than the target speed, according to the measured processing speed. Thus, the voltage supplied to the asynchronous circuit is adjusted. By doing so, the processing speed of the asynchronous circuit is kept constant at the target speed. FIG. 21 shows a processing speed stabilizing device 10 to which the reference is changed from FIG. 2 in Patent Document 1 and to which the technique is applied.

JP 2009-260612 A

As can be seen from FIG. 21, the processing speed stabilizing device 10 includes a period fluctuation pulse generation unit 14 (ring oscillator) for measuring the processing speed (number of pulses) of the asynchronous circuit 12 and a pulse measurement unit 30 (12-bit binary). Counter), constant cycle pulse generation unit 20 (crystal oscillator), operation / processing speed change condition setting unit 70 for setting a target speed (target pulse number), operation / processing speed change condition acquisition unit 60 operation / processing speed change Control unit 80, memory 52 for storing target speed, voltage control signal generation unit 50 (comparator 54 for comparing measured speed with target speed, and voltage regulator for adjusting voltage supplied to asynchronous circuit 12 40). In this case, there is a problem that the circuit scale for keeping the processing speed of the asynchronous circuit constant is large and the chip area increases.

The present invention has been made in view of the above circumstances, and provides a technique for keeping the processing speed of an asynchronous circuit constant and suppressing an increase in circuit scale.

One embodiment of the present invention is a semiconductor device. The semiconductor device includes a first asynchronous circuit that repeatedly executes a predetermined process and a control circuit that outputs a permission signal to the first asynchronous circuit.

The first asynchronous circuit starts the predetermined processing when the permission signal becomes valid, sets the processing completion signal to valid when the predetermined processing is completed, and when the permission signal becomes invalid The processing complete signal is set to the invalid state.

The control circuit receives a processing start signal that is an inverted signal of the processing completion signal and a clock signal, and outputs a permission signal to the first asynchronous circuit. The control circuit enables the enable signal when both the processing start signal and the clock signal are enabled, and sets the enable signal when the process start signal and the clock signal are both disabled. To.

The “valid state” and “invalid state” mean one of the rising state and the falling state and the other, respectively.

Note that what is expressed by replacing the semiconductor device of the above aspect with a method or a system including the semiconductor device is also effective as an aspect of the present invention.

The technique according to the present invention can keep the processing speed of the asynchronous circuit constant while suppressing an increase in circuit scale.

1 is a diagram showing a semiconductor device according to a first embodiment of the present invention. It is a figure which shows the circuit structural example of the control module in the semiconductor device shown in FIG. It is a figure which shows C element in the control module shown in FIG. It is a figure which shows the control circuit in the semiconductor device shown in FIG. 2 is a timing chart showing transitions of signals in the semiconductor device shown in FIG. It is a figure which shows the semiconductor device concerning the 2nd Embodiment of this invention. It is a figure which shows the circuit structural example of the control module in the semiconductor device shown in FIG. 7 is a timing chart showing transition of each signal in the semiconductor device shown in FIG. 6. It is a figure which shows the semiconductor device concerning the 3rd Embodiment of this invention. 10 is a timing chart showing transitions of signals in the semiconductor device shown in FIG. It is a figure which shows CPU concerning the 4th Embodiment of this invention. 12 is a timing chart showing transition of each signal in the CPU shown in FIG. 11. It is a figure which shows the processor concerning the 5th Embodiment of this invention. It is a figure which shows the semiconductor device concerning the 6th Embodiment of this invention. 15 is a timing chart showing transitions of signals in the semiconductor device shown in FIG. It is a figure for demonstrating a problem when the time from the start of this process to the next start exceeds 1 cycle length of a clock signal. It is a figure which shows the semiconductor device concerning the 7th Embodiment of this invention. FIG. 18 is a timing chart showing transitions of signals in the semiconductor device shown in FIG. 17 (part 1); FIG. 18 is a timing chart showing transitions of signals in the semiconductor device shown in FIG. 17 (part 2). It is a figure which shows the semiconductor device concerning the 8th Embodiment of this invention. It is the figure which changed the code | symbol with respect to FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. Note that, in each drawing, the same element is denoted by the same reference numeral, and redundant description is omitted as necessary.

For convenience of explanation, some terms are defined. First, “process” and “basic operation” are defined for the asynchronous circuit.

For example, in order to execute the process “F = (A + B + C) ² ”, the process is divided into three processes “D = A + B”, “E = D + C”, and “F = E ² ”. Are connected in stages. By doing so, the three asynchronous circuits realize the process “F = (A + B + C) ² ” by executing the respective processes while handshaking each other.

Regardless of the number of stages of asynchronous circuits included in the circuit, the process executed by the entire circuit is called a `` process '', and each process constituting each of the processes executed by each asynchronous circuit included in the circuit is expressed as `` process ''. This is called “basic operation”.

In the above example, the process “F = (A + B + C) ² ” is a process, and the three processes “D = A + B”, “E = D + C”, and “F = E ² ” are basic operations of the process. .

When the process is executed by a single-stage asynchronous circuit, the “process” and “basic operation” are the same.

For example, when the circuit that executes the process “C = A + B” is configured by an asynchronous circuit that executes the operation “C = A + B”, both the “process” and the “basic operation” are calculated as “C = A + B”. Become.

In the asynchronous circuit, in addition to the processing itself corresponding to the basic operation, data movement between registers for the processing is involved in order to execute the basic operation. In the following description, it is assumed that “basic operation” includes data movement between registers for the basic operation.

Next, the maximum value Tmax is defined.
As will be understood from the following description, the technique according to the present invention is a conventional technique that directly inputs a signal (hereinafter referred to as a “process start signal”) that is input directly to the first asynchronous circuit and causes the asynchronous circuit to start processing. Input to the control circuit, and the control circuit synchronizes the start timing of processing (basic operation) by the first asynchronous circuit with the clock. This first asynchronous circuit is the asynchronous circuit itself when the process is executed by a single-stage asynchronous circuit, and a plurality of asynchronous circuits perform their basic operations while handshaking each other. In the case where the process is executed sequentially, it is one of these asynchronous circuits.

The maximum value Tmax is the next execution from the start of the current execution of the process, assuming that the predetermined control circuit is not provided and the processing start signal is directly input to the first asynchronous circuit. This is the longest time that can be taken before the start of.

As described above, the processing speed of the asynchronous circuit is not constant due to manufacturing variations and environmental factors such as temperature. Therefore, conventionally, the length of time from the start of the current execution of the process to the start of the next execution varies. The maximum value Tmax is the maximum value in the fluctuation range of the time length.

Next, “valid state”, “invalid state”, “valid edge”, and “invalid edge” are defined for a signal that can have one of the rising state and the falling state.

The “valid state” of the signal is either one of the rising state and the falling state. For this reason, the “invalid state” is different from the “valid state” between the falling state and the falling state.

Also, “effective edge” means the beginning of the effective state. For example, when the valid state is a rising state, the valid edge is a rising edge, and when the valid state is a falling state, the valid edge is a falling edge. Similarly, “invalid edge” means the beginning of an invalid state.

Whether the effective edge or the effective state of the signal is to be determined may be appropriately determined from the consistency with other devices, the convenience of control, and the like.

In the following description, as an example, it is assumed that the effective edge is a rising edge and the effective state is a rising state.

Moreover, in the following description, while using the term defined above, the explanation of the term is not repeated when it is used.
<First Embodiment>

FIG. 1 shows a semiconductor device 100 according to a first embodiment of the present invention. The semiconductor device 100 executes a predetermined process by a single-stage asynchronous circuit, and includes a control circuit 110, an inverter 120, and an asynchronous circuit 150. This asynchronous circuit 150 corresponds to the first asynchronous circuit described above.

The asynchronous circuit 150 is a two-phase asynchronous circuit, and includes an arithmetic circuit 180 and a control module 160 that performs two-phase control on the arithmetic circuit 180.

The control circuit 110 outputs a permission signal al to the control module 160.
When the permission signal al rises, the control module 160 causes the arithmetic circuit 180 to perform a basic operation (same as the process here) that the asynchronous circuit 150 performs. After that, when the above process is completed, the control module 160 outputs a latch signal to the arithmetic circuit 180 to hold the arithmetic result, and raises a processing completion signal (hereinafter also simply referred to as “completion signal”) out. Thereafter, the control module 160 causes the completion signal out to fall in response to the fall of the permission signal al.

The completion signal out is output to the inverter 120. Inverter 120 outputs an inverted signal of completion signal out to control circuit 110.

Normally, in a semiconductor device that executes a process using a single-stage asynchronous circuit, the inverted signal of the completion signal out output from the asynchronous circuit instructs the asynchronous circuit to start the next process (basic operation). Signal. Therefore, here, the signal output from the inverter 120 is referred to as a processing start signal start. Hereinafter, the processing start signal is also simply referred to as “start signal”.

In a semiconductor device that executes a process using a single-stage asynchronous circuit, an inverted signal (start signal start) of the completion signal out output from the asynchronous circuit is directly input to the asynchronous circuit.

In the semiconductor device 100 of the present embodiment, the start signal start is input to the control circuit 110.

In addition to the start signal start, a clock signal CLK is also input to the control circuit 110.

The control circuit 110 raises the permission signal al when both the start signal start and the clock signal CLK are enabled, i.e., rises, and permits when both the start signal start and the clock signal CLK fall. The signal al falls.

In the semiconductor device 100 of the present embodiment, the cycle of the clock signal CLK is equal to or greater than the maximum value Tmax of the asynchronous circuit 150.

FIG. 2 shows an example of the circuit configuration of the control module 160 in the asynchronous circuit 150. As shown in FIG. 2, the control module 160 includes an AND element 161, an inverter 162, an AND element 164, an inverter 165, a delay element 166, and a C element 170. The permission signal al from the control circuit 110 is input to one input terminal of the AND element 161 and one input terminal of the C element 170. The inverter 162 has an input terminal connected to the output terminal of the C element 170 and an output terminal connected to the other input terminal of the AND element 161. A signal output from the C element 170 is OUT. The output terminal of the C element 170 is also connected to one input terminal of the AND element 164.

The output of the AND element 161 is input to the delay element 166. The output of the delay element 166 is output to the arithmetic circuit 180 as a latch signal lat, and is input to the other input terminal of the C element 170 and the input terminal of the inverter 165.

The AND element 164 receives the C element 170 and the output of the inverter 165, and outputs a logical product of them. This logical product is a completion signal out output from the control module 160.

The C element 170 is a Muller C element, and is a storage element whose output transitions to the input value only when all the input values match. FIG. 3 shows the configuration of the C element 170. The C element 170 receives the permission signal al and the latch signal lat output from the control module 160 shown in FIG. 2, and outputs a signal OUT.

The C element 170 includes three 2-input AND elements 171 to 173 and a 3-input OR element 174. Three inputs of the OR element 174 are outputs of the three AND elements 171 to 173.

The permission signal al and the output OUT of the OR element 174 are input to the AND element 171. The AND element 172 receives the permission signal al and the latch signal lat. The AND element 173 receives the output OUT of the OR element 174 and the latch signal lat.

FIG. 4 shows an example of the circuit configuration of the control circuit 110 in the semiconductor device 100. The control circuit 110 receives the clock signal CLK and the start signal start, and outputs the permission signal al.

The control circuit 110 includes three 2-input AND elements 111 to 113 and a 3-input OR element 114. Three inputs of the OR element 114 are outputs of the three AND elements 111 to 113.

The AND element 111 receives the clock signal CLK and the permission signal al that is the output of the OR element 114. A clock signal CLK and a start signal start are input to the AND element 112. The AND element 113 receives the permission signal al and the start signal start.

As can be seen by comparing FIG. 3 and FIG. 4, the control circuit 110 has the same configuration as the C element 170 except that the input signals are different. That is, the control circuit 110 is also a Muller C element, and only when all input values (clock signal CLK, start signal start) match, the output (permission signal al) transitions to the input value.

FIG. 5 is a timing chart showing transition of each signal in the semiconductor device 100 shown in FIG. In the initial state of the semiconductor device 100, it is assumed that each signal shown in FIG. 5 is “0” except for the start signal start signal. Since the start signal start is an inverted signal of the completion signal out, it is “1” in the initial state.

At time t1, the clock signal CLK rises. In response to this, the permission signal al also rises at timing t2. As a result, the operating phase of the asynchronous circuit 150 starts.

In response to the rise of the permission signal al at the timing t2, the latch signal lat rises at the timing t3 and subsequently falls at the timing t4. This starts the rest phase of the asynchronous circuit 150.

At timing t4, the completion signal out rises due to the fall of the latch signal lat.

In response to the rise of the completion signal out, the start signal start falls at timing t5. At this time, although the start signal start has changed from “1” to “0”, the clock signal CLK remains “1”, so the permission signal al is still “1”.

Then, at the timing t6, the clock signal CLK falls. Since the start signal start is also “0”, the permission signal al falls at timing t7.

Since the latch signal lat is “0”, the completion signal out falls at the timing t8 in response to the fall of the permission signal al at the timing t7. This completes the pause phase of the asynchronous circuit 150. Subsequently, at timing t9, the start signal start rises.

In the case of a normal asynchronous circuit in which the control circuit 110 is not provided and the start signal start is directly input to the control module 160, the next execution of the process (next operation phase) is performed in response to the rise of the start signal start. The start signal start is input to the control circuit 110 in the semiconductor device 100 of the present embodiment.

Therefore, even when the start signal start rises at the timing t9, the clock signal CLK remains “0”, so that the permission signal al also remains “0”. That is, the asynchronous circuit 150 does not start the next execution of the process even when the start signal start rises.

Thereafter, at timing t10, the clock signal CLK rises. Since the start signal start is “1”, the permission signal al rises at the timing t11.
As a result, the asynchronous circuit 150 starts the next execution of the process, that is, the next operation phase.

From timing t10 to t20, each signal follows the same transition as from timing t1 to t10. Such a transition is repeated after the timing t20.

As described above, since the processing speed of the asynchronous circuit varies depending on manufacturing variations and environmental factors such as temperature, the time required for each processing may also vary.

For example, in FIG. 5, the timing when the same time as the length (t3−t2) between the timings t2 and t3 has elapsed from the rising edge of the permission signal al at the timing t11 is the timing t12. However, in actuality, the latch signal lat rises at timing t13 delayed by Δt from timing t12. Therefore, the rise of the completion signal out and the fall of the start signal start are also delayed. In such a case, in a normal asynchronous circuit to which the start signal start is directly input, the start of the next processing is also delayed by Δt.

On the other hand, in the asynchronous circuit 150 in the semiconductor device 100 of the present embodiment, the control circuit 110 synchronizes the processing start timing of the asynchronous circuit 150 with the clock signal CLK signal, thereby causing the above-described shift. Even in such a case, the time from the start of the current process to the start of the next process (“t11-t2”, “t21-t11” in FIG. 5) is always the cycle “T” of the clock signal CLK. That is, the processing speed is constant when viewed from the whole processing (here, the process) that the asynchronous circuit 150 performs.

Further, only the control circuit 110 is added to realize this. As in the example shown in FIG. 4, the control circuit 110 that performs such control can be composed of C elements, that is, C elements including three AND elements and one OR element, so that the processing speed of the asynchronous circuit 150 is increased. There is little increase in the circuit scale required to keep it constant.
<Second Embodiment>

A semiconductor device 100 according to the first embodiment shown in FIG. 1 is an example in which the technique according to the present invention is applied to a two-phase asynchronous circuit. The technology according to the present invention is not limited to a two-phase asynchronous circuit, and can be applied to any asynchronous circuit. For example, the semiconductor device 200 of the second embodiment shown in FIG. 6 is an example in which the technique according to the present invention is applied to a two-wire asynchronous circuit.

As shown in FIG. 6, the semiconductor device 200 executes a predetermined process with a single-stage asynchronous circuit, and includes a control circuit 210, an inverter 120, and an asynchronous circuit 250. The asynchronous circuit 250 corresponds to the first asynchronous circuit.

The asynchronous circuit 250 is a two-wire asynchronous circuit, and includes a control module 260 and an arithmetic circuit 280.

The control circuit 210 outputs a permission signal al to the control module 260.
When the permission signal al rises, the control module 260 sets a signal (request signal req) output to the arithmetic circuit 280 to a value that causes the arithmetic circuit 280 to start calculation. When the calculation is completed, the arithmetic circuit 280 changes the notification signal ack to be returned to the control module 260 to a value indicating the completion of the calculation. Then, the control module 260 changes the request signal req to a value for causing the arithmetic circuit 280 to perform initialization, and when the initialization is completed, the arithmetic circuit 280 indicates the notification signal ack indicating the completion of initialization. Change to a value.

Further, the control module 260 raises a completion signal out to be output to the inverter 120 when the notification signal ack becomes a value indicating completion of initialization. Thereafter, the control module 260 causes the completion signal out to fall in response to the fall of the permission signal al.

The inverter 120 outputs an inverted signal of the completion signal out to the control circuit 110. This inverted signal is also a start signal start instructing the start of the next process (basic operation) in this normal asynchronous circuit of this type. Here, the start signal start is input to the control circuit 210.

A clock signal CLK is also input to the control circuit 210 in addition to the start signal start.

The control circuit 210 raises the permission signal al when both the start signal start and the clock signal CLK are enabled, that is, when the signal rises, and permits when both the start signal start and the clock signal CLK fall. The signal al is lowered, and the permission signal al is maintained at other times.

In addition, the control circuit 210 is comprised by C element similarly to the control circuit 110 shown in FIG.

FIG. 7 shows an example of the circuit configuration of the control module 260 in the asynchronous circuit 250. As shown in FIG. 7, the control module 260 includes an AND element 261, an inverter 262, an AND element 264, an inverter 265, and a C element 270. The permission signal al from the control circuit 210 is input to one input terminal of the AND element 261 and one input terminal of the C element 270. The inverter 262 has an input terminal connected to the output terminal of the C element 270 and an output terminal connected to the other input terminal of the AND element 261. The output terminal of the C element 170 is also connected to one input terminal of the AND element 264.

The output of the AND element 261 is output to the arithmetic circuit 280 as the request signal req. The notification signal ack from the arithmetic circuit 280 is input to the other input terminal of the C element 270 and the input terminal of the inverter 265.

The AND element 264 receives the C element 270 and the output of the inverter 265 and outputs a logical product of them. This logical product is a completion signal out output from the control module 260.

The C element 270 is a Muller C element similar to the C element 170 shown in FIG. 3, and a detailed description thereof will be omitted here. The output of the C element 270 transitions to the input value only when all input values (here, the permission signal al and the notification signal ack) match.

FIG. 8 is a timing chart showing transition of each signal in the semiconductor device 200 shown in FIG. In the initial state of the semiconductor device 200, it is assumed that each signal shown in FIG. 8 is “0” except for the start signal start signal. Since the start signal start is an inverted signal of the completion signal out, it is “1” in the initial state.

At time t1, the clock signal CLK rises. In response to this, the permission signal al also rises at timing t2. In response to this, the request signal req rises at timing t3.

Thereafter, the calculation by the calculation circuit 280 is completed, and the notification signal ack rises at timing t4. In response to this, the request signal req falls at timing t5.

Thereafter, initialization by the arithmetic circuit 280 is completed, the notification signal ack falls and the completion signal out rises at timing t6.

In response to the fall of the completion signal out, the start signal start falls at timing t7. At this time, although the start signal start has changed from “1” to “0”, the clock signal CLK remains “1”, so the permission signal al is still “1”.

Then, at timing t8, the clock signal CLK falls. Since the start signal start is also “0”, the permission signal al falls at timing t9.

Since the notification signal ack is “0”, the completion signal out falls at timing t10 in response to the fall of the permission signal al at timing t9. Subsequently, at timing t11, the start signal start rises.

Thereafter, at timing t12, the clock signal CLK rises. Since the start signal start is “1”, the permission signal al rises at timing t13.
As a result, the asynchronous circuit 150 starts the next execution of the process.

In response to the rise of the permission signal al, the request signal req rises at timing t14.

Thereafter, the calculation by the calculation circuit 280 is completed, and the notification signal ack rises at timing t16. In response to this, the request signal req falls at timing t17.

Thereafter, initialization by the arithmetic circuit 280 is completed, and at timing t18, the notification signal ack falls and the completion signal out rises.

In response to the fall of the completion signal out, the start signal start falls at timing t20.

Note that the clock signal CLK fell at the timing t19 between the timings t18 and t20. However, at the timing t19, the start signal “start” is still “1”, so that the permission signal “al” is still “1”. is there.

Since the start signal start falls at timing 20, the permission signal al falls at timing 21.

After that, the falling of the completion signal out and the rising of the start signal start are started, the clock signal CLK rises at the timing t23, and the permission signal al rises at the timing t24.
As a result, the asynchronous circuit 150 starts the next execution of the process.

In FIG. 8, the timing at which the same time as the length (t4-t3) between timings t3 and t4 has elapsed from the rising edge of the request signal req at timing t14 is timing t15. However, actually, the notification signal ack rises at timing t16 delayed by Δt from timing t15. Therefore, the subsequent fall of the request signal req is also delayed. In such a case, in a normal asynchronous circuit to which the start signal start is directly input, the start of the next processing is also delayed by Δt.

On the other hand, in the asynchronous circuit 250 in the semiconductor device 200 of the present embodiment, the control circuit 210 synchronizes the processing start timing of the asynchronous circuit 250 with the clock signal CLK signal, thereby causing the above-described shift. Even in this case, the time from the start of the current process to the start of the next process (“t13-t2” and “t24-t13” in FIG. 8) is always the cycle “T” of the clock signal CLK. In other words, the processing speed is constant when viewed from the entire processing (here, the process) performed by the asynchronous circuit 250.

Further, similarly to the semiconductor device 100 of the first embodiment, the increase in circuit scale necessary for keeping the processing speed of the asynchronous circuit constant is small.
<Third Embodiment>

The semiconductor device 100 and the semiconductor device 200 described above are examples in which the technique according to the present invention is applied to the case where all processes are executed by a single-stage asynchronous circuit. The technique according to the present invention can be applied to a case where a process is executed by an asynchronous circuit having an arbitrary number of stages of one or more. Here, as a third embodiment, a semiconductor device to which the technique according to the present invention is applied when a process is executed by a three-stage asynchronous circuit will be described. Further, as an example, these asynchronous circuits are assumed to be two-phase asynchronous circuits.

The semiconductor device 300 according to the third embodiment shown in FIG. 9 includes a control circuit 310, an asynchronous circuit 320, an asynchronous circuit 330, an asynchronous circuit 340, and an inverter 120. The asynchronous circuit 330 corresponds to the first asynchronous circuit.

The asynchronous circuit 320 has a control module 322 and an arithmetic circuit 324, the asynchronous circuit 330 has a control module 332 and an arithmetic circuit 334, and the asynchronous circuit 340 has a control module 342 and an arithmetic circuit 344. The control modules provided in these asynchronous circuits operate in the same manner as the control module 160 of the asynchronous circuit 150 in the semiconductor device 100 shown in FIG. 1, and detailed description thereof is omitted here. In order to distinguish the signals output by each control module, the completion signal and latch signal output by the control module 322 are denoted by out1 and lat1, and the completion signal and latch signal output by the control module 332 are denoted by out2 and lat2. The completion signal and the latch signal output from the control module 342 are expressed as out3 and lat3.

Usually, in this type of apparatus that executes a process by an asynchronous circuit having two or more stages, each asynchronous circuit in the second stage and thereafter is input with a completion signal output from the previous stage as a start signal. The completion signal output from the lowest asynchronous circuit is inverted by the inverter and input to the first asynchronous circuit as the start signal of the first asynchronous circuit. Note that the completion signal output from the lowest asynchronous circuit indicates the completion of the current execution of the process (basic operation) by the asynchronous circuit itself and the completion of the current execution of the process.

In the semiconductor device 300 of the present embodiment, the completion signal out3 output from the lowest-level asynchronous circuit (asynchronous circuit 340) here is output by the inverter 120 as in the case of this type of normal device. Inverted and input to the control module 322. Here, a signal output from the inverter 120 is denoted by end. This signal end becomes a start signal for the asynchronous circuit 320.

However, in the semiconductor device 300 of this embodiment, the completion signal out1 output from the first-stage asynchronous circuit (asynchronous circuit 320) is not output to the next-stage asynchronous circuit. As illustrated, the completion signal out1 is input to the control circuit 310. The control circuit 310 receives the completion signal out1 and the clock signal CLK, and outputs a permission signal al to the second-stage asynchronous circuit (asynchronous circuit 330). The permission signal al acts on the asynchronous circuit 330 in the same manner as the start signal.

The control circuit 310 synchronizes the start timing of processing (basic operation) by the asynchronous circuit 330 with the clock signal CLK. Similar to the control circuit 110 shown in FIG. 4 except that the cycle of the input clock signal CLK is different from the cycle of the clock signal CLK input to the control circuit 110 in the semiconductor device 100 shown in FIG. Is done.

The cycle of the clock signal CLK input to the control circuit 310 is equal to or greater than the maximum value Tmax of the asynchronous circuit 320 to the asynchronous circuit 340.

FIG. 10 is a timing chart showing the transition of each signal in the semiconductor device 300. For the sake of clarity, in FIG. 10, illustration of the latch signal output by each asynchronous circuit is omitted.

Suppose that the completion signal out3 falls at timing t1. In response to this, the signal end rises at the timing t2. As a result, the asynchronous circuit 320 starts processing (first basic operation of the process), and raises the completion signal out1 at the processing completion timing t3.

Although the completion signal out1 rises at timing t3, the enable signal al remains “0” because the clock signal CLK has not risen yet.

At time t4, the clock signal CLK rises. In response to this, the permission signal al rises at timing t5. Therefore, the asynchronous circuit 330 starts processing (second basic operation of the process) and raises the completion signal out2 at the processing completion timing t6.

Since the completion signal out2 is directly input to the control module 342 as the start signal of the asynchronous circuit 340, when the completion signal out2 rises at the timing t6, the asynchronous circuit 340 performs processing (the third or last basic process). Operation) is started, and the completion signal out3 is raised at the processing completion timing t7.

In response to the rise of the completion signal out3 at timing t7, the signal end falls at timing t8. In response to this, the completion signal out1 falls at timing t9. Thereafter, each signal is not changed until the timing t10 when the clock signal CLK falls.

When the clock signal CLK falls at the timing t10, the permission signal al falls at the timing t11. Thereafter, the completion signal out2 and the completion signal out3 sequentially fall, and the signal end rises at timing t14.

Each signal makes the same transition from timing t14 to timing t18 and from timing t2 to timing t14. Such a transition is repeated after timing t18.

As described above, in the semiconductor device 300 according to the present embodiment, the control circuit 310 synchronizes the start timing of the processing of the asynchronous circuit 330 with the clock signal CLK signal, so that the current process of the asynchronous circuits 320 to 340 is performed. The time from the start of execution to the start of the next execution (“t14-t2”, “t18-t14” in FIG. 10) is always the cycle “T” of the clock signal CLK. That is, the processing speed is constant when viewed from the whole process that the asynchronous circuits 320 to 340 take.

Further, only the control circuit 310 is added to realize this, and the increase in circuit scale is small.
<Fourth embodiment>

The semiconductor device 300 according to the third embodiment described above is an example in which the technique according to the present invention is applied to a case where a process is executed by a plurality of asynchronous circuits. In this example, the basic operation start timing is The asynchronous circuit (first asynchronous circuit) controlled to synchronize with the clock signal is the second stage.

When applying the technique according to the present invention when a process is executed by a plurality of stages of asynchronous circuits, the first asynchronous circuit may be any of the plurality of stages of asynchronous circuits. Here, as a fourth embodiment, a semiconductor device in which the first asynchronous circuit is at the uppermost stage of a plurality of asynchronous circuits will be described.

FIG. 10 shows a CPU 400 according to the fourth embodiment of the present invention. The CPU 400 is a CSIC asynchronous CPU, and includes an asynchronous control unit 402 and a data path unit 404.

Asynchronous control unit 402 includes control circuit 410 and five control modules connected in stages (fetch control module 422, decode control module 432, execution control module 442, memory access control module 452, and write back control module 462). And the inverter 120 that inverts the completion signal out5 output from the lowermost write back control module 462 and outputs the inverted signal (start signal start) to the control circuit 410. Each control module outputs a latch signal to a later-described flip-flop (hereinafter referred to as FF) of the data path unit 404.

The data path unit 404 includes a memory 406, an FF 424, an arithmetic circuit 434, an FF 435, an arithmetic circuit 444, an FF 445, an arithmetic circuit 454, an FF 455, an arithmetic circuit 464, and an FF 465.

The fetch control module 422 and the FF 424 constitute a first-stage asynchronous circuit (asynchronous circuit 420). The asynchronous circuit 420 performs processing for fetching an instruction from the memory 406.

The decode control module 432, the arithmetic circuit 434, and the FF 435 constitute a second-stage asynchronous circuit (asynchronous circuit 430). The asynchronous circuit 430 performs processing for decoding the instruction fetched by the asynchronous circuit 420.

The execution control module 442, the arithmetic circuit 444, and the FF 445 constitute a third-stage asynchronous circuit (asynchronous circuit 440). The asynchronous circuit 440 performs processing for executing the instruction decoded by the asynchronous circuit 430.

The memory access control module 452, the arithmetic circuit 454, and the FF 455 constitute a fourth-stage asynchronous circuit (asynchronous circuit 450). The asynchronous circuit 450 accesses an access target (for example, a flip-flop in a peripheral module (not shown)) in accordance with the execution of the instruction.

The write-back control module 462, the arithmetic circuit 464, and the FF 465 configure a fifth-stage asynchronous circuit (asynchronous circuit 460). Asynchronous circuit 460 performs write back upon completion of instruction execution.

Each asynchronous circuit raises a completion signal that it outputs when its processing (basic operation) is completed.

Asynchronous circuits 430 to 460 in the second and subsequent stages are processed by themselves when the completion signals (out1 to out4) output by the asynchronous circuits in the previous stage are directly input and the completion signals rise. Start (basic operation).

In this embodiment, the first-stage asynchronous circuit 420 is a first asynchronous circuit, and the start timing of the process is controlled by the control circuit 410 so as to be synchronized with the clock signal CLK.

The control circuit 410 is a C element that receives the clock signal CLK and the start signal start from the inverter 120 and outputs the permission signal al to the asynchronous circuit 420. The cycle of the clock signal CLK input to the control circuit 410 is equal to or greater than the maximum value Tmax of the asynchronous circuit 420 to the asynchronous circuit 460.

Further, the fetch control module 422 to the write back control module 462 perform two-phase control, and have a circuit configuration similar to that of the control module 160 shown in FIG. 2, for example.

FIG. 12 is a timing chart showing the transition of each signal in the CPU 400. In the initial state, the value of each signal is “0” except for the start signal start.

At time t1, the clock signal CLK rises. At this time, since the start signal start is “1”, the permission signal al rises at timing t2. As a result, the operating phase of the asynchronous circuit 420 starts. Then, after the rise of the latch signal lat1 at the timing t3, the latch signal lat1 falls and the completion signal out1 rises at the timing t4. As a result, the pause phase of the asynchronous circuit 420 starts and the operating phase of the asynchronous circuit 430 starts.

Next, after the rise of the latch signal lat2 at timing t5, the latch signal lat2 falls and the completion signal out2 rises at timing t6. As a result, the pause phase of the asynchronous circuit 430 starts and the operating phase of the asynchronous circuit 440 starts.

Then, after the rise of the latch signal lat3 at timing t7, the latch signal lat3 falls and the completion signal out3 rises at timing t8. As a result, the asynchronous phase of the asynchronous circuit 440 starts and the active phase of the asynchronous circuit 450 starts.

Next, after the rise of the latch signal lat4 at timing t9, the latch signal lat4 falls and the completion signal out4 rises at timing t10. As a result, the pause phase of the asynchronous circuit 450 starts and the operating phase of the asynchronous circuit 460 starts.

Then, after the rise of the latch signal lat5 at timing t11, the latch signal lat5 falls and the completion signal out5 rises at timing t12. In response to this, the start signal start falls at timing t13.

As can be seen from FIG. 12, the clock signal CLK falls before the timing t13. When the clock signal CLK falls, since the start signal start is still “1”, the permission signal al remains “1”.

When the start signal start falls at the timing t13, the two inputs (clock signal CLK, start signal start) of the control circuit 410 become “0”, so that the permission signal al falls at the timing t14. Thereafter, the completion signal out1, the completion signal out2, and the completion signals out3, out4, and out5 also sequentially fall. As a result, the start signal start rises at the timing t20.

In a normal asynchronous CPU in which the start signal start is directly input to the first stage asynchronous circuit, the first stage asynchronous circuit starts the next execution of processing by the rising edge of the start signal start at timing t20. In the CPU 400, as shown in FIG. 12, even if the start signal start rises at the timing t20, the permission signal al does not rise, and the first-stage asynchronous circuit 420 remains in a pause phase.

Thereafter, the clock signal CLK rises at timing t21. Since the two inputs of the control circuit 410 are both “1”, the permission signal al rises at timing t22. As a result, the asynchronous circuit 420 starts the next execution of the process. Since the asynchronous circuit 420 is the first stage asynchronous circuit, the timing t22 is also the next start timing of the processes executed by the asynchronous circuits 420 to 460.

The transition of each signal from timing t1 to timing t21 is repeated from timing t21. In this way, as can be seen from FIG. 12, the time from the start of execution of the process to the start of the next execution (“t22-2”) is always maintained at the same length as the cycle T of the clock signal CLK. Be drunk. In other words, the processing speed is constant when viewed from the whole process of the asynchronous circuits 420 to 450.

Further, only the control circuit 410 is added to realize this, and the increase in circuit scale is small.
<Fifth embodiment>

FIG. 13 shows a processor 500 according to the fifth embodiment of the present invention. The processor 500 includes a CPU 400 and a peripheral module 510 shown in FIG. The peripheral module 510 is provided in a normal processor such as an A / D converter or a timer, and includes a flip-flop (FF) 512 that stores data. The clock signal CLK is also provided to the peripheral module 510.

Instructions are previously written in the memory 406 by a memory writer (not shown). The fetch address of the fetch performed by the asynchronous circuit 420 is determined by the value of a register (not shown) in the asynchronous control unit 402.

When the address fetched from the memory 406 by the asynchronous circuit 420 in the fetch phase is a read instruction for the peripheral module 510, the arithmetic circuit 444 in the asynchronous circuit 440 in the execution phase uses the data module DAR as the access target peripheral module 510. Output to. In response to this, the read data RD is output from the peripheral module 510. In the memory access phase, the read data RD is written into the FF 455 by the arithmetic circuit 454 of the asynchronous circuit 450.

Further, when the address fetched from the memory 406 by the asynchronous circuit 420 in the fetch phase is a write instruction for the peripheral module 510, the arithmetic circuit 444 in the asynchronous circuit 440 receives the data address DAR and the write data WD in the execution phase. Output to the peripheral module 510. Then, the write data WD is written to the FF 512 of the peripheral module 510 at the rising timing of the clock signal CLK.

The processor 500 according to the fifth embodiment applies the CPU 400 according to the fourth embodiment, and can obtain all the effects described in the case of the CPU 400.
<Sixth Embodiment>

FIG. 14 shows a semiconductor device 600 according to the sixth embodiment of the present invention. The semiconductor device 600 further includes a second pulse signal generation circuit 610, and the control circuit 110 receives the second pulse signal PLS2 from the second pulse signal generation circuit 610 instead of the clock signal CLK. Except for this, the semiconductor device 100 is the same as the semiconductor device 100 shown in FIG. Therefore, for the semiconductor device 600, only the second pulse signal generation circuit 610 will be described in detail.

The second pulse signal generation circuit 610 receives the clock signal CLK, the start signal start, and the permission signal al, and outputs the second pulse signal PLS2 to the control circuit 110.

The second pulse signal generation circuit 610 counts the number of times the permission signal al rises, and outputs the start signal start as the second pulse signal PLS2 when the counted number N is equal to or less than the set number N. On the other hand, when the counted number reaches the number N, the clock signal CLK is output as the second pulse signal PLS2, and the counted number is returned to zero.

Specifically, as shown in FIG. 14, the second pulse signal generation circuit 610 includes a number setting register 612, a counter 614, a comparator 616, and a selector 618.

The number setting register 612 is for setting the number N.
The counter 614 is a down counter and repeatedly counts down from the number N set to 0 in the number setting register 612. The counter 614 counts down by one every time the permission signal al becomes a rising edge, and starts counting from the number N again when the count value reaches zero.

The comparator 616 compares the count value of the counter 614 with 0, and outputs a comparison result indicating whether the count value is 0 to the selector 618.

The selector 618 selects the start signal start when the count value of the counter 614 is other than 0, and selects the clock signal CLK when the count value becomes 0, in accordance with the comparison result from the comparator 616. The pulse signal PLS2 is output to the control circuit 110.

The control circuit 110 raises the permission signal al when both the second pulse signal PLS2 and the start signal start rise, and allows the permission signal al when both the second pulse signal PLS2 and the start signal start fall. And the state of the permission signal al is maintained at other times.

FIG. 15 shows an example of a timing chart showing transition of each signal in the semiconductor device 600. In this example, it is assumed that the number of times N set in the number-of-times setting register 612 is 3.

As shown in the figure, since the count value of the counter 614 is 0 as the initial value at the timing t1, the second pulse signal PLS2 rises in response to the rise of the clock signal CLK.

At this time, since the start signal start also rises, the control circuit 110 raises the permission signal al. The count value of the counter 614 becomes 3 in response to the rise of the permission signal al.

Thereafter, the second pulse signal PLS2 is the same as the start signal start until timing t5 when the count value of the counter 614 becomes 0.

That is, among the three processes started by the asynchronous circuit 150 by the timing t5, the first start timing is synchronized with the clock signal CLK, while the second and third start timings are the clocks. The asynchronous circuit 150 is not synchronized with the signal CLK, and performs a normal asynchronous operation in which the control circuit 110 is not provided. Hereinafter, the case where the start timing is synchronized with the clock signal CLK is referred to as “synchronous mode”, and the case where the start timing is not synchronized with the clock signal CLK is referred to as “asynchronous mode”.

The count value of the counter 614 becomes 0 in response to the rise of the permission signal al at the timing t5. Therefore, the second pulse signal PLS2 changes to the clock signal CLK. Therefore, when the clock signal CLK falls at the timing t6, the second pulse signal PLS2 falls although the start signal start has not yet fallen.

Thereby, the start timing of the fourth process performed by the asynchronous circuit 150 is synchronized with the rising edge of the clock signal CLK and becomes timing t9.

After that, similarly, in each of the three processes by the asynchronous circuit 150, the first start timing is synchronized with the rising edge of the clock signal CLK, and the second and third start timings are not synchronized with the clock signal CLK. It is like that.

The processing speed by the asynchronous circuit can be made constant by synchronizing the start timing of the processing by the asynchronous circuit with the clock signal CLK, but there is a problem that the processing speed becomes slow. In addition, there is a possibility that the asynchronous circuit is not required to have an accuracy enough to synchronize the start timing of each process with the clock signal CLK depending on the application.

In the semiconductor device 600 of this embodiment, by providing the second pulse signal generation circuit 610, the processing speed adjustment accuracy of the asynchronous circuit 150 is increased by changing the number N set in the number setting register 612. It can be changed.

For example, when applying to a system in which processing speed is important, by setting the number of times N to a large value, the proportion of the asynchronous mode is increased, and in applying to a system in which processing speed stability is important. The ratio of the synchronous mode may be increased by setting the number N to a small value.

In the semiconductor device 600, the asynchronous circuit 150 can be operated only in the synchronous mode or only in the asynchronous mode.

When the asynchronous circuit 150 is operated only in the synchronous mode, 0 may be set in the number setting register 612 as the number N.

When the asynchronous circuit 150 is operated only in the asynchronous mode, the number setting register 612 is set to 1 or more times N, and the enable signal EN for controlling the counter 614 is set to 0 so that the counter 614 does not count down. What should I do? In this case, since the count value of the counter 614 is always N which is 1 or more, the asynchronous circuit 150 always operates in the asynchronous mode.
<Seventh embodiment>

In each of the first to fifth embodiments described above, the cycle of the clock signal CLK input to the control circuit is greater than or equal to the maximum value Tmax, and the start signal start is always in an invalid state (falling down). Stand up when Therefore, when the clock signal CLK rises, the start signal start has already risen, and the control circuit raises the permission signal al every time the clock signal CLK rises. As a result, the processing time of the process by the asynchronous circuit is made constant. The same applies to the sixth embodiment when the asynchronous circuit 150 is operated only in the synchronous mode.

However, for example, when the period of the clock signal CLK cannot be set to the maximum value Tmax or more due to constraints such as consistency with other functional blocks of the system, the time from the start of the process to the next start The period of the clock signal CLK, that is, one cycle length is exceeded. The problem in this case will be described with reference to the timing chart of FIG. The semiconductor device 100 according to the first embodiment is taken as an example.

As shown in FIG. 16, when the clock signal CLK rises at the timing t4, the start signal start has not yet risen, so that the permission signal al also falls. Thereafter, the start signal start rises at timing t5, and the permission signal al rises accordingly. The length between the start timing (timing t2) of the first process by the asynchronous circuit 150 and the start timing (timing t6) of the second process is T1.

Thereafter, the start signal start rises at timing t9 in response to the fall of the permission signal al at timing t7. At this time, since the clock signal CLK has already risen, the permission signal al also rises at timing t10. The length between the start timing (timing t6) of the second process by the asynchronous circuit 150 and the start timing (timing t10) of the third process is T2.

Subsequently, the start signal start falls at a timing t11 after the rise of the clock signal CLK, and rises at a timing t13 after the fall of the clock signal CLK. However, the permission signal al rises at timing t14 after the rising of the clock signal CLK again. The length between the start timing (timing t10) of the third process by the asynchronous circuit 150 and the start timing (timing t14) of the fourth process is T3.

As can be seen from FIG. 16, although the asynchronous circuit 150 can operate even in this case, there is a problem that the processing speed of the asynchronous circuit 150 varies and is not stable.

The inventor of the present application has established a method for solving this problem. This technique will be described using a semiconductor device 700 according to the seventh embodiment shown in FIG.

The semiconductor device 700 further includes a first pulse signal generation circuit 710, and the control circuit 110 receives the first pulse signal PLS1 from the first pulse signal generation circuit 710 instead of the clock signal CLK. Except for this, the semiconductor device 100 is the same as the semiconductor device 100 shown in FIG. Therefore, for the semiconductor device 700, only the first pulse signal generation circuit 710 will be described in detail.

The first pulse signal generation circuit 710 receives the clock signal CLK and the start signal start, and outputs the first pulse signal PLS1 to the control circuit 110. The first pulse signal generation circuit 710 includes a flip-flop (FF) 712, a delay circuit 714, and an AND element 716.

The FF 712 latches the start signal start at the rising edge of the clock signal CLK and continues to output the latched signal to the AND element 716 until the next rising edge of the clock signal CLK. The signal output from the FF 712 is hereinafter referred to as “signal S1”.

The delay circuit 714 delays the clock signal CLK and outputs it to the AND element 716. The delay circuit 714 has a delay amount equal to or longer than the delay time from the start of latching by the FF 712 to the output of the latched signal. The signal output from the delay circuit 714 is hereinafter referred to as “delayed clock signal S2”.

The AND element 716 obtains a logical product of the signal S1 and the delayed clock signal S2, and outputs the logical product to the control circuit 110. This logical product is the first pulse signal PLS1.

Note that the control circuit 110 raises the permission signal al when both the first pulse signal PLS1 and the start signal start rise, and permits when both the first pulse signal PLS1 and the start signal start fall. The signal al is lowered, and the permission signal al is maintained at other times.

FIG. 18 is an example of a timing chart showing the transition of each signal in the semiconductor device 700.

As shown in FIG. 18, since the start signal start falls when the clock signal CLK rises at timing t5, the signal S1 output from the FF 712 falls.

Therefore, when the start signal start rises at timing t6, the clock signal CLK rises, but the signal S1 falls, so the first pulse signal PLS1 does not rise. Therefore, the permission signal al does not rise.

Thereafter, when the clock signal CLK rises again at the timing t7, the signal S1 and the first pulse signal PLS1 rise because the start signal start rises. In response to this, the permission signal al rises at timing t8.

The length T1 between the start timing (timing t2) of the first process by the asynchronous circuit 150 and the start timing (timing t8) of the second process is twice the cycle T of the clock signal CLK.

Similarly, since the start signal start falls when the clock signal CLK rises at the timing t9, the signal S1 output from the FF 712 falls.

Therefore, when the start signal start rises at timing t10, the clock signal CLK rises, but the signal S1 falls, so the first pulse signal PLS1 does not rise. Therefore, the permission signal al does not rise.

Then, when the clock signal CLK rises again at the timing t11, the signal S1 and the first pulse signal PLS1 rise because the start signal start rises. In response to this, the permission signal al rises at timing t12.

The length T2 between the start timing (timing t8) of the second process by the asynchronous circuit 150 and the start timing (timing t12) of the third process is also twice the cycle T of the clock signal CLK.

FIG. 19 is another example of a timing chart showing the transition of each signal in the semiconductor device 700.

As shown in FIG. 19, when the clock signal CLK rises at timing t4, the start signal start is still rising, so the signal S1 output from the FF 712 remains rising. Therefore, the first pulse signal PLS1 rises. Note that the permission signal al remains rising.

Thereafter, the start signal start falls at timing t5. However, since both the clock signal CLK and the signal S1 remain rising, the first pulse signal PLS1 to the permission signal al also remain rising.

When the clock signal CLK falls at the timing t6, the signal S1 remains rising, but the first pulse signal PLS1 falls. In response to this, the permission signal al also falls at timing t7.

When the start signal start rises at timing t8, the clock signal CLK is still falling, so the first pulse signal PLS1 does not rise. Therefore, the permission signal al does not rise.

Thereafter, when the clock signal CLK rises again at timing t9, the first pulse signal PLS1 rises because the start signal start rises. In response to this, the permission signal al rises at timing t10.

The length T1 between the start timing (timing t2) of the first process by the asynchronous circuit 150 and the start timing (timing t10) of the second process is twice the period T of the clock signal CLK.

Similarly, when the clock signal CLK rises at timing t12, the signal S1 output from the FF 712 remains raised because the start signal start is still raised, and the first pulse signal PLS1 rises. .

Thereafter, the start signal start falls at the timing t13, but since both the clock signal CLK and the signal S1 remain rising, the first pulse signal PLS1 to the permission signal al also remain rising.

When the clock signal CLK falls at the timing t14, the signal S1 remains rising, but the first pulse signal PLS1 falls. In response to this, the permission signal al also falls at timing t15.

When the start signal start rises at timing t16, the clock signal CLK is still falling, so the first pulse signal PLS1 does not rise. Therefore, the permission signal al does not rise.

After that, when the clock signal CLK rises again at timing t17, the first pulse signal PLS1 rises because the start signal start rises. In response to this, the permission signal al rises at timing t18.

The length T2 between the start timing (timing t10) of the second process by the asynchronous circuit 150 and the start timing (timing t18) of the third process is also twice the cycle T of the clock signal CLK.

That is, the semiconductor device 700 according to the present embodiment generates the first pulse signal PLS1 by the first pulse signal generation circuit 710 and supplies it to the control circuit 110 instead of the clock signal CLK. The processing start timing is synchronized with the next rising edge of the clock signal CLK. Therefore, the processing speed of the asynchronous circuit can be made constant even when the cycle of the clock signal CLK is smaller than the maximum value Tmax.

This method can also be applied when mixing synchronous mode and asynchronous mode. This will be described in an eighth embodiment.

<Eighth Embodiment>
FIG. 20 shows a semiconductor device 800 according to the eighth embodiment of the present invention. The semiconductor device 800 is a combination of the semiconductor device 600 and the semiconductor device 700, and is provided with a first pulse signal generation circuit 710 and a second pulse signal generation circuit 610 with respect to the semiconductor device 100.

The first pulse signal generation circuit 710 receives the clock signal CLK and the start signal start, generates the first pulse signal PLS1, and outputs it to the second pulse signal generation circuit 610.

The second pulse signal generation circuit 610 receives the first pulse signal PLS1, the start signal start, and the permission signal al, generates the second pulse signal PLS2, and outputs it to the control circuit 110.

The first pulse signal generation circuit 710 and the second pulse signal generation circuit 610 are the same as those described for the semiconductor device 600 and the semiconductor device 700.

That is, according to the semiconductor device 800 of the present embodiment, the asynchronous circuit 150 can be operated while switching between the synchronous mode and the asynchronous mode, and the period of the clock signal CLK is maximum when operating in the synchronous mode. Even when the value is smaller than the value Tmax, the processing speed of the asynchronous circuit can be made constant.

In the semiconductor device 600 shown in FIG. 14, when the asynchronous circuit is operated in the asynchronous mode, the processing speed of the asynchronous circuit may vary even when the cycle of the clock signal CLK is larger than the maximum value Tmax. is there. For example, in the example of the timing chart shown in FIG. 15, when the fourth rise timing (t8) of the start signal start falls within the third High period (timing t4 to timing t6) of the clock signal CLK, the asynchronous circuit Operates in the fifth asynchronous mode, and does not switch to the synchronous mode when the clock signal CLK rises at timing t9.

According to the semiconductor device 800 of the present embodiment, this problem does not occur and the processing speed of the asynchronous circuit can be made constant.

The present invention has been described above based on the embodiments. The embodiment is an exemplification, and various changes, increases / decreases, and combinations may be made to the embodiment described above without departing from the gist of the present invention. It will be understood by those skilled in the art that modifications in which these changes, increases / decreases, and combinations are also within the scope of the present invention.

For example, only the example in which the first pulse signal generation circuit 710 and the second pulse signal generation circuit 610 are provided for the semiconductor device 100 has been described. However, the first pulse signal generation circuit 710 and the second pulse signal generation circuit 610 have been described. The generation circuit 610 may be provided for a control circuit in any of the semiconductor device 200, the semiconductor device 300, the CPU 400, and the processor 500. Of course, the effects described above can be obtained by providing the first pulse signal generation circuit 710 and the second pulse signal generation circuit 610 in the devices according to these embodiments.

Further, for example, in each of the above-described embodiments, the effective edge of the clock signal CLK is the rising edge, but the falling edge may be the effective edge. In this case, for example, an inverter that inverts the clock signal CLK or the first pulse signal PLS1 may be further provided in the control circuit (control circuit 110, control circuit 210, control circuit 310, control circuit 410).

This application claims priority based on Japanese Patent Application No. 2011-051677 filed on Mar. 9, 2011, the entire disclosure of which is incorporated herein.

The present invention can be applied to control of the processing speed of an asynchronous circuit provided in a semiconductor device.

DESCRIPTION OF SYMBOLS 10 Processing speed constant apparatus 12 Asynchronous circuit 14 Period fluctuation pulse generation part 20 Period constant pulse generation part 30 Pulse measurement part 40 Voltage regulator 50 Voltage control signal generation part 52 Memory 54 Comparator 60 Operation | movement / processing speed change condition acquisition part 70 Operation / Processing Speed Change Condition Setting Unit 80 Operation / Processing Speed Change Control Unit 100 Semiconductor Device 110 Control Circuit 111 AND Element 112 AND Element 113 AND Element 114 OR Element 120 Inverter 150 Asynchronous Circuit 160 Control Module 161 AND Element 162 Inverter 164 AND Element 165 Inverter 166 Delay element 170 C element 171 AND element 172 AND element 173 AND element 174 OR element 180 Arithmetic circuit 200 Semiconductor device 210 Control circuit 250 Asynchronous circuit 260 Control Joule 261 AND element 262 Inverter 264 AND element 265 Inverter 270 C element 280 Arithmetic circuit 300 Semiconductor device 310 Control circuit 320 Asynchronous circuit 322 Control module 324 Arithmetic circuit 330 Asynchronous circuit 332 Control module 334 Arithmetic circuit 340 Asynchronous circuit 342 Control module 344 arithmetic circuit 400 CPU
402 Asynchronous control unit 404 Data path unit 406 Memory 410 Control circuit 420 Asynchronous circuit 422 Fetch control module 424 FF 430 Asynchronous circuit 432 Decode control module 434 Arithmetic circuit 435 FF 440 Asynchronous circuit 442 Execution control module 444 Arithmetic circuit 445 FF 450 Asynchronous circuit 452 Memory access control module 454 Arithmetic circuit 455 FF 460 Asynchronous circuit 462 Write-back control module 464 Arithmetic circuit 465 FF 500 Processor 510 Peripheral module 512 FF
600 Semiconductor device 610 Second pulse signal generation circuit 612 Count setting register 614 Counter 616 Comparator 618 Selector 700 Semiconductor device 710 First pulse signal generation circuit 712 FF 714 Delay circuit 716 AND element 800 Semiconductor device al Permission signal CLK Clock signal out completion signal start start signal RD read data WD write data DAR data address PLS1 first pulse signal PLS2 second pulse signal EN enable signal

Claims

If one and the other of the rising and falling states of the signal are valid and invalid, respectively,
A first asynchronous circuit that repeatedly executes a predetermined process, wherein the predetermined process is started when a permission signal is in the valid state, and a process completion signal is sent to the valid state when the predetermined process is completed; And the first asynchronous circuit that sets the processing completion signal to the invalid state when the permission signal is in the invalid state;
A processing start signal that is an inverted signal of the processing completion signal, and a control circuit that receives a clock signal and outputs the permission signal to the first asynchronous circuit;
The control circuit includes:
When both the processing start signal and the clock signal are in the valid state, the permission signal is in the valid state,
When both the processing start signal and the clock signal are in the invalid state, the permission signal is in the invalid state,
A semiconductor device characterized by maintaining the state of the permission signal at other times.
The effective state is a standing state,
The control circuit includes:
A first AND element to which the clock signal and the permission signal are input;
A second AND element to which the clock signal and the processing start signal are input;
A third AND element to which the permission signal and the processing start signal are input;
The semiconductor device according to claim 1, further comprising: an OR element that outputs a logical sum of logical products output by the three AND elements as the permission signal.
An inverter,
The first asynchronous circuit is a top stage of a plurality of asynchronous circuits connected in stages,
The plurality of asynchronous circuits repeatedly execute a predetermined process, execute a plurality of processes included in the process in one execution of the process, and output a process completion signal,
Each asynchronous circuit after the second stage starts its own processing when the processing completion signal output from the previous asynchronous circuit is in the valid state, and outputs itself when the processing is completed. The completion signal is set to the valid state, and when the process completion signal output by the asynchronous circuit in the previous stage is set to the invalid state, the process completion signal output by itself is set to the invalid state,
The inverter receives the processing completion signal output from the lowest asynchronous circuit among the plurality of asynchronous circuits, and outputs an inverted signal of the processing completion signal as the processing start signal to the control circuit. The semiconductor device according to claim 1 or 2.
An asynchronous CPU (Central Processing Unit) having an asynchronous control unit and a data path unit;
The asynchronous control unit includes:
The control circuit, the inverter, a fetch control module, a decode control module, an execution control module, a memory access control module, and a write back control module,
The data path part is
Memory,
A first flip-flop;
A second arithmetic circuit and a second flip-flop;
A third arithmetic circuit and a third flip-flop;
A fourth arithmetic circuit and a fourth flip-flop;
A fifth arithmetic circuit and a fifth flip-flop;
The fetch control module and the first flip-flop constitute an uppermost asynchronous circuit of the plurality of asynchronous circuits and latch an instruction from the memory;
The decode control module, the second arithmetic circuit, and the second flip-flop constitute a second asynchronous circuit of the plurality of asynchronous circuits, and the uppermost asynchronous circuit is latched. Decodes instructions,
The execution control module, the third arithmetic circuit, and the third flip-flop constitute a third stage asynchronous circuit of the plurality of asynchronous circuits, and the second stage asynchronous circuit decodes Executed instructions,
The memory access control module, the fourth arithmetic circuit, and the fourth flip-flop constitute a fourth stage asynchronous circuit of the plurality of asynchronous circuits, and are based on the third stage asynchronous circuit. Access to the access target accompanying the execution of the instruction,
The write-back control module, the fifth arithmetic circuit, and the fifth flip-flop are the lowest-stage asynchronous circuits of the plurality of asynchronous circuits, and perform write-back upon completion of instruction execution. The semiconductor device according to claim 3, wherein the semiconductor device is a device.
An inverter,
The first asynchronous circuit is the second and subsequent stages of a plurality of asynchronous circuits connected in stages,
The plurality of asynchronous circuits repeatedly execute a predetermined process, execute a plurality of processes included in the process in one execution of the process, and output a process completion signal,
The inverter receives the processing completion signal output from the lowest asynchronous circuit among the plurality of asynchronous circuits, and outputs an inverted signal of the processing completion signal to the uppermost asynchronous circuit,
The uppermost asynchronous circuit starts its own processing when the inverted signal is in the valid state, sets the processing completion signal output by itself upon completion of the processing to the valid state, and When the signal is in the invalid state, the processing completion signal output by itself is in the invalid state,
The processing completion signal output from the asynchronous circuit preceding the first asynchronous circuit is input to the control circuit as the processing start signal,
Each asynchronous circuit other than the uppermost asynchronous circuit and the first asynchronous circuit starts its own processing when the processing completion signal output from the previous asynchronous circuit is in the valid state. The processing completion signal output by itself upon completion of the processing is set in the valid state, and the processing completion signal output by itself when the processing completion signal output by the asynchronous circuit in the previous stage is in the invalid state. The semiconductor device according to claim 1, wherein the invalid state is set.
A first pulse signal generation circuit that receives the clock signal and the processing start signal and generates a first pulse signal;
The control circuit receives the first pulse signal instead of the clock signal,
The first pulse signal generation circuit includes:
A flip-flop that latches the processing start signal each time the clock signal becomes a valid edge that is the head of the valid state and continues to output the latched signal until the clock signal next becomes the valid edge;
6. The AND circuit according to claim 2, further comprising: an AND circuit that obtains a logical product of the clock signal and a signal latched by the flip-flop and outputs the logical product as the first pulse signal. The semiconductor device described.
The first pulse signal generation circuit further includes a delay circuit having a delay amount equal to or longer than a delay time from the start of latching by the flip-flop until the output of the latched signal.
The semiconductor device according to claim 6, wherein the clock signal is input to the logical product circuit via the delay circuit.
A second pulse signal generation circuit configured to receive the first pulse signal and the processing start signal and generate a second pulse signal;
The control circuit receives the second pulse signal instead of the first pulse signal,
The second pulse signal generation circuit includes:
Count the number of times the permission signal is in the valid state,
Outputting the processing start signal as the second pulse signal when the counted number is equal to or less than a set number of times N;
8. When the counted number reaches the number N, the first pulse signal is output as the second pulse signal, and the counted number is returned to zero. Semiconductor device.
The second pulse signal generation circuit includes:
A frequency setting register for setting the frequency N;
A counter that repeatedly counts down from the number of times N to 0 set in the number-of-times setting register, and counts down by one every time the permission signal becomes a valid edge that is the head of the valid state;
A comparator for comparing the count value of the counter with 0;
The first pulse signal and the processing start signal are input, and the processing start signal is set to 0 when the count value of the counter is other than 0 according to the comparison result of the comparator. The semiconductor device according to claim 8, further comprising a selector that selects the first pulse signal and outputs the second pulse signal as the second pulse signal.
10. The semiconductor device according to claim 9, wherein the number setting register can set 0 as the number N.
11. The semiconductor device according to claim 9, wherein, when enabled, the counter outputs the number N set in the number setting register as a count value to the comparator.