CN210958326U

CN210958326U - High-reliability self-recoverable latch structure

Info

Publication number: CN210958326U
Application number: CN201921987985.6U
Authority: CN
Inventors: 白雨鑫; 陈鑫; 张颖; 刘小雨; 高翔; 毛志明; 单永欣; 马丽萍; 姚嘉祺; 陈凯; 施聿哲; 金铮斐; 李森; 葛明慧; 张骁煜
Original assignee: Nanjing University of Aeronautics and Astronautics
Current assignee: Nanjing University of Aeronautics and Astronautics
Priority date: 2019-11-18
Filing date: 2019-11-18
Publication date: 2020-07-07
Anticipated expiration: 2029-11-18

Abstract

The utility model relates to a high reliability latch structure that can self-resuming has proposed a neotype pulse latch unit and a neotype connected mode of the reverse phase unit that self-resumes, has structurally realized the reinforcement to interior node and outside output node, has realized the immunologic function to the single particle upset. The latch adopts a clock control technology, a high-speed path and a small number of transistors, thereby reducing the expense of the latch and improving the circuit performance. The utility model is suitable for an integrated circuit and system of high reliability can be applied to the reliability and the higher field of comprehensive overhead requirement of latch.

Description

High-reliability self-recoverable latch structure

Technical Field

The utility model relates to an anti single event upset of integrated circuit consolidates technical field, especially relates to a high reliability latch structure that can self-resuming.

Background

Digital integrated circuits are widely used in the fields of aerospace and the like. With the rapid development of semiconductor technology, the characteristic size of transistors is continuously reduced, the working voltage of an integrated circuit is continuously reduced, the critical charge of the circuit node which is overturned is also reduced, and a digital integrated circuit is more and more easily influenced by space radiation to generate a phenomenon of single event upset.

The single event upset refers to a phenomenon that a logic state of a logic value changed from 0 to 1 or from 1 to 0 is inverted when a certain node in a sensitive area of a semiconductor device is interfered, and is a common transient error. In the event of such a transient error, the system function may be disturbed, and in the severe case, an accident may be caused. Therefore, it is important to improve the single event upset tolerance of sensitive nodes in semiconductor devices. The latch is used as a basic sequential circuit unit with a storage structure and works in a space radiation environment for a long time, so that the reinforcement design of carrying out necessary single event upset on the latch has important significance for improving the reliability of an integrated circuit.

At present, the single event upset resistance reinforcement design aiming at the latch has the main problems that: for the output end node of the latch, when the single event upset occurs, the output end of the latch is kept as an error logic value, and the self-recovery of the single event upset cannot be realized, that is, all the nodes cannot be ensured to be capable of on-line self-recovery, or although the complete tolerance of the single event upset can be realized, the latch has large area overhead and large power consumption and has certain transmission delay.

SUMMERY OF THE UTILITY MODEL

The utility model aims to solve the technical problem that to the defect that involves in the background art, provide a latch structure that high reliability can be from recovering.

The utility model discloses a solve above-mentioned technical problem and adopt following technical scheme:

a high-reliability self-recoverable latch structure comprises a first transmission gate, a second transmission gate, a first pulse latch unit, a second pulse latch unit and a self-recovering inverting unit;

the signal input end of the first transmission gate is connected with the signal input end of the second transmission gate, and the two gate control ends of the first transmission gate and the second transmission gate are respectively connected with an external clock signal and an external reverse clock signal;

the first pulse latch unit and the second pulse latch unit respectively comprise a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second PMOS tube, a second NMOS tube and a gate control unit; the gate control unit comprises a first input end, a second input end and an inverted output end, wherein the second input end is used for inputting an external inverted clock signal, and the inverted output end is used for inverting and outputting a signal input by the first signal input end;

the source electrode of the first NMOS tube is respectively connected with the source electrode of the second PMOS tube, the first input end of the gate control unit, the grid electrode of the first NMOS tube and the grid electrode of the second PMOS tube, and the drain electrode of the first NMOS tube is connected with the drain electrode of the first PMOS tube;

the source electrode of the first PMOS tube is connected with an external power supply, and the grid electrode of the first PMOS tube is respectively connected with the grid electrode of the second NMOS tube and the inverted output end of the gate unit;

the drain electrode of the second PMOS tube is connected with the source electrode of the second NMOS tube; the source electrode of the second NMOS tube is grounded;

the source electrode of a first NMOS tube in the first pulse latch unit is connected with the signal output end of the first transmission gate, and the source electrode of a first NMOS tube in the second pulse latch unit is connected with the signal output end of the second transmission gate;

the self-recovery reverse phase unit comprises a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a fifth NMOS tube, a sixth NMOS tube and a seventh NMOS tube;

the source electrode of the fifth PMOS tube is connected with an external power supply, the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, and the grid electrode of the fifth PMOS tube is respectively connected with the drain electrode of the seventh PMOS tube, the drain electrode of the fifth NMOS tube and the grid electrode of the seventh NMOS tube;

the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fifth NMOS tube, and the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube;

the grid electrode of the sixth NMOS tube is connected with the grid electrode of the seventh PMOS tube, the drain electrode of the sixth NMOS tube is connected with the source electrode of the fifth NMOS tube, and the source electrode of the sixth NMOS tube is connected with the drain electrode of the seventh NMOS tube;

the source electrode of the seventh NMOS tube is grounded;

the grid electrode of the sixth PMOS tube is connected with the first input end of the gate control unit in the first pulse latch unit, and the grid electrode of the seventh PMOS tube is connected with the first input end of the gate control unit in the second pulse latch unit.

The utility model adopts the above technical scheme to compare with prior art, have following technological effect:

the utility model provides a neotype pulse latch inverting unit and a neotype from the connected mode of recovering inverting unit have structurally realized the reinforcement to interior node and output node, have realized the immunologic function to the single event upset. The latch structure adopts two transmission gates, two novel pulse latch phase-inverting units and two novel self-recovery phase-inverting unit structures, effectively ensures the reinforcement efficiency of single event upset, and simultaneously adopts a clock control technology, a high-speed path and a small number of transistors, thereby reducing the area and power consumption overhead of the latch.

Drawings

FIG. 1 is a schematic circuit diagram of a high reliability self-recoverable latch according to the present invention;

fig. 2 is a schematic circuit diagram of a pulse latch unit according to the present invention;

fig. 3 is a schematic circuit diagram of a self-recovery inverter unit according to the present invention;

fig. 4 is a truth table of the self-recovery inverting unit according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

The present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, components are exaggerated for clarity.

As shown in fig. 1, the present invention discloses a latch structure with high reliability and self-recovery, which comprises a first transmission gate, a second transmission gate, a first pulse latch unit, a second pulse latch unit and a self-recovery inverting unit; inside it, there are six nodes D1, D2, D3, D4, D5, and D6, one external data input node D, and one external data output node Q. The signal input end of the first transmission gate is connected with the signal input end of the second transmission gate, and the two gate control ends of the first transmission gate and the second transmission gate are respectively connected with an external clock signal and an external reverse clock signal.

As shown in fig. 2, each of the first pulse latch unit and the second pulse latch unit includes a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, a second NMOS transistor, and a gate control unit; the gate control unit has the function of inverting and outputting an input signal; the pulse latch unit circuit comprises a signal input end I, an inverted clock signal input end CLKB and a signal output end OUT; the source electrode of the first NMOS tube is connected with the source electrode of the second PMOS tube, the connection point is the signal input end of the pulse latch unit, the inverted clock signal input end CLKB of the gate control unit is the inverted clock signal input end CLKB of the pulse latch unit, the source electrode of the first NMOS tube, the source electrode of the second PMOS tube, the grid electrode of the first NMOS tube and the grid electrode of the second PMOS tube are connected with the signal input end of the gate control unit, and the connection point is the signal output end of the pulse latch unit; the source electrode of the first PMOS tube is connected with a power supply VDD, the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the source electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the signal output end of the gate control unit is connected with the grid electrode of the first PMOS tube and the grid electrode of the second NMOS tube.

The source electrode of a first NMOS tube in the first pulse latch unit is connected with the signal output end of the first transmission gate, and the source electrode of a first NMOS tube in the second pulse latch unit is connected with the signal output end of the second transmission gate.

As shown in fig. 3, the self-recovery inverter unit circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; the self-recovery latch unit circuit comprises a first signal input end I1, a second signal input end I2 and a signal output end OUT; the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fifth NMOS tube, the connection point is the first signal input end I1 of the self-recovery phase reversal unit, the grid electrode of the seventh PMOS tube is connected with the grid electrode of the sixth NMOS tube, the connection point is the second signal input end I2 of the self-recovery phase reversal unit, the grid electrode of the fifth PMOS tube is connected with the grid electrode of the seventh NMOS tube, and the connection point is the signal output end OUT of the self-recovery phase reversal unit; the source electrode of the fifth PMOS tube is connected with a power supply VDD, the drain electrode of the fifth PMOS tube is connected with the source electrode of the sixth PMOS tube, the drain electrode of the sixth PMOS tube is connected with the source electrode of the seventh PMOS tube, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is connected with the drain electrode of the sixth NMOS tube, the source electrode of the sixth NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the source electrode of the seventh NMOS tube is grounded.

The truth table of the self-recovery inverting unit of the present invention is shown in fig. 4, and it can be known from the truth table that when the logic values of the first signal input terminal I1 and the second signal input terminal I2 are the same, the signal output terminal OUT will output the logic value opposite to the first signal input terminal OUT; when the logic values of the first signal input terminal I1 and the second signal input terminal I2 are different, the signal output terminal OUT will enter a hold state, outputting the logic value in the previous state.

The working principle of the latch capable of self-recovering in resisting single event upset provided by the present invention is explained below, and the specific working principle is as follows:

when the clock signal CLK is at a high level and the inverted clock signal CLKB is at a low level, the latch is in a transparent mode, and at this time, the first transmission gate, the second transmission gate, the gate control unit of the first pulse latch unit, and the gate control unit of the second pulse latch unit are all in a conducting state, and the node D is divided into two nodes: d5 and D6, the signal input by the D port of the data input end of the latch is directly transmitted to the Q port of the signal output end through a high-speed path, and all input and output signals of the first pulse latch unit, the second pulse latch unit and the self-recovery inverting unit are known; propagation delay is reduced through a high-speed path, and power consumption overhead can be reduced by adopting a clock control technology.

When the clock signal CLK is at a low level and the inverted clock signal CLKB is at a high level, the latch is in a latch mode, at the moment, the first transmission gate, the second transmission gate, the gate control unit of the first pulse latch unit and the gate control unit of the second pulse latch unit are all in a closed state, at the moment, the pulse latch unit realizes the latch function of data, d5 and d6 are respectively latched by the first pulse latch unit and the second pulse latch unit, all internal nodes are separated from each other, and when any one node is subjected to single event upset, the node can be isolated without influencing output, so that the logic correctness is ensured.

The following explains the principle that the latch proposed by the present invention can self-recover against single event upset, specifically as follows:

in the proposed circuit, all sensitive nodes which are likely to have single event upset are: d1, d2, d3, d4, d5, d6 and Q;

(1) when a single event upset occurs at the node d1 or the node d2, the d5 enters a high impedance state and keeps the previous logic value, so that the output end Q cannot be influenced;

(2) when a single event upset occurs at the node d3 or the node d4, the d6 enters a high impedance state and keeps the previous logic value, so that the output end Q cannot be influenced;

(3) when the node d5 or d6 has single event upset, Q will enter a high impedance state, the previous logic value is kept, and the output end of the latch will not be affected;

(4) when the node Q is subjected to single event upset, the value of the node Q is quickly corrected due to the self feedback characteristics of the fifth PMOS tube and the seventh NMOS tube, and it is emphasized that the feedback mechanism is started only when the output node of the self-recovery inverting unit is interfered, so that the hardware and power consumption expenses for constructing the latch module are further reduced.

To sum up, the utility model provides a but high reliability self-resuming latch's structure has improved the reliability of latch circuit, adopts clock control technique, highway and less quantity's transistor to reduce the area and the consumption expense of latch. The utility model discloses an integrated circuit and system suitable for high reliability, but wide application requires higher field to latch reliability and comprehensive spending.

It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The above-mentioned embodiments further describe the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims

1. A high-reliability self-recoverable latch structure is characterized by comprising a first transmission gate, a second transmission gate, a first pulse latch unit, a second pulse latch unit and a self-recovering inverting unit;

the source electrode of the seventh NMOS tube is grounded;