JPH1174764A - Latch circuit having voltage level conversion function and flip-flop circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of required elements, to reduce power consumption and to accelerate an operation speed by providing a latch circuit with a voltage level conversion function. SOLUTION: When a clock signal CK is high, both transmission gates TG1 and TG2 become conductive. A slave latch circuit SL becomes a circuit which increases a voltage level of an intermediate output signal from a data output terminal Q1 in a master latch circuit ML and makes it pass through as it is when the signal CK is high. That is, since the voltage of the signal is VDD2 when the intermediate output signal from the terminal Q1 is high, the voltage VDD2 is converted into VDD1 that is higher voltage than it and an output data signal OD is outputted as a high signal. On the other hand, since the voltage of the signal is ground when the intermediate output signal of the terminal Q1 is low, the ground potential is just outputted as the signal OD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit and a flip-flop circuit having a voltage level conversion function,
The present invention relates to a latch circuit with a voltage level conversion function and a flip-flop circuit used for an LSI that operates with multiple power supplies.

[0002]

2. Description of the Related Art In order to suppress power consumption, it has been conventionally performed to increase the number of power supplies inside an LSI chip. For example, a combinational logic circuit operating at a normal voltage VDD and a combinational logic circuit operating at a voltage VDDL lower than the normal voltage VDD are provided in one LSI chip. In such an LSI, it is necessary to convert the voltage level between the combinational logic circuit operating at the low voltage VDDL and the combinational logic circuit operating at the normal voltage VDD. That is, it is necessary to provide a voltage level conversion circuit. It is not advisable to disperse such voltage level conversion circuits in various parts of the LSI chip. This is because, when the voltage level conversion circuits are provided in a distributed manner, the power consumption of the voltage level conversion circuit itself is consumed, and the effect of reducing the power consumption due to the internal power supply may be lost. Therefore, it is said that it is advisable to provide the voltage level conversion circuit intensively in the flip-flop portion. Such a flip-flop circuit provided with a voltage level conversion circuit is generally called a flip-flop circuit with a voltage level conversion function.

FIG. 15 is a diagram showing a typical master-slave flip-flop circuit MSF. This FIG.
As can be understood from the above, the master-slave flip-flop circuit MSF includes a master latch circuit ML and a slave latch circuit SL. The master latch circuit ML and the slave latch circuit SL have a function of passing data from the input terminal D and outputting from the output terminal Q when the input from the clock input terminal CLK is high. On the other hand, when the input from the clock input terminal CLK is low, it has a function of retaining data at the time when this input falls to low. Therefore, the signal input to clock input terminal CLK of master latch circuit ML shown in FIG.
Since the signal is K, the master latch circuit ML is in a passing state for passing data when the clock signal CK is low, and is in a holding state for holding data when the clock signal CK is high. On the other hand, since the signal input to the clock input terminal CLK of the slave latch circuit SL is the clock signal CK, the slave latch circuit SL enters a pass state in which data passes when the clock signal CK is high, When the clock signal CK is at a low level, the state is a holding state for holding data. That is, in the master-slave type flip-flop circuit MSF as a whole,
It operates as an edge-triggered flip-flop.

There are flip-flops having a voltage level conversion function obtained by combining a master-slave type flip-flop circuit MSF shown in FIG. 15 with a voltage level conversion circuit, as shown in FIGS. FIG. 16 shows a master-slave flip-flop M
This is a flip-flop circuit having a voltage level conversion function, in which a voltage level conversion circuit VC is provided at a stage preceding the SF. FIG.
Is a flip-flop circuit with a voltage level conversion function provided with a voltage level conversion circuit VC at a stage subsequent to the master-slave flip-flop MSF. FIG. 18 is similar to the flip-flop circuit with the voltage level conversion function of FIG.
A voltage level conversion circuit VC is provided at a subsequent stage. The difference between the flip-flop circuit with the voltage level conversion function shown in FIG.
The point is that an inverted output terminal / Q is provided for the output of L, and the output signal from the inverted output terminal / Q is used in the voltage level conversion circuit VC. Therefore, the voltage level conversion circuit VC shown in FIG. 18 is connected to the input terminal IN1 for inputting a signal from the output terminal Q of the slave latch circuit SL, and also to the inverted output terminal / Q of the slave latch circuit SL. Input terminal I for inputting a signal
N2 are provided.

[0005]

In the flip-flop circuit with a voltage level conversion function as described above, since data holding and voltage level conversion are performed independently, the number of necessary elements increases and the circuit area increases. However, there is a problem that the operating speed is reduced. In addition, since the voltage level conversion circuit VC requires a corresponding amount of power to operate independently, there is a problem that the entire power consumption increases.

In particular, in the flip-flop circuit with a voltage level conversion function shown in FIG. 16, since the flip-flop operation is performed after the conversion of the voltage level, the voltage level conversion circuit VC and the master-slave flip-flop circuit MS
Both F and F need to operate at the normal voltage VDD. Therefore, there is a problem that power consumption is increased. Moreover, since the master-slave flip-flop circuit MSF operates at the normal voltage VDD, there is a problem that the voltage of the clock signal CK cannot be reduced. That is, there has been a problem that the clock signal CK must be operated at the normal voltage VDD instead of the low voltage VDDL.

On the other hand, in the flip-flop with a voltage level conversion function shown in FIGS. 17 and 18, the voltage level is converted after performing the flip-flop operation.
The voltage of the input data signal ID and the clock signal CK can be reduced. That is, the master-slave flip-flop circuit MSF is operated at the low voltage VDDL,
The voltage level conversion circuit VC can be operated at the normal voltage VDD or at the normal voltage VDD and the low voltage VDDL. However, since the entire master-slave flip-flop circuit MSF operates at the low voltage VDDL, there is a problem that the operation speed is reduced.

The present invention has been made in view of these problems, and provides a latch circuit with a voltage level conversion function and a flip-flop circuit that can operate at high speed while suppressing power consumption. The purpose is to: That is, the input data signal ID and the clock signal CK
It is an object of the present invention to provide a latch circuit with a voltage level conversion function and a flip-flop circuit which can operate at high speed while lowering the voltage. In order to achieve the above object, it is an object to provide a latch circuit with a voltage level conversion function and a flip-flop circuit in which the number of necessary elements is reduced and the circuit area is reduced.

[0009]

In order to solve the above problems, a latch circuit with a voltage level conversion function according to the present invention comprises:
Voltage level converting means for converting a voltage level of an input signal and outputting an output signal having a voltage level different from the voltage level of the input signal; and the voltage level converting means according to an input control signal. A mode for switching between two states, a passing state in which the input signal passes and becomes an output signal, and a holding state in which the input signal is held and becomes an output signal when the control signal is switched. And switching means.

Further, the flip-flop circuit with a voltage level conversion function according to the present invention is a master latch circuit to which an input data signal and a control signal are inputted, and which passes the input data signal in response to the control signal. A master latch circuit having two states, a pass state in which an intermediate output signal is generated and a holding state in which the input data signal is switched to an intermediate output signal when the control signal is switched; A slave latch circuit to which an output signal and the control signal are input, wherein, when the master latch circuit is in the holding state, the intermediate output signal is passed to become an output data signal according to the control signal. State, and holds the intermediate output signal when the control signal is switched when the master touch circuit is in the passing state. A slave latch circuit that is in a holding state as an output data signal, converts the voltage level of the intermediate output signal, and outputs the output data signal as a voltage level different from the voltage level of the intermediate output signal. It is characterized by having.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) In a first embodiment of the present invention, a voltage level conversion circuit is incorporated in a slave latch circuit of a master-slave type flip-flop circuit, thereby reducing the number of necessary elements and suppressing power consumption. This is to speed up the operation. This will be described in more detail below.

FIG. 1 is a diagram showing an example of a circuit of a flip-flop with a voltage level conversion function according to a first embodiment of the present invention.

As can be seen from FIG. 1, the flip-flop circuit with a voltage level conversion function of the first embodiment includes a master latch circuit ML and a slave latch circuit SL.

The master latch ML is constituted by a general latch circuit. That is, the input data signal I
A data input terminal D1 for inputting a clock signal D and a clock input terminal CLK for inputting an inverted clock signal / CK.
And a data output terminal Q1 for outputting data, and an inverted data output terminal / Q1 for inverting and outputting the data. The data output signals from the data output terminal Q1 and the inverted data output terminal / Q1 can be regarded as an intermediate output signal to the slave latch circuit SL when viewed from the entire flip-flop.

The master latch circuit ML allows the input data signal ID to pass therethrough when the input from the clock input terminal CLK is high, and turns it into an intermediate output signal when the input from the clock input terminal CLK is low. It has a function of holding the state of the input data signal ID when it goes low and using it as an intermediate output signal. In the present embodiment, since the inverted clock signal / CK is input to the clock input terminal CLK, when the clock signal CK is low, the master latch circuit ML allows the input data signal ID to pass therethrough to pass the intermediate output signal And when the clock signal CK is high, the state is maintained and an intermediate output signal is provided.

The master latch circuit ML has a voltage VDD for operating a slave latch circuit SL described later.
It operates at a voltage VDD2 lower than 1. Further, the clock signal CK is supplied from the ground to the voltage VDD.
2 and the input data signal I
D is configured to oscillate with the width of the voltage VDD4 from the ground. The clock signal CK that oscillates with the width of the voltage VDD2 from the ground is output from the internal clock signal generation circuit 30 that operates at the voltage VDD2. That is, the clock signal CP oscillating with the width of the voltage VDD3 from the ground.
Through the inverters 32 and 34 operating at the voltage VDD2. These voltages VDD3, V3
DD4 is equal to or higher than voltage VDD2. That is, the voltages VDD3, VDD
4 is a voltage equal to or higher than the voltage VDD2. Further, these voltages VDD3 and VDD4 are smaller than the voltage VDD1. The relationship between these voltages is as follows: VDD1> VDD3, VDD4> VDD2. Note that the voltage VDD3 and the voltage VDD4 may be equal or different.

The slave latch circuit SL includes a mode switching section 10 and a voltage level conversion circuit 20. More specifically, the data output terminal Q1 of the master latch circuit ML is connected to the transmission gate TG1
It is connected to the. The inverted data output terminal / Q1 in the master latch circuit ML is connected to the transmission gate TG2. These transmission gates TG1 and TG2 are gate circuits for conducting and blocking the intermediate output signal from the master latch circuit ML in response to the clock signal CK. That is, when the clock signal CK is high, the signal is conducted, and when the clock signal CK is low, the signal is cut off. These transmission gates TG1 and TG2 are controlled by a clock signal CK having an amplitude of the voltage VDD2 and an inverted clock signal / CK similarly to the master latch circuit ML.

The transmission gate TG1 is connected to an n-type MOS transistor nMOS1. The drain D of the n-type MOS transistor nMOS1 is connected to a p-type MOS transistor pMOS1 provided on the upper side in the figure.
Is connected to the drain D. The source S of the p-type MOS transistor pMOS1 is connected to the power supply of the voltage VDD1. This voltage VDD1 is, as described above,
It is higher than the voltage VDD2 used for the master latch circuit ML. On the other hand, the source S of the n-type MOS transistor nMOS1 is connected to the ground.

The transmission gate TG2 is connected to an n-type MOS transistor nMOS2. The drain D of the n-type MOS transistor nMOS2 is connected to a p-type MOS transistor pMOS2 provided on the upper side in the figure.
Is connected to the drain D. The source S of the p-type MOS transistor pMOS2 is connected to the power supply of the voltage VDD1. On the other hand, the source S of the n-type MOS transistor nMOS2 is connected to the ground.

The aforementioned p-type MOS transistor pMOS1
A between the transistor and the n-type MOS transistor nMOS1 is
It is connected to the gate G of the p-type MOS transistor pMOS2. A point B between the p-type MOS transistor pMOS2 and the n-type MOS transistor nMOS2 is expressed by p
It is connected to the gate G of the type MOS transistor pMOS1. Point A and n-type MOS transistor nMOS
1 is an n-type MOS transistor nMOS3
Is connected to the gate G of the n-type MOS transistor nMOS2. The point D between the point B and the n-type MOS transistor nMOS2 is connected to the gate G of the n-type MOS transistor nMOS1 via the n-type MOS transistor nMOS4. These n-type M
The gates G of the OS transistors nMOS3 and nMOS4,
G is connected to an inverted clock signal / CK. Further, the point C is also connected to the inverter INV1, and the output from the inverter INV1 is output from the slave latch circuit SL as the output data signal OD. This output data signal OD
Is an output of the flip-flop circuit with the voltage level conversion function. That is, the inverter I
An output terminal for the output data signal OD is provided before NV1.

Of these elements, transmission gates TG1 and TG2 and n-type MOS transistor n
The mode switching unit 10 is composed of the MOS3 and the nMOS4. Also, an n-type MOS transistor nMOS1,
nMOS2 and p-type MOS transistors pMOS1, pMOS
The voltage level conversion circuit 20 is composed of the MOS2 and the inverter INV1. This voltage level conversion circuit 2
0 operates at the voltage VDD1 as described above.

Next, the operation of the flip-flop circuit with a voltage level conversion function shown in FIG. 1 will be described. First, the independent operation of the slave latch circuit SL will be described. at first,
The case where the clock signal CK is high will be described. When the clock signal CK is high, the transmission gates TG1 and TG2 are both conductive. Also,
Since the inverted clock signal / CK is low, the n-type MOS
The transistors nMOS3 and nMOS4 are both turned off. Therefore, when the clock signal CK is high, the flip-flop circuit with a voltage level conversion function of FIG. 1 is equivalent to the circuit shown in FIG.

As can be seen from FIG. 2, when the clock signal CK is high, the slave latch circuit SL
This is a circuit that raises the voltage level of the intermediate output signal from the data output terminal Q1 in the master latch circuit ML and passes the signal as it is. That is, when the intermediate output signal from the data output terminal Q1 is high, the voltage of this signal is VDD.
2, the voltage VDD2 is converted to a higher voltage VDD1, and the output data signal OD is output as a high signal. On the other hand, when the intermediate output signal of the data output terminal Q1 is low, the voltage of this signal is ground, and this ground potential is output as it is as the output data signal OD. This will be described in more detail below.

Assuming that the intermediate output signal from data output terminal Q1 in master latch circuit ML is low and the intermediate output signal from inverted data output terminal / Q1 is high, n-type MOS transistor nMOS1 is turned off. , N-type MOS transistor nMOS2 is turned on. Since the n-type MOS transistor nMOS2 is on, the voltage at the point B becomes ground. Therefore, the gate G of the p-type MOS transistor pMOS1
Is also ground, and the p-type MOS transistor pMOS1 is turned on. At this time, since the n-type MOS transistor nMOS1 is in the off state, the point A becomes the voltage VDD1. Since this point A becomes the voltage VDD1,
The gate G of the p-type MOS transistor pMOS2 also has the voltage V
DD1 and the p-type MOS transistor pMOS2
Is turned off. Further, since the point C also becomes the voltage VDD1, the output of the inverter INV1 becomes the ground.

On the contrary, the master latch circuit ML
The output from the data output terminal Q1 is high,
Assume that the output from inverted data output terminal / Q1 was low. In this case, the n-type MOS transistor nMOS
1 is turned on, and the n-type MOS transistor nMOS
2 is turned off. This n-type MOS transistor nM
Since the OS1 is in the ON state, the voltage at the point A becomes the ground. Therefore, the voltage of the gate G of the p-type MOS transistor pMOS2 also becomes the ground, and the p-type MOS transistor pMOS2 is turned on. At this time, n-type M
Since the OS transistor nMOS2 is off, the point B becomes the voltage VDD1. Since this point B becomes the voltage VDD1, the gate G of the p-type MOS transistor pMOS1
Also becomes the voltage VDD1, and this p-type MOS transistor p
MOS1 is turned off. Further, since the voltage at the point C also becomes the ground like the point A, the output of the inverter INV1 becomes the voltage VDD1. This voltage VDD1 is
The voltage is higher than the voltage VDD2. This indicates that the voltage VDD1 intermediate output signal output from the master latch circuit ML has been converted to a higher voltage and output.

The above is a description of the independent operation of the slave latch circuit SL when the clock signal CK is high. Next, the operation of the slave latch circuit SL when the clock signal CK is low is described. A single operation will be described.

As can be seen from FIG. 1, the clock signal CK
Is low, the transmission gates TG1, T
G2 is both in the cutoff state. Also, since the inverted clock signal / CK is high, the n-type MOS transistor nM
OS3 and nMOS4 are both turned on. Therefore, the flip-flop circuit with the voltage level conversion function of FIG. 1 when the clock signal CK is low is equivalent to the circuit shown in FIG.

As can be seen from FIG. 3, the slave latch circuit SL is a circuit that holds the output data signal OD when the clock signal CK switches from high to low. That is, when the output data signal OD is high when the clock signal CK is switched to low, this high state is changed to the next clock signal CK.
Hold until goes high. Conversely, if the output data signal OD is low when the clock signal CK is switched to low, the low state is maintained until the next clock signal CK goes high. This will be described in more detail below.

It is assumed that the output data signal OD is in the high state when the clock signal CK switches from high to low. In this case, as can be seen from the above-described operation when the clock signal CK is high, the voltage at the point C is ground, and the voltage of the gate G of the n-type MOS transistor nMOS2 is ground. Therefore, the n-type MOS
The off state of the transistor nMOS2 is maintained as it is. Since the voltage at point A is also ground, the p-type MO
The ON state of the S transistor pMOS2 is maintained as it is. Since the p-type MOS transistor pMOS2 is on and the n-type MOS transistor nMOS2 is off, the voltage VDD1 at the points B and D is also maintained. Since the point B is at the voltage VDD1, the p-type MOS
The gate G of the transistor pMOS1 also has the voltage VDD1, and the off state of the p-type MOS transistor pMOS1 is maintained as it is. Further, since the point D is the voltage VDD1, the ON state of the n-type MOS transistor nMOS1 is maintained as it is. This n-type MOS transistor n
Strictly speaking, the voltage at the gate G of the MOS1 is a potential lower than the voltage VDD1 by the threshold voltage of the n-type MOS transistor nMOS4.
The ON state of the S transistor nMOS1 can be sufficiently maintained. Thus, the ON state of the n-type MOS transistor nMOS1 is maintained, and the p-type MOS transistor pMOS1
Is maintained, the ground voltage at the point C is also maintained as it is. Therefore, the high state of the output data signal OD is maintained as it is.

On the contrary, it is assumed that the output data signal OD is in the low state when the clock signal CK switches from high to low. In this case, as can be seen from the operation when the clock signal CK is high, the point C
Is the voltage VDD1, so that the n-type MOS transistor n
The gate G of the MOS2 becomes the voltage VDD1. Therefore, the ON state of the n-type MOS transistor nMOS2 is maintained as it is. This n-type MOS transistor nMO
Strictly, the voltage of the gate G of S2 is a voltage lower than the voltage VDD1 by the threshold voltage of the n-type MOS transistor nMOS3. Even with this gate voltage, the on-state of the n-type MOS transistor nMOS2 can be sufficiently maintained.
Further, since the point A is also at the voltage VDD1, the p-type MOS transistor pMOS2 is kept in the off state.
Since the p-type MOS transistor pMOS2 is off and the n-type MOS transistor nMOS2 is on, the ground voltages at points B and D are also maintained. Since the voltage at the point B is ground, the voltage of the gate G of the p-type MOS transistor pMOS1 also becomes ground, and the ON state of the p-type MOS transistor pMOS1 is maintained as it is. Since the voltage at the point D is ground, the off state of the n-type MOS transistor nMOS1 is maintained as it is. As described above, the off state of the n-type MOS transistor nMOS1 is maintained and the on-state of the p-type MOS transistor pMOS1 is maintained, so that the voltage VDD1 at the point C is also maintained. Therefore,
The low state of the output data signal OD is maintained as it is.

Up to this point, the independent operation of the slave latch circuit SL has been described. Next, the overall operation of the flip-flop circuit with a voltage level conversion function will be described with reference to FIG. FIG. 4 is a diagram showing time charts at various points in the flip-flop circuit with a voltage level conversion function. FIG. 4A is a time chart of the clock signal CP, which oscillates with the width of the voltage VDD3 from the ground. FIG. 4B is a time chart illustrating an example of the clock signal CK, which oscillates with a width of the voltage VDD2 from the ground. FIG. 4C is a time chart illustrating an example of the input data signal ID.
Amplitude with a width of 4. FIGS. 4D and 4E are time charts showing examples of the intermediate output signal from the data output terminal Q1 and the intermediate output signal from the inverted data output terminal / Q1, and FIGS. 4F and 4G. Are nMOS1 and nMO
5 is a time chart showing an example of the voltage of the gate G with respect to S2, and all of them swing from the ground to the width of the voltage VDD2. FIGS. 4H and 4I are time charts showing examples of the voltages at points B and A, and FIG. 4J is a time chart showing an example of the output data signal OD. It swings with the width of the voltage VDD1 from the ground.

As can be seen from FIGS. 4 and 1, the clock signal CK and the inverted clock signal / CK are input to the transmission gates TG1, TG2 and the clock input terminal CLK of the master latch circuit ML. Further, the inverted clock signal / CK is input to the n-type MOS transistors nMOS3 and nMOS4.

In the state where the clock signal CK is input, as shown in FIG. 4C, at time t1, the data input terminal D1 of the master latch circuit ML is turned on.
It is assumed that the input data signal ID to be input to is switched from low to high. At this time t1, FIG.
Since the clock signal CK is low, the high signal in the input data signal ID is output from the data output terminal Q1 as can be seen from FIG. Also, as can be seen from FIG. 4E, the signal of the row obtained by inverting this signal is supplied to the inverted data output terminal / Q1.
Output from However, as can be seen from FIG.
Since the clock signal CK is still low, the transmission gates TG1 and TG2 are both in the cutoff state. Therefore, as can be seen from FIGS.
The voltage of the gate G of the n-type MOS transistor nMOS1 remains low, and the voltage of the gate G of the n-type MOS transistor nMOS2 remains high.

As can be seen from FIG. 4B, when the clock signal CK switches from low to high at time t2, FIG.
Transmission gates TG1 and TG2 are both conductive. Therefore, as can be seen from FIG. 4F, the potential of the gate G of the n-type MOS transistor nMOS1 becomes high. Also, as can be seen from FIG.
The potential of the gate G of the n-type MOS transistor nMOS2 becomes low. Therefore, as can be seen from FIG.
The potential at point B of the slave latch circuit SL switches from low to high, and as can be seen from FIG. 4 (i), the potential at point A of the slave latch circuit SL switches from high to low. Therefore, as can be seen from FIG. 4 (j), the output data signal OD switches from low to high. Moreover, FIG.
As can be seen by comparing (c) and (j), the voltage is converted to a voltage VDD1 higher than the voltage VDD4.

Next, as can be seen from FIG.
Assume that the input data signal ID has been switched from high to low at 3. However, since the clock signal CK at this time is high as shown in FIG. 4B, the output from the data output terminal Q1 is performed by the holding function of the master latch circuit ML as shown in FIG. 4D. Remain high. Also, as can be seen from FIG. 4 (e), the output from the inverted data output terminal / Q1 is maintained in a low state.

Next, as can be seen from FIG.
At 4, the clock signal switches from high to low. Then, as can be seen from FIG. 4C, the input data signal ID
Is in a low state, the output of the data output terminal Q1 switches from high to low as shown in FIG.
Further, as shown in FIG. 4E, the output of the inverted data signal output terminal / Q1 switches from low to high. But,
Since the inverted clock signal / CK is high, the transmission gates TG1 and TG2 are turned off, the mode switching unit 10 of the slave latch circuit SL is held, and the state when the clock signal CK is switched is maintained. That is, as can be seen from FIGS. 4H and 4I, point B is maintained in a high state and point A is maintained in a low state.
Therefore, the output data signal OD is also maintained at a high state.

Next, as can be seen from FIG.
At 5, the clock signal CK switches from low to high. Then, transmission gates TG1 and TG2 are both turned on. Therefore, as can be seen from FIGS. 4F and 4G, the potential of the gate G of the n-type MOS transistor nMOS1 becomes low and the n-type MOS transistor nM
The potential of the gate G of OS2 becomes high. Then, the potential at point B switches from high to low, and the potential at point A switches from low to high. That is, the mode switching unit 10 enters the passing state. Therefore, the output data signal OD switches from high to low.

As described above, according to the flip-flop circuit with a voltage level conversion function according to the present embodiment, as shown in FIG. 1, the voltage level conversion circuit 20 is provided in the slave latch circuit SL. The number can be reduced. That is, since it is not necessary to provide a voltage level conversion circuit separately from the master-slave type flip-flop unlike the conventional case, the number of transistors can be reduced. In other words, the n-type MOS transistors nMOS3 and nMOS
Since the latch function can be realized only by adding the two transistors of No. 4, the number of transistors can be reduced. Since the number of transistors can be reduced in this manner, the overall circuit area can be reduced and the overall operation speed can be increased.

Further, except for the voltage level conversion circuit 20, the voltages VDD2 and VDD which are lower than the voltage VDD1 are set.
Since operation can be performed with DD3 and VDD4, power consumption can be suppressed. That is, since the master latch circuit ML operates at the voltage VDD2 lower than the voltage VDD1, power consumption can be suppressed. Moreover, the voltage of the clock signal CP and the input data signal ID can be reduced. That is, the clock signal CP
From the ground to the width of the voltage VDD3, and the input data signal ID from the ground to the width of the voltage VDD4. These voltages VDD3 and VDD4 can be made lower than the voltage VDD1, thereby suppressing power consumption. Can be.

Further, since the voltages VDD3 and VDD4 are equal to or higher than the voltage VDD2,
The flip-flop operation can be performed without flowing a steady leak current to the master latch circuit ML. That is, as can be seen from FIG. 5, for example, a p-type MOS transistor pMOS5 and an n-type MOS transistor nMOS
5 are connected in series, there is a problem that if the voltages VDD3 and VDD4 are lower than the voltage VDD2, the p-type MOS transistor pMOS3 cannot be completely turned off. Because the p-type MOS transistor pMOS
This is because the potential difference Vgs between the gate and the source of No. 5 does not become smaller than the threshold voltage. Therefore, there is a problem that the p-type MOS transistor pMOS5 is not completely turned off and a leak current flows. However, as can be seen from FIG.
If the voltages VDD3 and VDD4 are higher than D2, or if the voltages VDD2 and VDD3 and VDD4 are equal, the potential difference Vgs between the gate and the source becomes equal to or less than the threshold voltage, so that no leak current flows. be able to.

(Second Embodiment) A second embodiment of the present invention is a modification of the flip-flop circuit with a voltage level conversion function in the first embodiment, and more specifically, an output terminal of the master latch circuit ML. To the data output terminal Q1
And the structure of the slave latch circuit SL is further simplified.

FIG. 7 is a diagram showing an example of a flip-flop circuit with a voltage level conversion function according to the second embodiment of the present invention.

As can be seen from FIG. 7, the master latch circuit ML has a data output terminal Q1 as an output terminal.
Only, and the inverted data output terminal / Q1 is not provided.

The slave latch circuit SL is composed of the mode switching section 12 and the voltage level conversion circuit 22 as in the first embodiment, but the configuration is different. More specifically, the data output terminal Q1 is connected to the drain D of the n-type MOS transistor nMOS6.
The clock signal CK is input to the gate G of the n-type MOS transistor nMOS6. Also, this n
The source S of the type MOS transistor nMOS6 is connected to the inverter INV2. This inverter INV
2 is connected to the inverter INV3. The output of the inverter INV3 becomes the output data signal OD which is the output of the slave latch circuit SL. The n-type M described above
A point E between the OS transistor nMOS6 and the inverter INV2 is connected to the drain D of the p-type MOS transistor pMOS6 provided on the upper side in the figure. This p
The source S of the p-type MOS transistor pMOS6 has a voltage V
It is connected to the power supply of DD1. Also, this p-type MOS
The gate G of the transistor pMOS6 is connected to a point F between the inverter INV2 and the inverter INV3. The point E and the output side of the inverter INV3 are connected via an n-type MOS transistor nMOS7. The inverted clock signal / CK is input to the gate G of the n-type MOS transistor nMOS7.

Except for these points, the flip-flop circuit with a voltage level conversion function according to the second embodiment has the following features.
Since it is the same as the first embodiment described above, a detailed description thereof will be omitted.

Next, the operation of the flip-flop circuit with a voltage level conversion function according to the second embodiment will be described.

First, the independent operation of the slave latch circuit SL will be described. First, a case where the clock signal CK is high will be described. When the clock signal CK is high, the n-type MOS transistor nMOS6 is turned on. Also, since the inverted clock signal / CK is low,
The n-type MOS transistor nMOS7 is turned off.
Therefore, the flip-flop circuit with the voltage level conversion function of FIG. 7 when the clock signal CK is high is equivalent to the circuit shown in FIG.

As can be seen from FIG. 8, when the clock signal CK is high, the slave latch circuit SL
This is a circuit that raises the voltage level of the intermediate output signal from the data output terminal Q1 in the master latch circuit ML and passes the signal as it is. That is, when the intermediate output signal from the data output terminal Q1 is high, the intermediate output signal is the voltage VDD2. This voltage VDD2 is converted to a higher voltage VDD1, and an output data signal OD as a high signal is output. On the other hand, the data output terminal Q1
When the intermediate output signal is low, the voltage of this intermediate output signal is ground, and this ground potential is output as it is as the output data signal OD. This will be described in more detail below.

It is assumed that the intermediate output signal from data output terminal Q1 in master latch circuit ML is low. Then, the output of the inverter INV2 becomes high,
The output of the inverter INV3 becomes low. Therefore,
The output data signal OD becomes low. Inverter INV2
Operates at the voltage VDD1, the point F is at the voltage VDD.
It becomes 1. Therefore, the p-type MOS transistor pMOS
The gate G of No. 6 is at the voltage VDD1. Therefore, the p-type MOS transistor pMOS6 is turned off,
Point E is kept low.

On the contrary, the master latch circuit ML
The case where the intermediate output signal from the data output terminal Q1 is high is described. In this case, the inverter INV
2 is low, and the output of inverter INV3 is high. Therefore, the output data signal OD becomes high. It can be seen that the voltage of the output data signal OD is the voltage VDD1, which is higher than the voltage VDD2 which is the voltage of the intermediate output signal from the data output terminal Q1.
The voltage at the point F on the output side of the inverter INV2 becomes the ground. Therefore, the p-type MOS transistor p
The voltage of the gate G of the MOS 6 also becomes the ground. Therefore, the p-type MOS transistor pMOS6 is turned on, and the point E is kept high.

Note that strictly speaking, the data output terminal Q
Immediately after the intermediate output signal from 1 goes high, the potential at point F does not go to ground. This is because the intermediate output signal is the voltage VDD2, and the potential at the point E becomes VDD2-α, which is lower by the threshold voltage of the n-type MOS transistor nMOS6. This VDD2-α is
The value is lower than the voltage VDD1. Therefore, the voltage VD
The output of the inverter INV2 operating at D1 does not fall to ground. However, even if the voltage does not fall to the ground, the p-type MOS transistor pMOS6
Is turned on enough to turn on. As a result, the p-type MOS transistor pMOS6 is turned on. This p-type MOS transistor pMOS6
Is turned on, the point E becomes the voltage VDD1. Then, the output voltage of the inverter INV2 becomes a complete ground.

The above is the description of the independent operation of the slave latch circuit SL when the clock signal CK is high. Next, the operation of the slave latch circuit SL when the clock signal CK is low is described. A single operation will be described.

As can be seen from FIG. 7, the clock signal CK
Is low, the n-type MOS transistor nMOS6 is turned off. Further, since the inverted clock signal / CK is high, the n-type MOS transistor nMOS7 is turned on. Therefore, the flip-flop circuit with the voltage level conversion function of FIG. 7 when the clock signal CK is low is equivalent to the circuit shown in FIG.

As can be seen from FIG. 9, the slave latch circuit SL is a circuit that holds the output data signal OD as it is when the clock signal CK switches from high to low. That is, when the output data signal OD is high when the clock signal CK is switched to low, this high state is changed to the next clock signal CK.
Hold until goes high. Conversely, if the output data signal OD is low when the clock signal CK is switched to low, the low state is maintained until the next clock signal CK goes high. This will be described in more detail below.

It is assumed that the output data signal OD is in the high state when the clock signal CK switches from high to low. In this case, the high state of the point E is maintained, and the low state of the point F is also maintained. Therefore, the ON state of the p-type MOS transistor pMOS6 is also maintained, and the point E remains at the high state of the voltage VDD1. Point F
Is in the low state, the output of the inverter INV3 is maintained in the high state.

On the contrary, it is assumed that when the clock signal CK switches from high to low, the output data signal OD is in the low state. In this case, the low state at the point E is maintained, and the high state at the point F is also maintained. Therefore, the off state of the p-type MOS transistor pMOS6 is also maintained, and the voltage at the point E remains at ground. That the point F is in the high state means that the inverter INV3
Is maintained in a low state.

Up to this point, the independent operation of the slave latch circuit SL has been described. Next, referring to FIG.
The overall operation of the flip-flop circuit with a voltage level conversion function will be described. FIG. 10 is a diagram showing time charts at various points in the flip-flop circuit with a voltage level conversion function. FIG. 10A shows the clock signal CP.
5 is a time chart showing an example, and the amplitude is from the ground to the width of the voltage VDD3. FIG. 10B is a time chart showing an example of the clock signal CK, which oscillates with a width of the voltage VDD2 from the ground. FIG. 10C is a time chart showing an example of the input data signal ID, which oscillates with a width of the voltage VDD4 from the ground. FIG. 10 (d)
Is a time chart showing an example of an intermediate output signal from the data output terminal Q1, which oscillates with the width of the voltage VDD2 from the ground. FIGS. 10E and 10F are time charts showing examples of voltages at points E and F.
(G) is a time chart showing an example of the output data signal OD, and each of the signals oscillates with the width of the voltage VDD1 from the ground.

As can be seen from FIGS. 10 and 7, the clock signal CK is input to the gate G of the n-type MOS transistor nMOS6. When the inverted clock signal / CK is n
Input to the gate G of the type MOS transistor nMOS7. The clock signal CK and the inverted clock signal / CK are input to the master latch circuit ML.

In the state where the clock signal CK is input, as shown in FIG. 10C, at time t1, the data input terminal D of the master latch circuit ML is turned on.
It is assumed that the input data signal ID input to 1 has switched from low to high. At this time t1, FIG.
As can be seen from FIG. 10B, since the clock signal CK is low, the high signal in the input data signal ID is, as can be seen from FIG.
1 is output. However, as can be seen from FIG. 10B, since the clock signal CK is still low, the n-type MOS transistor nMOS6 is off. Therefore, as can be seen from FIG. 10E, the voltage at the point E remains low.

Next, as can be seen from FIG. 10B, when the clock signal CK switches from low to high at time t2, the n-type MOS transistor nMOS6 in FIG. 7 is turned on. Therefore, as can be seen from FIG.
The voltage at point E goes high. However, as can be seen from the above description, the voltage at the point E immediately after the n-type MOS transistor nMOS6 is turned on is VDD2-α, and it cannot be said that the voltage is completely high yet. Therefore, as can be seen from FIG. 10F, the potential of the point F does not become the ground, but becomes β. However, the voltage at this point F is p
This is a voltage sufficient to turn on the type MOS transistor pMOS6. Therefore, the p-type MOS transistor pMOS6 is turned on, and as can be seen from FIG. 10 (e), the voltage at the point E becomes the voltage VDD1 with a delay of a certain time, and as can be seen from FIG. Becomes ground with a certain delay.

Next, as can be seen from FIG. 10C, it is assumed that the input data signal ID switches from high to low at time t3. However, as can be seen from FIG. 10B, since the clock signal CK at this time is high,
As can be seen from (d), the intermediate output signal from the data output terminal Q1 is maintained at a high state by the holding function of the master latch circuit ML.

Next, as can be seen from FIG. 10B, the clock signal switches from high to low at time t4. As can be seen from FIG. 10B, the inverted clock signal / CK switches from low to high. Then, FIG.
As can be seen from (c), since the input data signal ID is in the low state, the intermediate output signal from the data output terminal Q1 switches from high to low as shown in FIG. However, since the inverted clock signal / CK is high, in the slave latch circuit SL, the mode switching unit 12 is in the holding state, and the state when the clock signal CK is switched is maintained. That is, FIGS. 10 (e) to 10 (g)
As can be seen, the voltage at point E is maintained at a high state and the voltage at point F is maintained at a low state. For this reason,
The output data signal OD is also maintained at a high state.

Next, as can be seen from FIG. 10B, the clock signal CK switches from low to high at time t5.
Then, the n-type MOS transistor nMOS6 is turned on. Therefore, as can be seen from FIG. 10 (d), the intermediate output signal from the data output terminal Q1 is low, so that the voltage at the point E switches from high to low as can be seen from FIG. 10 (e). Therefore, the voltage at the point F switches from low to high, and the output data signal OD switches from high to low.

As described above, according to the flip-flop circuit with the voltage level conversion function according to the second embodiment, as can be seen from FIG. 7, the voltage level conversion circuit 22 is provided in the slave latch circuit SL. The same operation as the embodiment can be achieved. That is, since it is not necessary to provide a voltage level conversion circuit separately from the master-slave type flip-flop unlike the conventional case, the number of transistors can be reduced. In other words, the mode switching unit 12 can be realized only by adding the n-type MOS transistor nMOS7 to the voltage level conversion circuit 22, so that the number of transistors can be reduced as compared with the first embodiment. Such reduction in the number of transistors makes it possible to increase the speed of the entire circuit. Moreover, in the slave latch circuit SL, the number of elements that require the input of the clock signal CK or the inverted clock signal / CK can be the two n-type MOS transistors nMOS6 and nMOS7, so that the power consumption can be reduced. In addition, the output of the master latch circuit ML is connected to the data output terminal Q
Since there is only one, the number of output terminals in the master latch circuit ML can also be reduced. Therefore, the entire circuit area can be further reduced.

Further, as can be seen from FIG. 7, similar to the first embodiment, the voltage level conversion circuit 22 is provided in the slave latch circuit SL, so that the conventional flip-flop with a voltage level function shown in FIG. 17 is provided. It can be operated at high speed. That is, the speed can be increased by increasing the operating voltage of the slave latch circuit SL, and the speed can be increased by reducing the total number of transistors.

Further, similarly to the first embodiment, except for the voltage level conversion circuit 22, the operation can be performed at the voltages VDD2, VDD3, and VDD4 which are lower than the voltage VDD1, so that the power consumption can be suppressed. Can be.
That is, since the master latch circuit ML operates at the voltage VDD2 lower than the voltage VDD1, power consumption can be suppressed. Further, the voltage of the clock signal CK and the input data signal ID can be reduced. That is, the clock signal CK is made to swing from the ground by the width of the voltage VDD3, and
The amplitude is set to the width of DD4, and these voltages VDD3, VDD4
Can be made lower than the voltage VDD1, so that power consumption can be suppressed.

Further, since the voltages VDD3 and VDD4 are equal to or higher than the voltage VDD2,
The flip-flop operation can be performed without flowing a steady leak current to the master latch circuit ML.

The present invention is not limited to the above embodiment, but can be variously modified. For example, the inverted data output terminal / Q1 of the master latch circuit ML shown in FIG.
It can also be configured as shown in FIG. That is,
By connecting the transmission gate TG1 and the n-type MOS transistor nMOS2 via the inverter INV4, the inverted data output terminal / Q1 can be omitted.

Further, the gate circuit can be configured using a clocked inverter as shown in FIG. Further, it may be configured only with an n-type MOS transistor as shown in FIG. 13 or only with a p-type MOS transistor as shown in FIG.

The relationship between the levels of the voltages VDD1 to VDD4 is not limited to the above. In addition, the input data signal ID and the clock signal CK can use signals having a plurality of different amplitudes. For example, the clock signal C
K may have both the amplitude of the width of the voltage VDD3 from the ground and the amplitude of the width of the voltage VDD1 from the ground. Similarly, the input data signal ID is supplied from the ground to the voltage VDD.
The amplitude of the width of 4 and the amplitude of the width of the voltage VDD1 from the ground may be mixed.

Further, by making the voltage VDD1, the voltage VDD2, and the voltage VDD4 equal and setting only the voltage VDD3 lower than these voltages, the power of the clock system can be reduced.

[0072]

As described above, according to the latch circuit with the voltage level function and the flip-flop circuit according to the present invention, the voltage level conversion function is provided in the latch circuit.
The required number of elements can be reduced, which can reduce power consumption and increase operating speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a circuit of a flip-flop with a voltage level conversion function according to a first embodiment of the present invention.

2 is an equivalent circuit diagram of the flip-flop circuit with a voltage level conversion function in FIG. 1 in a state where a clock signal is high.

3 is an equivalent circuit diagram of the flip-flop circuit with a voltage level conversion function in FIG. 1 when a clock signal is in a low state;

FIG. 4 is a diagram showing time charts at various points in the flip-flop circuit with a voltage level conversion function of FIG. 1;

FIG. 5 is a diagram illustrating a state in which a MOS transistor does not completely turn off and a leak current flows.

FIG. 6 shows that the MOS transistor is completely turned off,
FIG. 4 is a diagram illustrating a state in which no leak current flows.

FIG. 7 is a diagram illustrating an example of a circuit of a flip-flop with a voltage level conversion function according to a second embodiment of the present invention.

8 is an equivalent circuit diagram of the flip-flop circuit with a voltage level conversion function in FIG. 7 when a clock signal is in a high state.

9 is an equivalent circuit diagram of the flip-flop circuit with a voltage level conversion function in FIG. 7 when a clock signal is in a low state.

10 is a diagram showing a time chart of each part in the flip-flop circuit with a voltage level conversion function of FIG. 7;

11 is a diagram showing a modification of the flip-flop circuit with a voltage level conversion function shown in FIG. 1;

FIG. 12 is a diagram illustrating a clocked inverter which is another example of the gate circuit.

FIG. 13 shows another example of an n-type M as a gate circuit.
FIG. 14 illustrates an OS transistor.

FIG. 14 shows a p-type M, which is another example of a gate circuit.
FIG. 14 illustrates an OS transistor.

FIG. 15 illustrates a general master-slave flip-flop circuit.

FIG. 16 is a diagram showing a conventional flip-flop circuit provided with a voltage level conversion function.

FIG. 17 is a diagram showing another conventional flip-flop circuit provided with a voltage level conversion function.

FIG. 18 is a diagram showing another conventional flip-flop circuit provided with a voltage level conversion function.

[Explanation of symbols]

 ML master latch circuit SL slave latch circuit ID input data signal OD output data signal CK clock signal / CK inverted clock signal 10 mode switching section 12 mode switching section 20 voltage level conversion circuit 22 voltage level conversion circuit TG1 transmission gate TG2 transmission gate

Claims (9)

[Claims] A voltage level converting means for converting a voltage level of an input signal and outputting an output signal having a voltage level different from the voltage level of the input signal, and according to an input control signal, The voltage level conversion means is switched into two states, a passing state in which the input signal passes and becomes an output signal, and a holding state in which the input signal is held and becomes an output signal when the control signal is switched. A latch circuit having a voltage level conversion function, comprising: mode switching means for switching. 2. The voltage level conversion means according to claim 1, wherein the first and second transistors have input terminals connected to a power supply of a first voltage, and have one output terminal and the other control terminal connected to each other. First and second transistors, and third and fourth transistors provided between output terminals of the first and second transistors and a power supply of a second voltage, respectively, wherein the first and second transistors and A third and a fourth switch for turning on and off the conduction between the power supply of the second voltage and the power supply complementarily according to the input signal;
A transistor, and an output terminal for extracting the output signal provided at at least one of between the first transistor and the third transistor and between the second transistor and the fourth transistor. A mode switching unit configured to connect an output terminal of the first transistor and a control terminal of the fourth transistor, the fifth transistor being a fifth transistor having a control terminal to which the control signal is input; A sixth transistor that connects an output terminal of the second transistor and a control terminal of the third transistor, the sixth transistor having a control terminal to which the control signal is input. The latch circuit with a voltage level conversion function according to claim 1. 3. The voltage level conversion means, comprising: a first inverter to which the input signal is input, and a second inverter having an input side connected to an output side of the first inverter and outputting the output signal from an output side. A control terminal connected between the first inverter and the second inverter, an input terminal connected to a power supply of a first voltage, and an output terminal connected to the input side of the first inverter. And a first transistor, wherein the mode switching means is a second transistor that connects an output side of the second inverter and an input side of the one inverter, and is a control terminal to which the control signal is input. The latch circuit with a voltage level conversion function according to claim 1, further comprising a second transistor having: 4. A master latch circuit to which an input data signal and a control signal are inputted, wherein the master latch circuit receives
A passing state in which the input data signal is passed to be an intermediate output signal, and a holding state in which the input data signal is held and the intermediate output signal is held when the control signal is switched,
A master latch circuit having two states, and a slave latch circuit to which the intermediate output signal and the control signal are input, wherein the master latch circuit is in the holding state according to the control signal. A pass state in which an intermediate output signal is passed to be an output data signal, and when the master touch circuit is in the pass state, the intermediate output signal when the control signal is switched is held and held as an output data signal And a slave latch circuit that converts the voltage level of the intermediate output signal and outputs the output data signal at a voltage level different from the voltage level of the intermediate output signal. Flip-flop circuit with level conversion function. 5. The flip-flop according to claim 4, wherein the slave latch circuit converts the voltage level of the output data signal higher than the voltage level of the intermediate output signal. circuit. 6. The voltage according to claim 5, wherein at least a part of the slave latch circuit operates at a first voltage, and the master latch circuit operates at a second voltage lower than the first voltage. Flip-flop circuit with level conversion function. 7. The control signal oscillates between ground and a third voltage, and the input data signal oscillates with a width between ground and a fourth voltage. 7. The flip-flop circuit with a voltage level conversion function according to claim 6, wherein is a voltage equal to or higher than the second voltage. 8. The system according to claim 1, wherein said third voltage and said fourth voltage are equal to said first voltage.
The flip-flop circuit with a voltage level conversion function according to claim 7, wherein the flip-flop circuit is lower than a voltage. 9. The flip-flop circuit according to claim 7, wherein the third voltage and the fourth voltage are equal to each other.