KR101967872B1 - Ternary multiplier - Google Patents

Abstract

The present invention provides a 1 x 1 ternary multiplier. The 1 x 1 ternary multiplier comprises: one not MIN (NMIN) gate consisting of a NAND gate using a ternary transistor; one positive ternary inverter (PTI) configured using binary and ternary transistors; one not-shift (NSHIFT) gate configured using the binary and ternary transistors; one standard ternary inverter (STI) configured using the ternary transistor; one or-and-invert (OAI21) gate configured using the ternary transistor; and one and-or-invert (AOI21) gate configured using the ternary transistor. The connection structures of the transistors of the NMIN gate, PTI, NSHIFT, STI, OAI21 gate, and AOI21 gate are different from each other.

Description

Ternary multiplier {TERNARY MULTIPLIER}

The present invention relates to a ternary multiplier designed based on a ternary transistor.

The miniaturization of semiconductor processes has continued to improve the performance of computing systems. However, the explosive increase in power density makes it increasingly difficult to improve performance through process miniaturization.

As a countermeasure against this problem, multiple-valued logic has been proposed. Multi-value logic is a computing method that operates with three or more logic states, and has great advantages in area and power consumption reduction compared to binary logic. In particular, the ternary system can reduce the circuit complexity to a level of log3 (2n) = n × 63.1% compared to a binary system having n-bits. Although the research of the device unit applying the ternary logic has been actively conducted, the study of the design of the circuit unit is insignificant due to the absence of the integrated ternary device.

Recently, a ternary CMOS (T-CMOS) using the existing CMOS process has been proposed, and it is possible to design an integrated ternary circuit using the ternary device.

However, the ternary multiplier based on the existing T-CMOS has the following problems. Current-mode ternary multipliers are characterized by high power consumption and are vulnerable to noise and PVT (process, voltage, and temperature) variations. In addition, ternary multipliers using floating gates are also susceptible to noise and PVT variations. In addition, the ternary multiplier using a ternary-to-unary (T / U) converter has disadvantages of increased circuit complexity and high power consumption.

Republic of Korea Patent Registration 10-1689159 (Name of the invention: "Trial logic circuit")

One embodiment of the present invention is to solve the above-described problems of the prior art, and to provide a new ternary multiplier in voltage mode based on ternary transistors but without floating gates and T / U converters.

However, the technical problem to be achieved by the present embodiment is not limited to the technical problem as described above, and other technical problems may exist.

As a technical means for achieving the above-described technical problem, the 1 × 1 ternary multiplier according to an aspect of the present invention, one NMIN (not MIN) gate consisting of a NAND gate using a ternary transistor; One positive-ternary inverter (PTI) constructed using binary transistors and ternary transistors; One NSHIFT (NOT-SHIFT) gate constructed using binary transistors and ternary transistors; One standard ternary inverter (STI) configured using ternary transistors; One OAI21 (OR-AND-INVERT) gate constructed using ternary transistors; And one AOI21 (AND-OR-INVERT) gate configured using the ternary transistor, wherein the connection structures of the transistors of the NMIN gate, PTI, NSHIFT, STI, OAI21 gate, and AOI21 gate are different from each other.

And a 2x2 ternary multiplier according to another aspect of the present invention, a plurality of said 1x1 ternary multiplier; Five ternary half adders (THAs) for summing partial products generated through a plurality of 1 × 1 ternary multipliers; And two ternary full adders (TFAs) that sum the outputs of the THAs, wherein the connection structure of the transistors of the NMIN gate, PTI, NSHIFT, STI, OAI21 gate and AOI21 gate are different from each other.

In this case, the THA includes one N CARIN gate configured using a binary transistor and a ternary transistor, three NMAX (not MAX) gates each configured with a NOR gate using a ternary transistor, and two NMINs each configured with a NAND gate using a ternary transistor. (not MIN) gate, two standard ternary inverters (STI) each configured using ternary transistors, one positive-ternary inverter (PTI), binary configured using binary transistors and ternary transistors CARRY gate, NMAX gate, including one NSHIFT (NOT-SHIFT) gate configured using transistors and ternary transistors, and one NAOI21 (NOT-AND-OR-INVERT) gate configured using binary and ternary transistors. The connection structures of the transistors of the, NMIN gate, STI, PTI, NSHIFT, and NAOI21 gates are different from each other.

The TFA also includes two THAs, two inverters, and one CARRY gate.

In addition, the 6 × 6 ternary multiplier according to another aspect of the present invention, a plurality of 1 × 1 ternary multiplier; Five ternary half adders (THAs) for summing partial products generated by the plurality of 1 × 1 ternary multipliers; And a plurality of 2x2 ternary multipliers each including two ternary fulladders (TFAs) for summing outputs of the THAs and 13 partial products for summing partial products generated through the plurality of 2x2 ternary multipliers. THA and 22 TFAs.

According to any one of the aforementioned problem solving means of the present invention, by providing a voltage mode ternary multiplier using a ternary transistor but no T / U converter, the number of logic gates used and the number of ternary transistors accordingly Can be greatly reduced. Accordingly, it is possible to increase high energy efficiency and performance, and to significantly reduce power delay and power consumption, compared to conventional ternary multipliers.

1A is a diagram illustrating the structure of a conventional 1 × 1 ternary multiplier.
1B is a diagram illustrating a structure of a 1 × 1 ternary multiplier according to an embodiment of the present invention.
2 is a diagram illustrating ternary logic gates generally included in a ternary multiplier.
3 illustrates ternary logic gates included in a ternary multiplier according to an embodiment of the present invention.
4 is a diagram illustrating a structure of a 2 × 2 ternary multiplier according to an embodiment of the present invention.
5 is a view showing the structure of a conventional ternary half adder.
Figure 6 is a view showing the structure of the ternary half-adder and ternary full adder according to an embodiment of the present invention.
7 is a diagram illustrating the structure of a 6x6 ternary multiplier according to an embodiment of the present invention.
8 is a graph illustrating an operation result of a 1 × 1 ternary multiplier and a ternary adder according to an embodiment of the present invention.
9 is a graph comparing the number of transistors of a ternary multiplier and a conventional ternary multiplier according to an embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, this includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, which means that it may further include other components, except to exclude other components unless otherwise stated.

Hereinafter, a ternary multiplier according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A illustrates a structure of a conventional 1 × 1 ternary multiplier, and FIG. 1B illustrates a structure of a 1 × 1 ternary multiplier according to an embodiment of the present invention.

2 is a diagram illustrating ternary logic gates generally used in a ternary multiplier, and FIG. 3 is a diagram illustrating ternary logic gates included in a ternary multiplier according to an embodiment of the present invention.

First, a conventional 1 × 1 ternary multiplier will be described with reference to FIG. 1A.

Figure 1a (a) shows the entire logic circuit of a conventional 1x1 ternary multiplier, Figure 1a (b) shows the symbols of a T / U converter included in a conventional 1x1 ternary multiplier, (C) of 1a shows the logic circuit of such a T / U converter.

Referring to FIG. 2, a ternary logic gate, which is generally used in a ternary multiplier, is a standard ternary inverter (STI) shown in (a), and a negative-triggered inverter shown in (b). negative ternary inverter (NTI), positive ternary inverter (PTI) shown in (c), not MIN gate shown in (d), and negative shown in (e) -Not MAX gates, etc.

For reference, the truth tables of STI, NTI, PTI, not MIN gate and not MAX gate shown in FIG. 2 are shown in Table 1 below. In Table 1 below, I ₁ and I ₂ each represent an input.

TABLE 1

Referring to the logic gates shown in FIG. 2, a conventional 1 × 1 ternary multiplier such as in FIG. 1A has two T / U converters, six MIN gates, and three Including the MAX gate, it can be seen that one T / U converter as shown in (c) of Figure 1a includes two NTI, one PTI and one not MAX gate. In this case, the MIN gate illustrated in FIG. 1A (a) includes one STI and one not MIN gate, and the MAX gate includes one STI and one not MAX gate.

Accordingly, a conventional 1 × 1 ternary multiplier has a total of eight logic gates included in two T / U converters, twelve logic gates included in six MIN gates, and six logic gates included in three MAX gates. It is implemented with 26 logic gates that are the sum of them.

As such, the conventional 1 × 1 ternary multiplier requires two T / U converters, but is designed using only the MIN gate and the MAX gate among the logic gates, so that the efficiency of the ternary logic design is greatly reduced.

On the other hand, the 1x1 ternary multiplier 100 according to an embodiment of the present invention as shown in Figure 1b is implemented with six logic gates.

Specifically, the 1x1 ternary multiplier 100 according to an embodiment of the present invention is designed in combination with the new logic gates, together with the PTI, not MIN gate, and STI described above with reference to FIG. 2.

Referring to FIG. 3, a new ternary logic gate used in a ternary multiplier according to an embodiment of the present invention is a CARRY gate shown in (b), and NAOI21 (NOT-AND-OR-INVERT) shown in (c). Gate, an NSHIFT (NOT-SHIFT) gate shown in (d), an OAI21 (OR-AND-INVERT) gate shown in (e), and an AOI21 (AND-OR-INVERT) gate shown in (f). do.

At this time, the five new ternary logic gates illustrated in FIGS. 3B to 3F are implemented as 'combination of a ternary transistor and a binary transistor' or 'combination of a ternary transistor', respectively. In an embodiment of the present invention, it will be described that the transistors applied to the new ternary logic gate are the ternary CMOS (T-COMS) and the binary CMOS (Binary CMOS, CMOS) shown in FIG. However, the type of transistor is not limited, and various transistors that operate with the same function may be applied. In this case, the ternary CMOS illustrated in FIG. 3A is T- n / p MOS, and the binary CMOS is binary n / p MOS.

3 (b) to 3 (f) show schematic circuits and symbols of the respective ternary logic gates.

The structure of each of these ternary logic gates will be described in detail.

The CARRY gate shown in (b) is implemented with two T- p MOSs, two T- n MOSs, and two binary p MOSs. Specifically, the CARRY gates include first and second transistors 11 and 12, which are T- p MOS, third and fourth transistors 13 and 14, which are binary p MOS, and fifth and sixth transistors, which are T- n MOS. (15, 16).

In this case, data A is input to the gate terminals of the first, third, and fifth transistors 11, 13, and 15, respectively, and the gate terminals of the second, fourth, and sixth transistors 12, 14, and 16, respectively. Data B is input.

The source terminals of each of the first transistors 11 to 3rd transistors 11, 12, and 13 are connected, and the drain terminal and the output terminal Y of each of the first, second, and fourth transistors 11, 12, and 14 are connected. ₁ ) is connected. In addition, the drain terminal of the third transistor 13 and the drain terminal of the fourth transistor 14 are connected. The source terminal of the fifth transistor 15 is connected to the drain terminal and the output terminal Y ₁ of each of the first, second, and fourth transistors 11, 12, 14, and the drain terminal of the fifth transistor 15 is It is connected to the source terminal of the sixth transistor 15. The drain terminal of the sixth transistor 16 is grounded to ground.

In this operation of the CARRY gate, the impedance of each transistor varies according to the input voltage as shown in Table 2 below.

TABLE 2

In Table 2, the magnitude of the impedance is in the order of 0 <Low <High, where '0' means very small but is not actually zero. When the transistors are connected in series, they follow the largest impedance among the transistors, while the parallel connection has the smallest impedance.

Based on the impedance change, the impedance of the upper circuit (PUN, pull-up network) and the lower circuit (PDN, pull-down network) can be calculated based on the output node (Y ₁ ), and accordingly, Table 3 below. The output value is determined as in.

TABLE 3

For reference, as shown in Table 3, (High, High) or (0, 0) cannot occur.

For example, when A = 0 and B = 0 in the circuit of the CARRY gate shown in (b), the impedances of the first to fourth transistors 11 to 14 are zero, and the fifth and sixth transistors 15 , 16) is low. That is, since the PUN impedance is 0 and the PDN impedance is Low, the output value is '2'.

For another example, when A = 1 and B = 2 in the circuit of the CARRY gate shown in (b), the impedance of each of the first to sixth transistors 11 to 16 is Low, Low, 0, High, Low , 0. As a result, since the fifth and sixth transistors 15 and 16 are in series, the impedance of the fifth and sixth transistors 15 is high, and the impedance of the PDN becomes Low. In addition, since the impedance of the third and fourth transistors 13 and 14 in series connection is High, the first and second transistors 11 and 12 are in parallel with the third and fourth transistors 13 and 14, and thus the most The smallest value is Low, and the PUN's impedance is Low. Therefore, the impedance of PDN and PUN becomes Low-Low and the output value is '1'.

The remaining gate devices to be described below can also be analyzed based on the driving principles described above.

The NAOI21 gate shown in (c) is implemented with three T- n MOSs, one T- p MOS, and two binary n MOSs. Specifically, the NAOI21 gate includes the first and second transistors 21 and 22 as T- n MOS and the third transistor 23 as T- p MOS as the upper circuit PUN of the output node Y ₂ . And a fourth transistor 24, which is a T- n MOS, and fifth and sixth transistors 25 and 26, which are binary n MOS, as a lower circuit PDN of an output node Y ₂ .

In this case, data A is input to the gate terminals of the third and fourth transistors 23 and 24, respectively, and data B is input to the gate terminals of the first and fifth transistors 21 and 25, respectively. Data C is input to the gate terminals of the six transistors 22 and 26, respectively.

A source terminal of each of the first and second transistors 21 and 22 is connected, and a drain terminal of each of the first and second transistors 21 and 22 and a source terminal of the third transistor 23 are connected to each other. The drain terminal of the third transistor 23 is connected to the source terminal and the output terminal Y ₂ of each of the fourth and fifth transistors 24 and 25. In addition, the drain terminal of the fifth transistor 25 and the source terminal of the sixth transistor 26 are connected, and the drain terminal of the fourth transistor 24 is connected with the drain terminal and the ground of the sixth transistor 26.

The NSHIFT gate shown in (d) is implemented with one T- p MOS, one T- n MOS, and one binary n MOS. Specifically, NSHIFT gate output node (Y ₃₎ as a top circuit (PUN) of T- p containing the MOS of the first transistor (31), binary n MOS circuit as a bottom (PDN) of the output node (Y ₃₎ A second transistor 32 and a third transistor 33 which is a T- n MOS.

At this time, 1 is input to the gate terminals of the first and third transistors 31 and 33, and data A is input to the gate terminal of the second transistor 32. The drain terminal of the first transistor 31 is connected to the source terminal and the output terminal Y ₃ of the second and third transistors 32 and 33, respectively. In addition, the drain terminals of each of the second and third transistors 32 and 33 are connected to ground.

The OAI21 gate shown in (e) is implemented with three T- p MOSs and three T- n MOSs, the first to third transistors being T- p MOS as the top circuit PUN of the output node Y ₄ . (41, 42, 43) are included and the fourth to sixth transistors (44, 45, 46), which are T- n MOS, as the bottom circuit (PDN) of the output node (Y ₄ ).

In this case, data A is input to the gate terminals of the first and fifth transistors 41 and 45, respectively, and data B is input to the gate terminals of the second and sixth transistors 42 and 46, respectively. Data C is input to the gate terminals of the four transistors 43 and 44, respectively.

A source terminal of each of the first transistor 41 and the third transistor 43 is connected, a drain terminal of the first transistor 41 and a source terminal of the second transistor 42 are connected, and a second transistor ( Each of the drain terminals 42 and the third transistor 43 is connected to the source terminal and the output terminal Y ₄ of the fourth transistor 44. In addition, the drain terminal of the fourth transistor 44 is connected to the source terminal of each of the fifth and sixth transistors 45 and 46, and the drain terminal of each of the fifth and sixth transistors 45 and 46 is connected to the ground. do.

The AOI21 gate shown in (f) is implemented with three T- p MOSs and three T- n MOSs, the first to third transistors being T- p MOS as the top circuit PUN of the output node Y ₅ . (51, 52, 53) are included and the fourth to sixth transistors (54, 55, 56), which are T- n MOS, as the bottom circuit (PDN) of the output node (Y ₅ ). However, the AOI21 gate device has a different connection structure between the transistor and the OAI21 gate device described in (e) above.

In this case, data A is input to the gate terminals of the first and fourth transistors 51 and 54, and data B is input to the gate terminals of the second and fifth transistors 52 and 55, respectively. Data C is input to the gate terminals of the six transistors 53 and 56, respectively.

A source terminal of each of the first and second transistors 51 and 52 is connected, and a drain terminal of each of the first and second transistors 51 and 52 is connected to a source terminal of the third transistor 53. The drain terminal of the third transistor 53 is connected to the source terminal and the output terminal Y ₅ of each of the fourth and sixth transistors 54 and 56. In addition, the drain terminal of the fourth transistor 54 is connected to the source terminal of the fifth transistor 55, and the drain terminals of each of the fifth and sixth transistors 55 and 56 are connected to ground.

When the new ternary logic gates shown in FIG. 3 described above and the general ternary logic gates described in FIG. 2 are applied, the 1 × 1 ternary multiplier 100 shown in FIG. 1B includes one not MIN gate, 1. A total of six ternary logic gates can be implemented, including one PTI, one NSHIFT gate, one STI, one OAI21 gate P10, and one AOI21 gate P11.

As such, the illustrated 1 × 1 ternary multiplier 100 according to an embodiment of the present invention does not need to use a T / U converter, unlike the conventional ternary multiplier, and also reduces the total number of logic gates, thereby eliminating the ternary multiplier. Area and power consumption can be greatly reduced. In addition, the conventional 1 × 1 ternary multiplier described above with reference to FIG. 1A has a logic depth of 11, whereas the 1 × 1 ternary multiplier 100 according to an embodiment of the present invention has a logic depth of only 4. This greatly improves the performance of the multiplier (eg processing speed).

Meanwhile, using the 1 × 1 ternary multiplier 100 according to the embodiment of the present invention described with reference to FIGS. 1B to 3, the 2 × 2 ternary multiplier according to the embodiment of the present invention as shown in FIG. 4 below ( 200) can be designed. In addition, a 6 × 6 ternary multiplier according to an embodiment of the present invention as shown in FIG. 7 may be designed using the 2 × 2 ternary multiplier 200 according to an embodiment of the present invention.

Before describing the 2 × 2 ternary multiplier 200 and the 6 × 6 ternary multiplier according to an embodiment of the present invention, five new ternary logic gates according to an embodiment of the present invention described with reference to FIG. The operation will be described in more detail.

For reference, STI, PTI, and NTI described above may be designed as T-CMOS (T-nMOS and T-pMOS), binary nMOS and T-pMOS, T-nMOS, and binary pMOS, respectively. In addition, because MIN / MAX gates function like AND / OR gates in binary logic, T-CMOS is used instead of binary CMOS to design not MIN (or NMIN) and not MAX (or NMAX) gates as NAND and NOR gates. can do.

The multiplier may be designed using a typical MIN / MAX gate, but one embodiment of the present invention uses a new ternary logic function with a simplified single gate to increase performance and energy efficiency when designing a ternary arithmetic multiplier.

The CARRY gate shown in FIG. 3 (b) is included in a ternary half adder (THA) and a ternary full adder (TFA) according to an embodiment of the present invention to be described below with reference to FIG. 6. It handles the carry trit of the multiplier, and this CARRY gate can be used to significantly reduce delay and power consumption.

For example, the threshold voltage (V _th ) for the binary p MOS to be switched on by inputs '0' and '1' at the CARRY gate is designed to be -0.3V, and T- p MOS and T- If the nMOS is designed with 0.8V of threshold voltage (| V _th |) for switching on by input '2' and input '0' respectively, the output is divided by voltage division when both pull-up and pull-down circuits are off. Move to '1'.

The CARRY gate operates according to Equation 1 below.

For reference, ∧ denotes a minimum (MIN) function, ∨ denotes a maximum (MAX) function, and ´ denotes a not function. In addition, Y means an output, A and B respectively represent an input, and C means a carry.

 <Equation 1>

The truth table of the CARRY gate is shown in Table 4 below.

TABLE 4

의 함수로서, 입력 (A, B) = (1, 2), (2, 1), (2, 2)에 의해 생성된다. At this time, the carry treatment

As a function of, it is generated by inputs (A, B) = (1, 2), (2, 1), (2, 2).

Next, the NAOI21 gate and the NSHIFT gate shown in FIGS. 3C and 3D operate for a sum generator of THA, which will be described later with reference to FIG. 6.

In this case, the NAOI21 gate operates as shown in Equation 2 below to process the summation operation except for the input pairs (1, 1) and (2, 2).

<Equation 2>

이다. At this time,

to be.

The truth table of the NAOI21 gate is shown in Table 5 below.

TABLE 5

For example, if the binary n MOS of the NAOI21 gate is designed with V _th = 0.3V, it creates a current path to ground (GND) for inputs '1' and '2'.

On the other hand, the output '2' by the input (1, 1) in the THA to be described in Figure 6 below can be designed using the existing MIN gate, MAX gate, PTI described above, by the input (2, 2) Output '1' requires a function of the NSHIFT gate.

At this time, the NSHIFT gate operates as in Equation 3 below.

<Equation 3>

The truth table of the NSHIFT gate is shown in Table 6 below.

TABLE 6

Finally, the OAI21 gate and AOI21 gate shown in FIGS. 3E and 3F are included in the 1 × 1 ternary multiplier 100 and are not designed because they are designed with only ternary CMOS (T- n / p MOS). You can use gates and not MAX gates to simply represent functions without if-conditions.

At this time, the OAI21 gate operates as shown in Equation 4 below, and the truth table of the OAI21 gate is shown in Table 7 below.

<Equation 4>

TABLE 7

In addition, the AOI21 gate operates as shown in Equation 5 below, and the truth table of the AOI21 gate is shown in Table 8 below.

<Equation 5>

TABLE 8

Meanwhile, the operation of the n × n ternary multiplier according to an embodiment of the present invention of the ternary logic gates described with reference to FIGS. 2 and 3 may be verified by characterizing each ternary logic gate in terms of delay and power consumption.

For example, in an embodiment of the present invention, a T-CMOS model ("Compact Design of Low Power Standard Ternary Inverter based on OFF") operates as shown in Equation 6 below to characterize and verify operation of each ternary logic gate. -State Current Mechanism using Nano-CMOS Technology ", IEEE Trans. Electron Devices, 62 (8) (2015)).

<Equation 6>

In Equation 6, I _CON corresponds to a current according to a band-to-band tunneling (BTBT) mechanism, and I _EXP corresponds to a subthreshold current. The parameters of the T-CMOS model of Equation 6 are α = 4.6, β = 33, I _C = 100 n A, and I _MAX = 30 ms at V _DD = 1V.

And, as shown in Table 9 below, the simulation results for the delay, capacitance, and power consumption are obtained for each ternary logic gate.

TABLE 9

For timing analysis, transient simulations of six input transitions (0 → 1, 1 → 2, 2 → 1, 1 → 0, 0 → 2, 2 → 0) are performed with a rise time t _r of 1 ps. ) And fall time (t _f ). At this time, based on the 50% -50% propagation delay estimation, the intrinsic delay τ ₀ and the linear coefficient () by the linear delay model according to the load capacitance C _L as shown in Equation 7 below. linear coefficient X is extracted.

<Equation 7>

At this time, the input capacitance C _in and the output capacitance C _out with respect to the load capacitance C _L are extracted from the CV simulation using the T-CMOS model of Equation 6. This can be confirmed by the gate capacitance (C _gg = 0.345 f F) and the drain capacitance (C _dd ~ C _gg / 3) calculated from the equivalent oxide thickness (EOT) of 1 nm. Worst delays were observed in the '0' → '1' and '2' → '1' transitions.

The static power consumption (static Ps) of the ternary logic gates has three output states ('0', ') taking into account the off-leakage currents of n / p MOS and T- n / p MOS. 1 ',' 2 '). For example, the static current of an STI is 1 μA for outputs '0' and '2', 100 nA for output '1', and the output of the NTI (or PTI) output due to binary nMOS (or pMOS) 10 nA for 0 '(or' 2 '). For reference, the dynamic power P _D for the operation of the 6 × 6 ternary multiplier to be described below with reference to FIG. 7 is calculated as having a switching operation of 0.1 and an operating frequency of 20 MHz.

Hereinafter, a 2 × 2 ternary multiplier and a 6 × 6 ternary multiplier according to an embodiment of the present invention will be described in detail with reference to FIGS. 4 to 7.

4 is a diagram illustrating a structure of a 2 × 2 ternary multiplier according to an embodiment of the present invention. And Figure 5 is a view showing the structure of a conventional ternary half adder, Figure 6 is a view showing the structure of a ternary half adder and a ternary full adder according to an embodiment of the present invention.

Referring to FIG. 4, the 2 × 2 ternary multiplier 200 according to an embodiment of the present invention is a new one different from the 1 × 1 ternary multiplier 100 and the conventional ternary half adder THA and the ternary full adder TFA. It can be designed in combination with THA and TFA.

In this case, the partial product generated by the 1 × 1 ternary multiplier 100 is added by a ternary half adder (ie, a new THA), and the output of the ternary half adders is struck by a ternary full adder (ie, a new TFA). Is added.

In this regard, referring to FIG. 5, the conventional THA requires 34 logic gates, and the logic depths of the output S and the carry C _out are 10 and 8, respectively.

On the contrary, referring to FIG. 6A, the ternary half adder (ie, the new THA) according to the exemplary embodiment of the present invention does not include a T / U converter and can be designed with only 11 logic gates.

Specifically, the THA shown in FIG. 6A includes one CARRY gate, three not MAX gates, two not MIN gates, two STIs, one PTI, one NSHIFT, and one NAOI21 gate. do.

Therefore, the logical depths of S and C _out in THA according to an embodiment of the present invention are 4 and 2, respectively, less than about 40% compared to conventional THA, thereby greatly improving processing performance and energy efficiency.

In addition, referring to Figure 6 (b), the ternary full adder (ie, the new TFA) according to an embodiment of the present invention is the two THA described in Figure 6 (a), two inverters and one CARRY gate Is designed as.

4 again, the 2x2 ternary multiplier 200 according to the embodiment of the present invention includes four 1x1 ternary multipliers 100 described with reference to FIGS. 1B to 3 (100-1 and 100-2). , 100-3, 100-4), five strikeout half adders (THA) described with reference to FIG. 6A, and two strikeout full adders (TFAs) described with reference to FIG. 6B.

In addition, a 6 × 6 ternary multiplier according to an embodiment of the present invention using a 2 × 2 ternary multiplier 200 as shown in FIG. 4 and a ternary half adder (THA) and a ternary full adder (TFA) as shown in FIG. 6. Can be designed.

7 is a diagram illustrating the structure of a 6x6 ternary multiplier according to an embodiment of the present invention.

As in FIG. 7A, partial products are generated using the 2 × 2 ternary multiplier 200. In this case, each of the partial products generated using the 2 × 2 ternary multiplier 200 may be summed according to the Wallace adding structure as shown in FIG. In this case, the summation structure of the 6x6 ternary multiplier according to an embodiment of the present invention may be composed of 13 THA and 22 TFA.

For reference, in an embodiment of the present invention, a 1 × 1 ternary multiplier and a ternary full adder (TFA) according to an embodiment of the present invention are designed using an HSPICE (Hspice Reference Manual (Synopsy Co., Ltd.)). Verified. In the same manner, the functions of the 2 × 2 ternary multiplier and the 6 × 6 ternary multiplier according to the embodiment of the present invention can also be verified.

8 is a graph illustrating an operation result of a 1 × 1 ternary multiplier and a ternary adder according to an embodiment of the present invention.

At this time, all possible input combinations were put at an operating frequency of 50 MHz and the outputs were checked. The results are shown in FIG. 8.

In FIG. 8A, the output result of the 1 × 1 ternary multiplier is shown. In FIG. 8B, the output result of the TFA is shown. That is, it can be seen that the 1 × 1 ternary multiplier and the TFA according to an embodiment of the present invention generate a normal output for all input combinations.

Meanwhile, the result of comparing the ternary multiplier and the conventional ternary multiplier according to an embodiment of the present invention can be confirmed through FIG. 9.

9 is a graph comparing the number of transistors of a ternary multiplier and a conventional ternary multiplier according to an embodiment of the present invention.

Referring to FIG. 9, it can be seen that both the ternary multipliers and the ternary adders according to an embodiment of the present invention can reduce the number of transistors by 60% or more in comparison to the ternary multiplier according to the conventional design.

Meanwhile, in order to compare power consumption and performance between a conventional 6 × 6 ternary multiplier and a 6 × 6 ternary multiplier according to an embodiment of the present invention, a ternary static timing analysis (T-STA) method is used. The slowest delay and leakage power for the six input transitions (switching) of all ternary logic gates can be extracted by HSPICE simulation. In this case, the magnitude of the output capacitance of the driving gate and the magnitude of the input capacitance of the fanout gate are considered for dynamic voltage analysis. Based on this, the results of analyzing the total power and delay of the two ternary multipliers are shown in Table 8 below. The power delay product (PDP) used herein is defined as in Equation 8 below.

TABLE 8

<Equation 8>

In Equation 8, i is all used logic gates. The PDP in Table 8 is a numerical value normalized to the result of a multiplier proposed by Dhande (“Ternary Digital System: Concepts and Applications”, SM online Publisher LLC, (2014)). The 6x6 ternary multiplier reduces power consumption by 69.7% and at the same time achieves 22.8% performance improvement, and can reduce 77% PDP and 70% power consumption compared to the conventional ternary multiplier.

The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined form.

The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

100: 1 × 1 ternary multiplier P10: OAI21 gate
P11: AOI21 gate 200: 2 × 2 ternary multiplier

Claims (19)

One NMIN (not MIN) gate consisting of a NAND gate using ternary transistors;
One positive-ternary inverter (PTI) constructed using binary transistors and ternary transistors;
One NSHIFT (NOT-SHIFT) gate constructed using binary transistors and ternary transistors;
One standard ternary inverter (STI) configured using ternary transistors;
One OAI21 (OR-AND-INVERT) gate constructed using ternary transistors; And
Includes one AOI21 (AND-OR-INVERT) gate configured using ternary transistors,
And a connection structure of transistors of the NMIN gate, PTI, NSHIFT, STI, OAI21 gate and AOI21 gate is different from each other.
The method of claim 1,
Wherein the NSHIFT gate operates according to the function of Equation 1 below.
<Equation 1>

(A is the input and Y is the output.)
The method of claim 1,
The OAI21 gate is operated according to Equation 2 below, 1 × 1 ternary multiplier.
<Equation 2>

(A and B are inputs, C is a carry, Y is an output, ∧ is a minimum (MIN) function, ∨ is a MAX function, and ´ is a not function.)
The method of claim 1,
Wherein the AOI21 gate operates according to Equation 3 below.
<Equation 3>

(A and B are inputs, C is a carry, Y is an output, ∧ is a minimum (MIN) function, ∨ is a MAX function, and ´ is a not function.)
The method of claim 1,
The ternary transistor is at least one of Ternary nMOS (T-nMOS) and Ternary pMOS (T-pMOS),
Wherein said binary transistor is at least one of binary nMOS and binary pMOS.
The method of claim 5,
The NSHIFT gate is
A second transistor, T-pMOS, comprising a first transistor, T-pMOS, as a pull-up network (PUN) of the output node, and a second transistor, T-nMOS, a binary nMOS, as a pull-down network (PDN) of the output node. 3 transistors,
1 is input to the gate terminals of the first and third transistors, and first data is input to the gate terminals of the second transistor.
1 × 1, wherein a drain terminal of the first transistor is connected to a source terminal and an output terminal of each of the second and third transistors, and a drain terminal of each of the second and third transistors is connected to ground. Ternary multiplier.
The method of claim 5,
The OAI21 gate,
Fourth to sixth transistors, including first to third transistors, which are T-pMOS as the pull-up network (PUN) of the output node, and fourth to sixth transistors as T-nMOS, as the pull-downnetwork (PDN) of the output node. Including,
First data is respectively input to the gate terminals of the first and fifth transistors, second data is respectively input to the gate terminals of the second and sixth transistors, and second data is respectively input to the gate terminals of the third and fourth transistors. 3 data is entered,
A source terminal of each of the first and third transistors is connected, a drain terminal of the first transistor and a source terminal of the second transistor are connected, and a drain terminal of each of the second and third transistors is connected to the fourth transistor. Is connected to a source terminal and an output terminal of the drain terminal of the fourth transistor and the source terminal of each of the fifth and sixth transistors, and the drain terminal of each of the fifth and sixth transistors is connected to ground. Phosphorus, 1 × 1 Ternary multiplier.
The method of claim 5,
The AOI21 gate is,
Fourth to sixth transistors comprising first to third transistors, T-pMOS, as a pull-up network (PUN) of the output node, and fourth to sixth transistors as T-nMOS, as a pull-down network (PDN) of the output node. Including transistors,
First data is respectively input to the gate terminals of the first and fourth transistors, second data is respectively input to the gate terminals of the second and fifth transistors, and first data is respectively input to the gate terminals of the third and sixth transistors. 3 data is entered,
A source terminal of each of the first and second transistors is connected, a drain terminal of each of the first and second transistors is connected to a source terminal of the third transistor, and a drain terminal of the third transistor is connected to the fourth and second transistors. A source terminal and an output terminal of each of the sixth transistors, a drain terminal of the fourth transistor is connected to a source terminal of the fifth transistor, and a drain terminal of each of the fifth and sixth transistors is connected to ground Phosphorus, 1 × 1 Ternary multiplier.
1 NM (not MIN) gate configured with NAND gate with ternary transistor, 1 positive ternary inverter (PTI) configured with binary transistor and ternary transistor, 1 configured with binary transistor and ternary transistor Two NSHIFT (NOT-SHIFT) gates, one standard ternary inverter (STI) configured using ternary transistors, one OAI21 (OR-AND-INVERT) gate configured using ternary transistors, and a ternary transistor. A plurality of 1x1 ternary multipliers each comprising one AOI21 (AND-OR-INVERT) gate configured using;
Five ternary half adders (THAs) for summing partial products generated by the plurality of 1 × 1 ternary multipliers; And
Including two ternary full adders (TFAs) for summing the outputs of the THAs,
And a connection structure of transistors of the NMIN gate, PTI, NSHIFT, STI, OAI21 gate, and AOI21 gate is different from each other.
The method of claim 9,
THA,
1 CARRY gate constructed using binary transistors and ternary transistors,
Three NMAX (not MAX) gates, each consisting of a NOR gate with ternary transistors,
Two NMIN (not MIN) gates, each consisting of a NAND gate with ternary transistors,
Two standard ternary inverters (STI), each configured using ternary transistors,
1 positive-ternary inverter (PTI) configured using binary and ternary transistors,
One NSHIFT (NOT-SHIFT) gate constructed using binary and ternary transistors, and
Includes one NAOI21 (NOT-AND-OR-INVERT) gate configured using binary and ternary transistors,
Wherein the connection structure of the transistors of the CARRY gate, NMAX gate, NMIN gate, STI, PTI, NSHIFT, and NAOI21 gates are different from each other.
The method of claim 10,
The CARRY gate is to operate according to Equation 4 below, 2 × 2 ternary multiplier.
<Equation 4>

(A and B are inputs, C is a carry, Y is an output, ∧ is a minimum (MIN) function, ∨ is a MAX function, and ´ is a not function.)
The method of claim 10,
The NAOI21 gate is operated according to Equation 5 below, 2 × 2 ternary multiplier.
<Equation 5>

Where A and B are input, C is carry, Y is output, ∧ is the MIN function, ´ is the not function,

∨ is the MAX function.)
The method of claim 10,
The TFA is,
2 x 2 ternary multiplier comprising two said THA, two inverters and one CARRY gate.
The method of claim 10,
The ternary transistor is at least one of Ternary nMOS (T-nMOS) and Ternary pMOS (T-pMOS),
Wherein said binary transistor is at least one of binary nMOS and binary pMOS.
The method of claim 14,
The CARRY gate,
A pull-up network (PUN) of the output node includes first and second transistors, T-pMOS, and third and fourth transistors, binary pMOS, and a pull-down network (PDN) of the output node. Including fifth and sixth transistors that are T-nMOS,
First data is input to the gate terminals of the first, third, and fifth transistors, respectively, and second data is input to the gate terminals of the second, fourth, and sixth transistors,
A source terminal of each of the first to third transistors is connected, a drain terminal and an output terminal of each of the first, second and fourth transistors are connected, and a drain terminal of each of the third and fourth transistors is connected. The source terminal of the fifth transistor is connected to the drain terminal and the output terminal of each of the first, second, and fourth transistors, the drain terminal of the fifth transistor is connected to the source terminal of the sixth transistor, 2x2, wherein the drain terminal of the sixth transistor is connected to ground Ternary multiplier.
The method of claim 14,
The NAOI21 gate is,
A pull-up network (PUN) of the output node includes first and second transistors, T-nMOS, and a third transistor, T-pMOS, and a T- pull-down network (PDN, pull-down network) of the output node. a fourth transistor that is nMOS and fifth and sixth transistors that are binary nMOS,
First data is input to the gate terminals of the third and fourth transistors, respectively, and second data is input to the gate terminals of the first and fifth transistors, respectively, and the gate terminals of the second and sixth transistors, respectively. Third data is entered,
A source terminal of each of the first and second transistors is connected, a drain terminal of each of the first and second transistors and a source terminal of the third transistor are connected, and a drain terminal of the third transistor is connected to the fourth and second transistors. A source terminal and an output terminal of each of the fifth transistors, a drain terminal of the fifth transistor and a source terminal of the sixth transistor are connected, and a drain terminal of the fourth transistor is connected to a drain terminal and a ground of the sixth transistor. 2 × 2 ternary multiplier.
A ternary half adder (THA) summing a plurality of 1 × 1 ternary multipliers, partial products generated by the plural 1 × 1 ternary multipliers, and 2 summing outputs of the THAs A plurality of 2 × 2 ternary multipliers, each comprising three ternary full adders (TFAs); And
13 THA and 22 TFAs that sum the partial products generated by the plurality of 2 × 2 ternary multipliers,
The 1 × 1 ternary multiplier,
1 NM (not MIN) gate configured with NAND gate with ternary transistor, 1 positive ternary inverter (PTI) configured with binary transistor and ternary transistor, 1 configured with binary transistor and ternary transistor Two NSHIFT (NOT-SHIFT) gates, one standard ternary inverter (STI) configured using ternary transistors, one OAI21 (OR-AND-INVERT) gate configured using ternary transistors, and a ternary transistor. One AOI21 (AND-OR-INVERT) gate configured using
And a connection structure of transistors of the NMIN gate, PTI, NSHIFT, STI, OAI21 gate, AOI21 gate, CARRY gate, NMAX gate, and NAOI21 gate is different from each other.
The method of claim 17,
THA,
1 CARRY gate constructed using binary transistors and ternary transistors,
Three NMAX (not MAX) gates, each consisting of a NOR gate with ternary transistors,
Two NMIN (not MIN) gates, each consisting of a NAND gate with ternary transistors,
Two standard ternary inverters (STIs) each configured with ternary transistors,
1 positive-ternary inverter (PTI) configured using binary and ternary transistors,
One NSHIFT (NOT-SHIFT) gate constructed using binary and ternary transistors, and
A 6x6 ternary multiplier comprising one NAOI21 (NOT-AND-OR-INVERT) gate constructed using binary transistors and ternary transistors.
The method of claim 18,
The TFA is,
6 × 6 ternary multiplier, comprising two said THA, two inverters and one CARRY gate.

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