CN101951256B - Single-phase clock pass transistor adiabatic logic circuit, full adder and 5-2 compressor - Google Patents

Abstract

The invention discloses a single-phase clock pass transistor adiabatic logic circuit. The circuit is characterized by comprising a logic assignment circuit and an energy regeneration circuit, wherein the energy regeneration circuit consists of two pMOS transistors, namely a first pMOS transistor and a second pMOS transistor; the source of the first pMOS transistor and the source of the second pMOS transistor are connected in parallel with a power clock end; and the logic assignment circuit consists of four nMOS pass transistors, namely, a fifth nMOS pass transistor, a sixth nMOS pass transistor, a seventh nMOS pass transistor and an eighth nMOS pass transistor. The circuit has the advantages of combining the advantages of the single-phase power clock adiabatic logic (CAL) and complementary pass transistor logic (CPL), only one power clock CLK is needed, an auxiliary clock (CX and CX') alternately controls each stage of logic circuit, and the frequency of the circuit is half that of the power clock CLK; the single-phase power clock is used by a full adder on the basis, so that complexity of the clock circuit is reduced, the clock circuit is easier to generate, and the area of the circuit is greatly reduced; and a 5-2 compressor only consists of the full adder and has a simple and normative circuit structure and can compress more digits at one time.

Description

A kind of single phase clock transfer tube heat insulation logic circuit and full adder and 5-2 compressor reducer

Technical field

The present invention relates to a kind of 5-2 compressor reducer, especially relate to a kind of single phase clock transfer tube heat insulation logic circuit and full adder and 5-2 compressor reducer.

Background technology

At present VLSI designs technology has got into the nanometer stage, no matter from the performance and the cost consideration of chip itself, or the consideration of the angle in electronic product market, power consumption has become a key index of performance of integrated circuits gradually.The focus and the difficult point of the present IC design of low power consumption integrated circuit design having become.Traditional cmos circuit employing DC power supply, its energy are with the irreversible formal transformation of electric energy to heat energy, though can be through reducing supply voltage, reduction node capacitor and the redundant saltus step of minimizing switch reduce power consumption, and its Power Cutback amplitude is limited.Energy recovery type circuit is also claimed adiabatic circuits; Be a kind of brand-new Low-power Technology of rising in recent ten years, it is a kind of new type integrated circuit designing technique that obtains low-power consumption from the angle that changes power conversion, and its basic principle is to adopt ac power supply; Through reclaiming the electric charge of node capacitor; Energy in the recycling circuit, thus realize low-power consumption, so the energy consumption of energy recovery type digital integrated circuit significantly reduces.Adiabatic circuits has obtained very big achievement through nearly ten years development on circuit design, proposed a lot of heat insulation logic circuit types at present, like PAL-2N, ECRL, 2N-2N2P, and CAL and CPAL etc.These circuit all have good low-power consumption characteristic, but these circuit all need the polyphase ac power clock.The polyphase ac power clock produces circuit need produce a plurality of sinusoidal power clocks with fixed skew, and circuit structure is complicated, has increased circuit power consumption.Adopt the adiabatic circuits of polyphase ac power clock need in circuit, insert a lot of buffers in addition, to realize correct pile line operation, this has increased the power consumption of circuit undoubtedly again, and therefore circuit area also can increase.

Summary of the invention

Technical problem to be solved by this invention provides a kind of single phase clock transfer tube heat insulation logic circuit and full adder and 5-2 compressor reducer, and its clock circuit more is easy to generate, and the area of circuit reduces greatly, has correct logic functions and low-power consumption characteristic.

The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of single phase clock transfer tube heat insulation logic circuit; Comprise logical assignment circuit and energy recovery circuit; Described energy recovery circuit is that pMOS pipe and the 2nd pMOS pipe constitute by two pMOS pipes; The source electrode of the source electrode of described pMOS pipe and described the 2nd pMOS pipe is connected to the power clock end; The drain electrode of described pMOS pipe is connected with the source electrode of nMOS pipe; The drain electrode of described the 2nd pMOS pipe is connected with the source electrode of the 2nd nMOS pipe; The drain electrode of the drain electrode of described nMOS pipe and described the 2nd nMOS pipe is connected to ground; The drain electrode of the grid of the grid of described the 2nd pMOS pipe, described the 2nd nMOS pipe and described pMOS pipe is connected to signal output part, and the grid of the grid of described pMOS pipe, described nMOS pipe and the drain electrode of described the 2nd pMOS pipe are connected to the inversion signal output, and described signal output part is connected with the source electrode of the 3rd nMOS pipe; The grid of described the 3rd nMOS pipe is connected with the auxiliary clock signal end; Described inversion signal output is connected with the source electrode of the 4th nMOS pipe, and the grid of described the 4th nMOS pipe is connected with anti-phase auxiliary clock signal end, and promptly the 5th nMOS pipe, the 6th nMOS pipe, the 7th nMOS pipe and the 8th nMOS pipe constitute described logical assignment circuit by four nMOS transfer tubes; The source electrode of the source electrode of described the 5th nMOS pipe and the 6th nMOS pipe is connected with the drain electrode of described the 3rd nMOS pipe; The source electrode of the source electrode of described the 7th nMOS pipe and described the 8th nMOS pipe is connected with the drain electrode of described the 4th nMOS pipe, and the drain electrode of described the 5th nMOS pipe is connected with first signal input part, and the drain electrode of described the 6th nMOS pipe is connected with the secondary signal input; The drain electrode of described the 7th nMOS pipe is connected with the 3rd signal input part; The drain electrode of described the 8th nMOS pipe is connected with the 4th signal input part, and the grid of the grid of described the 5th nMOS pipe and described the 8th nMOS pipe is connected to the 5th signal input part, and the grid of the grid of described the 6th nMOS pipe and described the 7th nMOS pipe is connected to the 6th signal input part.

Use the full adder of above-mentioned single phase clock transfer tube heat insulation logic circuit, comprise that carry signal produces circuit and produces circuit with summing signal, described carry signal produces circuit, and promptly the 9th nMOS pipe, the tenth nMOS pipe, the 11 nMOS pipe, the 12 nMOS pipe, the 13 nMOS pipe, the 14 nMOS pipe, the 15 nMOS pipe and the 16 nMOS manage and constitute by the first single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipes; The described first single phase clock transfer tube heat insulation logic circuit comprises the first logical assignment circuit and first energy recovery circuit, and described first energy recovery circuit is that pMOS pipe and the 2nd pMOS pipe constitute by two pMOS pipes, and the drain electrode of described pMOS pipe is connected with the source electrode of nMOS pipe; The drain electrode of described the 2nd pMOS pipe is connected with the source electrode of the 2nd nMOS pipe, and the drain electrode of the drain electrode of described nMOS pipe and described the 2nd nMOS pipe is connected to ground, and the grid of the grid of described the 2nd pMOS pipe, described the 2nd nMOS pipe and the drain electrode of described pMOS pipe are connected to the carry signal output; The drain electrode of the grid of the grid of described pMOS pipe, described nMOS pipe and described the 2nd pMOS pipe is connected to anti-phase carry signal output, and described carry signal output is connected with the source electrode of the 3rd nMOS pipe, and described anti-phase carry signal output is connected with the source electrode of the 4th nMOS pipe; Promptly the 5th nMOS pipe, the 6th nMOS manage the described first logical assignment circuit, the 7th nMOS manages and the 8th nMOS pipe constitutes by four nMOS transfer tubes, and the source electrode of the source electrode of described the 5th nMOS pipe and the 6th nMOS pipe is connected with the drain electrode that described the 3rd nMOS manages, and the source electrode of source electrode that described the 7th nMOS manages and described the 8th nMOS pipe is connected with the drain electrode of described the 4th nMOS pipe; The source electrode of the source electrode of the drain electrode of described the 5th nMOS pipe and described the 9th nMOS pipe and described the tenth nMOS pipe also connects, and the source electrode of the drain electrode of described the 6th nMOS pipe and described the 11 nMOS pipe and the source electrode of described the 12 nMOS pipe also connect, and the source electrode of the drain electrode of described the 7th nMOS pipe and described the 13 nMOS pipe and the source electrode of described the 14 nMOS pipe also connect; The drain electrode of described the 8th nMOS pipe also connects with the source electrode of described the 15 nMOS pipe and the source electrode of described the 16 nMOS pipe, described summing signal produce circuit by the second single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipes promptly the 25 nMOS pipe, the 26 nMOS pipe, the 27 nMOS pipe, the 28 nMOS pipe, the 29 nMOS pipe, the 30 nMOS pipe, the 31 nMOS pipe and the 32 nMOS manage and constitute, the described second single phase clock transfer tube heat insulation logic circuit comprises the second logical assignment circuit and second energy recovery circuit; Described second energy recovery circuit is that the 3rd pMOS pipe and the 4th pMOS pipe constitute by two pMOS pipes, and the drain electrode of described the 3rd pMOS pipe is connected with the source electrode of the 17 nMOS pipe, and the drain electrode that described the 4th pMOS manages is connected with the source electrode of the 18 nMOS pipe; The drain electrode of the drain electrode of described the 17 nMOS pipe and described the 18 nMOS pipe is connected to ground, and the grid of the grid of described the 4th pMOS pipe, described the 18 nMOS pipe and the drain electrode of described the 3rd pMOS pipe are connected to the summing signal output, and the grid of the grid of described the 3rd pMOS pipe, described the 17 nMOS pipe and the drain electrode of described the 4th pMOS pipe are connected to anti-phase summing signal output; Described summing signal output is connected with the source electrode of the 19 nMOS pipe; Described anti-phase summing signal output is connected with the source electrode of the 20 nMOS pipe, and promptly the 21 nMOS pipe, the 22 nMOS manage the described second logical assignment circuit, the 23 nMOS manages and the 24 nMOS pipe constitutes by four nMOS transfer tubes, and the source electrode of the source electrode of described the 21 nMOS pipe and the 22 nMOS pipe is connected with the drain electrode that described the 19 nMOS manages; The source electrode of the source electrode of described the 23 nMOS pipe and the 24 nMOS pipe is connected with the drain electrode of described the 20 nMOS pipe; The source electrode of the source electrode of the drain electrode of described the 21 nMOS pipe and described the 25 nMOS pipe and described the 26 nMOS pipe also connects, and the source electrode of the drain electrode of described the 22 nMOS pipe and described the 27 nMOS pipe and the source electrode of described the 28 nMOS pipe also connect, and the source electrode of the drain electrode of described the 23 nMOS pipe and described the 29 nMOS pipe and the source electrode of described the 30 nMOS pipe also connect; The source electrode of the source electrode of the drain electrode of described the 24 nMOS pipe and described the 31 nMOS pipe and described the 32 nMOS pipe also connects; The source electrode of the source electrode of the source electrode of the source electrode of described pMOS pipe, described the 2nd pMOS pipe, described the 3rd pMOS pipe and described the 4th pMOS pipe is connected to the power clock end, and the grid of described the 3rd nMOS pipe is connected with the auxiliary clock signal end with the grid of described the 19 nMOS pipe, and the grid of described the 4th nMOS pipe is connected with anti-phase auxiliary clock signal end with the grid of described the 20 nMOS pipe; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of the grid of the grid of described the 6th nMOS pipe, described the 7th nMOS pipe, described the 9th nMOS pipe, described the 11 nMOS pipe, described the 25 nMOS pipe, described the 27 nMOS pipe, described the 29 nMOS pipe and described the 31 nMOS pipe is connected to the first addend input; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of the grid of the grid of described the 5th nMOS pipe, described the 8th nMOS pipe, described the 13 nMOS pipe, described the 15 nMOS pipe, described the 26 nMOS pipe, described the 28 nMOS pipe, described the 30 nMOS pipe and described the 32 nMOS pipe is connected to the first addend inverting input, and the grid of the grid of described the tenth nMOS pipe, the grid of described the 11 nMOS pipe, the grid of described the 13 nMOS pipe, the grid of described the 16 nMOS pipe, the grid of described the 26 nMOS pipe, the grid of described the 27 nMOS pipe, described the 30 nMOS pipe and the grid of described the 31 nMOS pipe are connected to the second addend input, and the grid of the grid of described the 9th nMOS pipe, the grid of described the 12 nMOS pipe, the grid of described the 14 nMOS pipe, the grid of described the 15 nMOS pipe, the grid of described the 25 nMOS pipe, the grid of described the 28 nMOS pipe, described the 29 nMOS pipe and the grid of described the 32 nMOS pipe are connected to the second addend inverting input; The grid of the grid of the drain electrode of the drain electrode of described the tenth nMOS pipe, described the 12 nMOS pipe, described the 22 nMOS pipe and described the 23 nMOS pipe is connected to the 3rd addend input, and the grid of the drain electrode of described the 14 nMOS pipe, the drain electrode of described the 16 nMOS pipe, described the 21 nMOS pipe and the grid of described the 24 nMOS pipe are connected to the 3rd addend inverting input.

Use the 5-2 compressor reducer of above-mentioned full adder; It is formed by first full adder, second full adder and the 3rd full adder cascade; The first addend input of described first full adder is connected with first input signal; The second addend input of described first full adder is connected with second input signal; The 3rd addend input of described first full adder is connected with the 3rd input signal; The first addend input of described second full adder is connected with the carry signal output of first full adder of upper level 5-2 compressor reducer; The second addend input of described second full adder is connected with the summing signal output of described first full adder, and the 3rd addend input of described second full adder is connected with the 4th input signal, and the first addend input of described the 3rd full adder is connected with the carry signal output of second full adder of upper level 5-2 compressor reducer; The second addend input of described the 3rd full adder is connected with the summing signal output of described second full adder, and the 3rd addend input of described the 3rd full adder is connected with the 5th input signal.

Compared with prior art; The invention has the advantages that single phase clock transfer tube heat insulation logic circuit of the present invention combines the advantage of single-phase power clock adiabatic logic (CAL) and complementary transfer tube logic (CPL); Only need same power clock CLK; And auxiliary clock (CX and

) is alternately controlled each level logic circuit, and its frequency is the half the of power clock CLK frequency; Only need to change the method that connects of the input signal of four transfer tubes of CAL-CPL logical assignment part among Fig. 1, and the structure of unnecessary change basic circuit can obtain like Fig. 2, Fig. 3 and 2 inputs and door shown in Figure 4,2 inputs or door, 2 input XOR gates.

Full adder of the present invention uses the single-phase power clock, has reduced the complexity of clock circuit, and clock circuit more is easy to generate like this, and the area of circuit also can reduce greatly simultaneously.In addition, because the utilization of the logical assignment circuit part of circuit of the present invention is the structure of CPL circuit, this circuit structure has modular characteristics; They all take identical topological structure; Just the arrangement of input is different, so the advantages of simple design of circuit, and structure also compares standard; This makes that the design of this type cell library is very simple, and the area of circuit is also littler.Compare with traditional full adder circuit based on static CMOS, because element circuit of the present invention has identical circuit structure, so the time-delay of its circuit, line and area all reduce relatively.

The present invention is applied to single-phase adiabatic full adder circuit in the element circuit 5-2 compressor reducer of multiplier, and the 5-2 compressor circuit only is made up of full adder, the circuit structure simple specification.Than the 4-2 compressor reducer, the once compressible figure place of 5-2 compressor reducer is more, can reduce the number of compressor reducer like this, optimizes the structure of multiplier circuit, simultaneously, because adiabatic circuits has lower power consumption, can realize the design of low-consumption multiplier like this.Single-phase adiabatic full adder and 5-2 compressor reducer are carried out simulating, verifying, and they have correct logic functions and low-power consumption characteristic the simulation result proof.

Adopt PTM 90nm and PTM 45nm CMOS technology device parameters, above-mentioned single-phase adiabatic full adder and 5-2 compressor reducer are carried out functional simulation.Fig. 7 has provided the analog waveform based on the single-phase adiabatic full adder of single-phase transfer tube clock adiabatic logic; Analog result shows that the single-phase adiabatic full adder based on single phase clock transfer tube adiabatic logic has correct logic functions; Fig. 8 and Fig. 9 have provided single-phase adiabatic full adder circuit of the present invention and static CMOS full adder respectively under the different operating frequency; The comparison of phase energy consumption weekly; Compare with the full adder of static CMOS, can be known by Fig. 8 and Fig. 9, single-phase adiabatic full adder circuit of the present invention has good low-power consumption effect.

Figure 10 is the structural representation of 5-2 compressor reducer of the present invention, the functional simulation figure that Figure 11 is the 5-2 compressor reducer under given five inputs and two prime carry signals, and analog result shows that single-phase adiabatic 5-2 compressor reducer of the present invention has correct logic functions.Figure 12 and Figure 13 are respectively 5-2 compressor reducer (the adiabatic 5-2 compressor reducers of single phase clock transfer tube of three kinds of Different Logic structures; Single phase clock adiabatic logic CAL 5-2 compressor reducer and static CMOS 5-2 compressor reducer), the energy consumption comparison diagram of phase weekly under different process and different operating frequency.Under the 90nm CMOS technology; Under the 100MHz operating frequency, the adiabatic 5-2 compressor reducer of single phase clock transfer tube is with respect to static CMOS 5-2 compressor reducer, and the phase energy consumption saves about 72.8% weekly; Under the 45nm CMOS technology; Under the 100MHz operating frequency, the adiabatic 5-2 compressor reducer of single phase clock transfer tube is with respect to static CMOS 5-2 compressor reducer, and the phase energy consumption saves about 63.6% weekly.We also will compare with respect to the energy consumption saving situation of 5-2 compressor reducer under identical operating frequency based on CAL based on the 5-2 compressor reducer of CAL-CPL simultaneously; Under the 90nm CMOS technology; Power Cutback rate maximum can reach 18.34%; Under the 45nm CMOS technology, Power Cutback rate maximum can reach 15.01%.

Description of drawings

Fig. 1 is structural representation, expression graphical diagram and the clock figure of single-phase transfer tube clock adiabatic logic basic circuit;

Fig. 2 is the structural representation and expression graphical diagram of single-phase transfer tube clock adiabatic logic and door;

Fig. 3 is the structural representation and expression graphical diagram of single-phase transfer tube clock adiabatic logic or door;

Fig. 4 is the structural representation and expression graphical diagram of single-phase transfer tube clock adiabatic logic XOR gate;

Fig. 5 is for to represent graphical diagram based on the single-phase adiabatic full adder of CAL-CPL;

Fig. 6 (a) is the carry signal generation circuit based on the single-phase adiabatic full adder of CAL-CPL;

Fig. 6 (b) is the summing signal generation circuit based on the single-phase adiabatic full adder of CAL-CPL;

Fig. 7 is the functional simulation waveform of full adder of the present invention;

Fig. 8 for full adder of the present invention when 90nm technology under the different operating frequency with the static CMOS full adder energy consumption comparison diagram of phase weekly;

Fig. 9 for full adder of the present invention when 45nm technology under the different operating frequency with the static CMOS full adder energy consumption comparison diagram of phase weekly;

Figure 10 is the structural representation of 5-2 compressor reducer of the present invention;

Figure 11 is the functional simulation waveform of 5-2 compressor reducer of the present invention;

Figure 12 for 5-2 compressor reducer of the present invention when 90nm technology under the different operating frequency with the static CMOS 5-2 compressor reducer energy consumption comparison diagram of phase weekly;

Figure 13 for 5-2 compressor reducer of the present invention when 45nm technology under the different operating frequency with the static CMOS 5-2 compressor reducer energy consumption comparison diagram of phase weekly.

Embodiment

Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.

Embodiment one: as shown in Figure 1; Single phase clock transfer tube heat insulation logic circuit; Form by logical assignment circuit and energy recovery circuit; Wherein energy recovery circuit is made up of pMOS pipe P1 and the 2nd pMOS pipe P2; Clamper is made up of nMOS pipe N1 and the 2nd nMOS pipe N2; Be used to avoid output node unsettled; CX is used for control input signals and the auxiliary clock signal introduced; It is to control through the 3rd nMOS pipe N3 and the 4th nMOS pipe N4; The source electrode of the one pMOS pipe P1 and the 2nd pMOS pipe P2 all is connected to power clock end CLK; Substrate is connected on the high level; The drain electrode of the one pMOS pipe P1 is connected with the source electrode of nMOS pipe N1, and the drain electrode of the 2nd pMOS pipe P2 is connected with the source electrode of the 2nd nMOS pipe N2, and the drain electrode of the drain electrode of nMOS pipe N1 and the 2nd nMOS pipe N2 is connected to ground; The drain electrode of the grid of the grid of the 2nd pMOS pipe P2, the 2nd nMOS pipe N2 and pMOS pipe P1 is connected to signal output part OUT; The drain electrode of the grid of the grid of the one pMOS pipe P1, nMOS pipe N1 and the 2nd pMOS pipe P2 is connected to inversion signal output

signal output part OUT and is connected with the source electrode of the 3rd nMOS pipe N3, and the grid of the 3rd nMOS pipe N3 is connected with auxiliary clock signal end CX, and inversion signal output is connected with the source electrode of the 4th nMOS pipe N4; The grid of the 4th nMOS pipe N4 is connected with anti-phase auxiliary clock signal end

; Promptly the 5th nMOS pipe N5, the 6th nMOS manage N6 to the logical assignment circuit, the 7th nMOS manages N7 and the 8th nMOS pipe N8 constitutes by four nMOS transfer tubes, and the source electrode of the 5th nMOS pipe N5 and the source electrode of the 6th nMOS pipe N6 are connected with the drain electrode that the 3rd nMOS manages N3, and the 7th nMOS manages the source electrode of N7 and the source electrode of the 8th nMOS pipe N8 is connected with the drain electrode of the 4th nMOS pipe N4; The drain electrode of the 5th nMOS pipe N5 is connected with the first signal input part IN1; The drain electrode of the 6th nMOS pipe N6 is connected with secondary signal input IN2, and the drain electrode of the 7th nMOS pipe N7 is connected with the 3rd signal input part IN3, and the drain electrode of the 8th nMOS pipe N8 is connected with the 4th signal input part IN4; The grid of the grid of the 5th nMOS pipe N5 and the 8th nMOS pipe N8 is connected to the 5th signal input part IN5, and the grid of the grid of the 6th nMOS pipe N6 and the 7th nMOS pipe N7 is connected to the 6th signal input part IN6.

Single phase clock transfer tube heat insulation logic circuit in the present embodiment only needs to change the assignment of input port, just can obtain 2 inputs as shown in Figure 2 and door, 2 inputs shown in Figure 3 or door and shown in Figure 42 and import XOR gates.

Embodiment two: the graphical diagram of single-phase adiabatic full adder of the present invention is as shown in Figure 5, A, B, C _iBe three addend input ports of full adder; CLK is the power clock end; CX is the auxiliary clock signal end; C is the carry signal output of full adder; S is the summing signal output of full adder, and it produces circuit by carry signal and summing signal generation circuit is formed, and carry signal produces circuit shown in Fig. 6 (a); Promptly the 9th nMOS pipe N9, the tenth nMOS pipe N10, the 11 nMOS pipe N11, the 12 nMOS pipe N12, the 13 nMOS pipe N13, the 14 nMOS pipe N14, the 15 nMOS pipe N15 and the 16 nMOS pipe N16 constitute by the first single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipe; The first single phase clock transfer tube heat insulation logic circuit comprises the first logical assignment circuit and first energy recovery circuit, and first energy recovery circuit is made up of pMOS pipe P1 and the 2nd pMOS pipe P2, and clamper is made up of nMOS pipe N1 and the 2nd nMOS pipe N2; Be used to avoid output node unsettled; The drain electrode of the one pMOS pipe P1 is connected with the source electrode of nMOS pipe N1, and the drain electrode of the 2nd pMOS pipe P2 is connected with the source electrode of the 2nd nMOS pipe N2, and the drain electrode of the drain electrode of nMOS pipe N1 and the 2nd nMOS pipe N2 is connected to ground; The drain electrode of the grid of the grid of the 2nd pMOS pipe P2, the 2nd nMOS pipe N2 and pMOS pipe P1 is connected to carry signal output C, and the grid of the grid of pMOS pipe P1, nMOS pipe N1 and the drain electrode of the 2nd pMOS pipe P2 are connected to anti-phase carry signal output

, carry signal output C is connected anti-phase carry signal output with the source electrode of the 3rd nMOS pipe N3

Be connected with the source electrode of the 4th nMOS pipe N4; Promptly the 5th nMOS pipe N5, the 6th nMOS pipe N6, the 7th nMOS pipe N7 and the 8th nMOS pipe N8 constitute the described first logical assignment circuit by four nMOS transfer tubes; The source electrode of the source electrode of the 5th nMOS pipe N5 and the 6th nMOS pipe N6 is connected with the drain electrode of the 3rd nMOS pipe N3; The source electrode of the source electrode of the 7th nMOS pipe N7 and the 8th nMOS pipe N8 is connected with the drain electrode of the 4th nMOS pipe N4; The source electrode of the source electrode of the drain electrode of the 5th nMOS pipe N5 and the 9th nMOS pipe N9 and the tenth nMOS pipe N10 also connects; The source electrode of the source electrode of the drain electrode of the 6th nMOS pipe N6 and the 11 nMOS pipe N11 and the 12 nMOS pipe N12 also connects; The source electrode of the source electrode of the drain electrode of the 7th nMOS pipe N7 and the 13 nMOS pipe N13 and the 14 nMOS pipe N14 also connects; The source electrode of the source electrode of the drain electrode of the 8th nMOS pipe N8 and the 15 nMOS pipe N15 and the 16 nMOS pipe N16 also connects; Summing signal produces circuit shown in Fig. 6 (b); Promptly the 25 nMOS pipe N25, the 26 nMOS pipe N26, the 27 nMOS pipe N27, the 28 nMOS pipe N28, the 29 nMOS pipe N29, the 30 nMOS pipe N30, the 31 nMOS pipe N31 and the 32 nMOS pipe N32 constitute by the second single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipe; The second single phase clock transfer tube heat insulation logic circuit comprises the second logical assignment circuit and second energy recovery circuit, and second energy recovery circuit is that the 3rd pMOS pipe P3 and the 4th pMOS pipe P4 constitute by two pMOS pipes, and clamper is made up of the 17 nMOS pipe N17 and the 18 nMOS pipe N18; Be used to avoid output node unsettled; The drain electrode of the 3rd pMOS pipe P3 is connected with the source electrode of the 17 nMOS pipe N17, and the drain electrode of the 4th pMOS pipe P2 is connected with the source electrode of the 18 nMOS pipe N18, and the drain electrode of the drain electrode of the 17 nMOS pipe N17 and the 18 nMOS pipe N18 is connected to ground; The drain electrode of the grid of the grid of the 4th pMOS pipe P4, the 18 nMOS pipe N18 and the 3rd pMOS pipe P3 is connected to summing signal output S, and the grid of the grid of the 3rd pMOS pipe P3, the 17 nMOS pipe N17 and the drain electrode of the 4th pMOS pipe P4 are connected to anti-phase summing signal output

, summing signal output S is connected anti-phase summing signal output with the source electrode of the 19 nMOS pipe N19

Be connected with the source electrode of the 20 nMOS pipe N20; Promptly the 21 nMOS pipe N21, the 22 nMOS pipe N22, the 23 nMOS pipe N23 and the 24 nMOS pipe N24 constitute the second logical assignment circuit by four nMOS transfer tubes; The source electrode of the source electrode of the 21 nMOS pipe N20 and the 22 nMOS pipe N20 is connected with the drain electrode of the 19 nMOS pipe N20; The source electrode of the source electrode of the 23 nMOS pipe N20 and the 24 nMOS pipe N20 is connected with the drain electrode of the 20 nMOS pipe N20; The source electrode of the source electrode of the drain electrode of the 21 nMOS pipe N21 and the 25 nMOS pipe N25 and the 26 nMOS pipe N26 also connects; The source electrode of the source electrode of the drain electrode of the 22 nMOS pipe N22 and the 27 nMOS pipe N27 and the 28 nMOS pipe N28 also connects; The source electrode of the source electrode of the drain electrode of the 23 nMOS pipe N23 and the 29 nMOS pipe N29 and the 30 nMOS pipe N30 also connects; The source electrode of the source electrode of the drain electrode of the 24 nMOS pipe N24 and the 31 nMOS pipe N31 and the 32 nMOS pipe N32 also connects; The source electrode of the source electrode of the source electrode of the source electrode of the one pMOS pipe, the 2nd pMOS pipe, the 3rd pMOS pipe and the 4th pMOS pipe is connected to power clock end CLK; The grid of the 3rd nMOS pipe N3 is connected with auxiliary clock signal end CX with the grid of the 19 nMOS pipe N19, grid and the anti-phase auxiliary clock signal end of the grid of the 4th nMOS pipe N4 and the 20 nMOS pipe N20

Connect; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of the grid of the grid of the 6th nMOS pipe N6, the 7th nMOS pipe N7, the 9th nMOS pipe N9, the 11 nMOS pipe N11, the 25 nMOS pipe N25, the 27 nMOS pipe N27, the 29 nMOS pipe N29 and the 31 nMOS pipe N31 is connected to the first addend input A, and the drain electrode of the drain electrode of the grid of the grid of the 5th nMOS pipe N5, the 8th nMOS pipe N8, the drain electrode of the 13 nMOS pipe N13, the 15 nMOS pipe N15, the drain electrode of the 26 nMOS pipe N26, the 28 nMOS pipe N28, the drain electrode of the 30 nMOS pipe N30 and the drain electrode of the 32 nMOS pipe N32 are connected to the first addend inverting input

The grid of the grid of the grid of the grid of the grid of the grid of the grid of the grid of the tenth nMOS pipe N10, the 11 nMOS pipe N11, the 13 nMOS pipe N13, the 16 nMOS pipe N16, the 26 nMOS pipe N26, the 27 nMOS pipe N27, the 30 nMOS pipe N30 and the 31 nMOS pipe N31 is connected to the second addend input B, and the grid of the grid of the grid of the grid of the 9th nMOS pipe N9, the 12 nMOS pipe N12, the grid of the 14 nMOS pipe N14, the 15 nMOS pipe N15, the grid of the 25 nMOS pipe N25, the 28 nMOS pipe N28, the grid of the 29 nMOS pipe N29 and the grid of the 32 nMOS pipe N32 are connected to the second addend inverting input

The grid of the grid of the drain electrode of the drain electrode of the tenth nMOS pipe N10, the 12 nMOS pipe N12, the 22 nMOS pipe N22 and the 23 nMOS pipe N23 is connected to the 3rd addend input Ci, and the grid of the drain electrode of the drain electrode of the 14 nMOS pipe N14, the 16 nMOS pipe N16, the grid of the 21 nMOS pipe N21 and the 24 nMOS pipe N24 is connected to the 3rd addend inverting input

Full adder circuit than static CMOS full adder circuit and CAL logic; The structure of single-phase adiabatic full adder circuit of the present invention is rule very, and it is the same with the logical construction that summing signal produces circuit basically that carry signal produces circuit, and just the assignment of input port is different; Thereby produce different output; Design is just very simple like this, only needs one of them structure of design to get final product, and area can reduce greatly.

Embodiment three: the structure of single-phase adiabatic 5-2 compressor reducer of the present invention is shown in figure 10, and its basic principle is with 7 numbers (five actual input data I 1, I2, I3; I4, I5, two carry input Cin1, Cin2) addition produces 4 number Sum; Carry, Cout1, Cout2 output, wherein carry Cout1; Cout2 can be to the next stage transmission, but as the input signal Cin1 of an adjacent high position, Cin2, thus realize the 5-2 compression function.It is formed by the first full adder I, the second full adder II and the 3rd full adder III cascade; The first addend input A1 of the first full adder I is connected with first input signal I1; The second addend input B1 of the first full adder I is connected with second input signal I2, the 3rd addend input C of the first full adder I _i1 is connected with the 3rd input signal I3; The carry signal output C1 of the first full adder I exports the first carry output signals Cout1 and gives next stage 5-2 compressor reducer as the first carry input signal; The first addend input A2 of the second full adder II is connected with the first carry input signal Cin1 of the carry signal output of first full adder of upper level 5-2 compressor reducer output; The second addend input B2 of the second full adder II is connected with the summing signal output S1 of the first full adder I, the 3rd addend input C of the second full adder II _i2 are connected with the 4th input signal I4; The carry signal output C2 of the second full adder II exports the second carry output signals Cout2 and gives next stage 5-2 compressor reducer as the second carry input signal; The first addend input A3 of the 3rd full adder III is connected with the second carry input signal Cin2 of the carry signal output of second full adder of upper level 5-2 compressor reducer output; The second addend input B3 of the 3rd full adder III is connected with the summing signal output S2 of the second full adder II, the 3rd addend input C of the 3rd full adder III _i3 are connected with the 5th input signal I5, the carry signal Carry of the carry signal output C3 output 5-2 compressor reducer of the 3rd full adder III, the summing signal Sum of the summing signal output S3 output 5-2 compressor reducer of the 3rd full adder III.

The functional verification formula of 5-2 compressor reducer is following:

$\mathrm{Sum}=I1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">I</figure-callout>}2\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png,HDA0000026619960000052.png"\; state="\{\{state\}\}">I</figure-callout>}3\&CirclePlus;I4\&CirclePlus;I5\&CirclePlus;\mathrm{Cin}1\&CirclePlus;\mathrm{Cin}2---\left(3\right)$

$\mathrm{Carry}=(I1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">I</figure-callout>}2\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png,HDA0000026619960000052.png"\; state="\{\{state\}\}">I</figure-callout>}3\&CirclePlus;I4\&CirclePlus;I5\&CirclePlus;\mathrm{Cin}1)\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="Cin"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">Cin</figure-callout>}2+\stackrel{\&OverBar;}{(I1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">I</figure-callout>}2\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png,HDA0000026619960000052.png"\; state="\{\{state\}\}">I</figure-callout>}3\&CirclePlus;I4\&CirclePlus;\mathrm{Cin}1)}\&CenterDot;I5---\left(4\right)$

$\mathrm{Cout}1=(I1\&CirclePlus;I2)\&CenterDot;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png,HDA0000026619960000052.png"\; state="\{\{state\}\}">I</figure-callout>}3+\stackrel{\&OverBar;}{(I1+I2)}\&CenterDot;I1---\left(5\right)$

$\mathrm{<figure-callout\; id="2"\; label="Cout"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">Cout</figure-callout>}2=(I1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">I</figure-callout>}2\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png,HDA0000026619960000052.png"\; state="\{\{state\}\}">I</figure-callout>}3\&CirclePlus;I4)\&CenterDot;\mathrm{Cin}1+\stackrel{\&OverBar;}{(I1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">I</figure-callout>}2\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png,HDA0000026619960000052.png"\; state="\{\{state\}\}">I</figure-callout>}3\&CirclePlus;I4)}\&CenterDot;I4---\left(6\right)$

The single-phase adiabatic full adder circuit that our utilization has been designed through the 5-2 compressor configuration sketch map of Figure 10, just can very simply make up the single-phase adiabatic 5-2 compressor circuit that obtains us.Figure 11 is a 5-2 compressor reducer functional simulation waveform, and the functional verification formula of utilization 5-2 compressor reducer is verified it, can know that it is functional, can realize the 5-2 compressor circuit of single-phase power clock control.

Claims (3)

1. single phase clock transfer tube heat insulation logic circuit; It is characterized in that comprising logical assignment circuit and energy recovery circuit; Described energy recovery circuit is that pMOS pipe and the 2nd pMOS pipe constitute by two pMOS pipes; The source electrode of the source electrode of described pMOS pipe and described the 2nd pMOS pipe is connected to the power clock end; The drain electrode of described pMOS pipe is connected with the source electrode of nMOS pipe; The drain electrode of described the 2nd pMOS pipe is connected with the source electrode of the 2nd nMOS pipe; The drain electrode of the drain electrode of described nMOS pipe and described the 2nd nMOS pipe is connected to ground; The drain electrode of the grid of the grid of described the 2nd pMOS pipe, described the 2nd nMOS pipe and described pMOS pipe is connected to signal output part, and the grid of the grid of described pMOS pipe, described nMOS pipe and the drain electrode of described the 2nd pMOS pipe are connected to the inversion signal output, and described signal output part is connected with the source electrode of the 3rd nMOS pipe; The grid of described the 3rd nMOS pipe is connected with the auxiliary clock signal end; Described inversion signal output is connected with the source electrode of the 4th nMOS pipe, and the grid of described the 4th nMOS pipe is connected with anti-phase auxiliary clock signal end, and promptly the 5th nMOS pipe, the 6th nMOS pipe, the 7th nMOS pipe and the 8th nMOS pipe constitute described logical assignment circuit by four nMOS transfer tubes; The source electrode of the source electrode of described the 5th nMOS pipe and the 6th nMOS pipe is connected with the drain electrode of described the 3rd nMOS pipe; The source electrode of the source electrode of described the 7th nMOS pipe and described the 8th nMOS pipe is connected with the drain electrode of described the 4th nMOS pipe, and the drain electrode of described the 5th nMOS pipe is connected with first signal input part, and the drain electrode of described the 6th nMOS pipe is connected with the secondary signal input; The drain electrode of described the 7th nMOS pipe is connected with the 3rd signal input part; The drain electrode of described the 8th nMOS pipe is connected with the 4th signal input part, and the grid of the grid of described the 5th nMOS pipe and described the 8th nMOS pipe is connected to the 5th signal input part, and the grid of the grid of described the 6th nMOS pipe and described the 7th nMOS pipe is connected to the 6th signal input part.

2. full adder that uses the described single phase clock transfer tube of claim 1 heat insulation logic circuit is characterized in that comprising that carry signal produces circuit and produces circuit with summing signal, and described carry signal produces circuit, and promptly the 9th nMOS pipe, the tenth nMOS pipe, the 11 nMOS pipe, the 12 nMOS pipe, the 13 nMOS pipe, the 14 nMOS pipe, the 15 nMOS pipe and the 16 nMOS manage and constitute by the first single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipes; The described first single phase clock transfer tube heat insulation logic circuit comprises the first logical assignment circuit and first energy recovery circuit, and described first energy recovery circuit is that pMOS pipe and the 2nd pMOS pipe constitute by two pMOS pipes, and the drain electrode of described pMOS pipe is connected with the source electrode of nMOS pipe; The drain electrode of described the 2nd pMOS pipe is connected with the source electrode of the 2nd nMOS pipe, and the drain electrode of the drain electrode of described nMOS pipe and described the 2nd nMOS pipe is connected to ground, and the grid of the grid of described the 2nd pMOS pipe, described the 2nd nMOS pipe and the drain electrode of described pMOS pipe are connected to the carry signal output; The drain electrode of the grid of the grid of described pMOS pipe, described nMOS pipe and described the 2nd pMOS pipe is connected to anti-phase carry signal output, and described carry signal output is connected with the source electrode of the 3rd nMOS pipe, and described anti-phase carry signal output is connected with the source electrode of the 4th nMOS pipe; Promptly the 5th nMOS pipe, the 6th nMOS manage the described first logical assignment circuit, the 7th nMOS manages and the 8th nMOS pipe constitutes by four nMOS transfer tubes, and the source electrode of the source electrode of described the 5th nMOS pipe and the 6th nMOS pipe is connected with the drain electrode that described the 3rd nMOS manages, and the source electrode of source electrode that described the 7th nMOS manages and described the 8th nMOS pipe is connected with the drain electrode of described the 4th nMOS pipe; The source electrode of the source electrode of the drain electrode of described the 5th nMOS pipe and described the 9th nMOS pipe and described the tenth nMOS pipe also connects, and the source electrode of the drain electrode of described the 6th nMOS pipe and described the 11 nMOS pipe and the source electrode of described the 12 nMOS pipe also connect, and the source electrode of the drain electrode of described the 7th nMOS pipe and described the 13 nMOS pipe and the source electrode of described the 14 nMOS pipe also connect; The drain electrode of described the 8th nMOS pipe also connects with the source electrode of described the 15 nMOS pipe and the source electrode of described the 16 nMOS pipe, described summing signal produce circuit by the second single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipes promptly the 25 nMOS pipe, the 26 nMOS pipe, the 27 nMOS pipe, the 28 nMOS pipe, the 29 nMOS pipe, the 30 nMOS pipe, the 31 nMOS pipe and the 32 nMOS manage and constitute, the described second single phase clock transfer tube heat insulation logic circuit comprises the second logical assignment circuit and second energy recovery circuit; Described second energy recovery circuit is that the 3rd pMOS pipe and the 4th pMOS pipe constitute by two pMOS pipes, and the drain electrode of described the 3rd pMOS pipe is connected with the source electrode of the 17 nMOS pipe, and the drain electrode that described the 4th pMOS manages is connected with the source electrode of the 18 nMOS pipe; The drain electrode of the drain electrode of described the 17 nMOS pipe and described the 18 nMOS pipe is connected to ground, and the grid of the grid of described the 4th pMOS pipe, described the 18 nMOS pipe and the drain electrode of described the 3rd pMOS pipe are connected to the summing signal output, and the grid of the grid of described the 3rd pMOS pipe, described the 17 nMOS pipe and the drain electrode of described the 4th pMOS pipe are connected to anti-phase summing signal output; Described summing signal output is connected with the source electrode of the 19 nMOS pipe; Described anti-phase summing signal output is connected with the source electrode of the 20 nMOS pipe, and promptly the 21 nMOS pipe, the 22 nMOS manage the described second logical assignment circuit, the 23 nMOS manages and the 24 nMOS pipe constitutes by four nMOS transfer tubes, and the source electrode of the source electrode of described the 21 nMOS pipe and the 22 nMOS pipe is connected with the drain electrode that described the 19 nMOS manages; The source electrode of the source electrode of described the 23 nMOS pipe and the 24 nMOS pipe is connected with the drain electrode of described the 20 nMOS pipe; The source electrode of the source electrode of the drain electrode of described the 21 nMOS pipe and described the 25 nMOS pipe and described the 26 nMOS pipe also connects, and the source electrode of the drain electrode of described the 22 nMOS pipe and described the 27 nMOS pipe and the source electrode of described the 28 nMOS pipe also connect, and the source electrode of the drain electrode of described the 23 nMOS pipe and described the 29 nMOS pipe and the source electrode of described the 30 nMOS pipe also connect; The source electrode of the source electrode of the drain electrode of described the 24 nMOS pipe and described the 31 nMOS pipe and described the 32 nMOS pipe also connects; The source electrode of the source electrode of the source electrode of the source electrode of described pMOS pipe, described the 2nd pMOS pipe, described the 3rd pMOS pipe and described the 4th pMOS pipe is connected to the power clock end, and the grid of described the 3rd nMOS pipe is connected with the auxiliary clock signal end with the grid of described the 19 nMOS pipe, and the grid of described the 4th nMOS pipe is connected with anti-phase auxiliary clock signal end with the grid of described the 20 nMOS pipe; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of the grid of the grid of described the 6th nMOS pipe, described the 7th nMOS pipe, described the 9th nMOS pipe, described the 11 nMOS pipe, described the 25 nMOS pipe, described the 27 nMOS pipe, described the 29 nMOS pipe and described the 31 nMOS pipe is connected to the first addend input; The drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of the drain electrode of the grid of the grid of described the 5th nMOS pipe, described the 8th nMOS pipe, described the 13 nMOS pipe, described the 15 nMOS pipe, described the 26 nMOS pipe, described the 28 nMOS pipe, described the 30 nMOS pipe and described the 32 nMOS pipe is connected to the first addend inverting input, and the grid of the grid of described the tenth nMOS pipe, the grid of described the 11 nMOS pipe, the grid of described the 13 nMOS pipe, the grid of described the 16 nMOS pipe, the grid of described the 26 nMOS pipe, the grid of described the 27 nMOS pipe, described the 30 nMOS pipe and the grid of described the 31 nMOS pipe are connected to the second addend input, and the grid of the grid of described the 9th nMOS pipe, the grid of described the 12 nMOS pipe, the grid of described the 14 nMOS pipe, the grid of described the 15 nMOS pipe, the grid of described the 25 nMOS pipe, the grid of described the 28 nMOS pipe, described the 29 nMOS pipe and the grid of described the 32 nMOS pipe are connected to the second addend inverting input; The grid of the grid of the drain electrode of the drain electrode of described the tenth nMOS pipe, described the 12 nMOS pipe, described the 22 nMOS pipe and described the 23 nMOS pipe is connected to the 3rd addend input, and the grid of the drain electrode of described the 14 nMOS pipe, the drain electrode of described the 16 nMOS pipe, described the 21 nMOS pipe and the grid of described the 24 nMOS pipe are connected to the 3rd addend inverting input.

3. 5-2 compressor reducer that uses the described full adder of claim 2; It is characterized in that it is formed by first full adder, second full adder and the 3rd full adder cascade; The first addend input of described first full adder is connected with first input signal; The second addend input of described first full adder is connected with second input signal; The 3rd addend input of described first full adder is connected with the 3rd input signal; The first addend input of described second full adder is connected with the carry signal output of first full adder of upper level 5-2 compressor reducer; The second addend input of described second full adder is connected with the summing signal output of described first full adder, and the 3rd addend input of described second full adder is connected with the 4th input signal, and the first addend input of described the 3rd full adder is connected with the carry signal output of second full adder of upper level 5-2 compressor reducer; The second addend input of described the 3rd full adder is connected with the summing signal output of described second full adder; The 3rd addend input of described the 3rd full adder is connected with the 5th input signal, the carry signal of the carry signal output output 5-2 compressor reducer of described the 3rd full adder, the summing signal of the summing signal output output 5-2 compressor reducer of described the 3rd full adder.

Images