WO2014012005A1

WO2014012005A1 - Adiabatic logic family

Info

Publication number: WO2014012005A1
Application number: PCT/US2013/050298
Authority: WO
Inventors: Mlhail CUTITARU; Lee BELFORE
Original assignee: Old Dominion University Research Foundation
Priority date: 2012-07-13
Filing date: 2013-07-12
Publication date: 2014-01-16

Abstract

An adiabatic logic family that is suitable for use with a dual-phase sinusoidal power clock as the driver. The core of all circuits in this family consists of two pMOS transistors, PI and P2, and two nMOS transistors, N3 and N4, These transistors provide the drive that provides the circuit outputs, which are complementary outputs in all cases. The logic function and its complement are specified by nMOS switching circuits that connect to N3 and N4 respectively. Unlike other adiabatic families, where the logic function switching networks are in the same path as the output networks, the proposed family decouples the logic function from the core driver circuit. The adiabatic logic family can achieve substantial reductions in energy dissipation when compared to traditional CMOS circuits.

Description

ADIABATIC LOGIC FAMILY

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Patent Application No.

61/671 ,462, filed July 13, 2012, which is hereby incorporated in its entirety.

STATEMENT REGARDING GOVERNMENT SUPPORT

[0002] Not applicable.

FIELD OF THE INVENTION

[0003] The present invention relates to adiabatic logic circuits,

BACKGROUND

[0004] Current conventional Complementary Metal-Oxide-Semiconductor (CMOS) technology uses a square-wave clock as a driver for CMOS circuits. This process leads to a loss of energy which is discharged as heat once the result of a calculation is no longer needed. A different kind of computing (calied adiabatic computing) which works with CMOS transistors but is able to recover some or most of the energy input in the system has been investigated by some researchers. While there is a difference in operating frequencies (usually up to the range of a few GHz for regular CMOS and several hundred MHz for adiabatic circuits), adiabatic circuits have applications in lower-power computing environments.

[0005] Adiabatic logic families that have been described include l nl p, 2n2p, 2n-

2n2p, PAL2n2p, 2n-2n2p, PAL, and TSEL. The l n l p quasi -adiabatic logic family uses the same setup as a CMOS inverter, but uses a single-phase sinusoidal driver that oscillates between Ground (GND) and W^- This logic family is not suitable for pipelining, and requires the input to be stable for the entire time of computing the output in order to have valid data. A diagram of a l n l p inverter is shown in Figure 1 . The 2n2p logic family uses two nMOS and two pMOS transistors to achieve adiabatic operation and compute a logic function and its complement given an input and its complement. The two pMOS transistors are cross-coupled, guaranteeing that the two outputs will always be complementary. A diagram of a 2n2p inverter is shown in Figure 2. The 2n-2n2p family is a variation of the diagram of a 2n2p inverter is shown in Figure 2. The 2n-2n2p family is a variation of the 2n2p family and consists of two new cross-coupled nMOS transistors added in parallel to the two nMOS transistors. The new nMOS pair makes the 2n-2n2p act as a full inverter and is similar to a Static Random-Access Memory (SRAM) cell. A diagram of a 2n-2n2p inverter is shown in Figure 3. Pass-Transistor Adiabatic Logic (PAL) is another variation of the 2n2p logic family. In this family, instead of having the lowest node connect to GND, it is connected to the power clock, allowing for fully adiabatic operation. Another difference between the two families is that PAL uses a two-phase sinusoidal power clock, which allows for simpler implementation and potentially higher power savings. A diagram of a PAL inverter is shown in Figure 4. The True Single-Phase Energy-Recovery Logic (TSEL) logic fami ly is similar to the 2n-2n2p family. This family uses a single-phase sinusoidal power clock with cascades made up of alternating pMOS and nMOS gates. Some of these families have been patented (see, e.g., U.S. Patent Nos.: 5,378,940, 5,459,414, and 6,3 16,962), but the operation and interconnections of the proposed family is different than the other families. Unlike other adiabatic families, where the logic function switching networks are in the same path as the output networks, the proposed family decouples these parts of the circuit. The patents mentioned above also mostly use a multi-phase clock (4- and 8-phase) instead of, e.g., a dual-phase sinusoidal clock.

SUMMARY

[0006] Disclosed is a new adiabatic logic family that is suitable for use with dual- phase sinusoidal complementary clocks as the driver, where alternate gates are controlled by alternate clocks. The core of all circuits in this family consists of two pMOS transistors, PI and P2, and two nMOS transistors, N3 and N4. These transistors provide the drive that provides the circuit outputs. As with all adiabatic logic families in the literature, the circuit provides complementary outputs in all cases. The logic function and its complement are specified by nMOS switching circuits that connect to N3 and N4 respectively. The adiabatic logic family can achieve substantial reductions in energy dissipation when compared to traditional CMOS circuits because the switching networks permit charge stored in lumped gate capacitance to be returned to the power supply.

[0007] An adiabatic logic circuit includes a circuit core, primary and complementary logic portions, and a periodic power clock configured to drive the circuit. The circuit core includes a first p-type transistor PI, a second p-type transistor P2, a first n-type transistor N3, and a second n-type transistor N4. The primary and complementary logic portions are configured to perform a logic function and its complement, respectively. The adiabatic logic circuit is configured such that the primary logic portion is logically decoupled from the circuit core.

[0008] The periodic power clock can be, e.g., a sinusoidal power clock such as a dual- phase sinusoidal complementary power clock. The adiabatic circuit can comprise, e.g., an inverter, an XOR gate, an AND gate, an OR gate, a full-adder circuit, or any other logical circuit.

[0009] The source terminals of each of the PI and P2 transistors are connected to the power clock. The source terminals of each of the N3 and N4 transistors are connected to ground. The drain terminals of PI and N3 are connected to one another and to a gate terminal of P2 and define an output node of the adiabatic logic circuit. The drain terminals of P2 and N4 are connected to one another and define a complementary output node of the adiabatic logic circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a circuit diagram of a prior art In 1 p inverter.

[001 1 ] Figure 2 is a circuit diagram of a prior art 2n2p inverter.

[0012] Figure 3 is a circuit diagram of a prior art 2n-2n2p inverter.

[0013] Figure 4 is a circuit diagram of a prior art PAL inverter.

[0014] Figure 5 is a circuit diagram of an adiabatic buffer / inverter according to one embodiment of the present invention.

[0015] Figure 6 is a graph showing the results of a simulation comparing the power consumption of the adiabatic buffer / inverter of Figure 5 with that of a conventional CMOS inverter circuit.

[0016] Figure 7 is a circuit diagram of an XOR gate according to one embodiment of the present invention. [0017] Figure 8 is a circuit diagram of an AND gate according to one embodiment of the present invention.

[0018] Figure 9 is a graph showing the results of a simulation comparing the power consumption of a full-adder circuit implemented using the XOR and AND gates of Figures 3 and 4 with that of a traditional CMOS full-adder circuit.

[0019] Figure 10 is a circuit schematic for an OR gate according to one embodiment of the present invention.

[0020] Figure 1 1 is a circuit schematic for a full adder circuit.

DESCRIPTION

[0021] An adiabatic logic family is proposed that achieves very good energy recovery characteristics. In certain embodiments, the adiabatic logic family is used with dual-phase complementary sinusoidal Power Clocks (PCs). In other embodiments, other drivers and waveforms may be used such as, for example, a trapezoidal waveform, rectangular waveform, sawtooth wavefonn, single-phase sinusoidal clock, or any other type of periodic clock.

[0022] Figure 5 shows a circuit diagram of an adiabatic buffer / inverter according to one embodiment of the present invention. The inverter of Figure 5 includes a circuit core comprising two pMOS transistors, PI and P2, and two nMOS transistors, N3 and N4. This circuit core is common to all of the circuits in the proposed adiabatic logic family. Each of the pMOS transistors, PI and P2, has its source tenninal connected to Power Clock, PC. Power Clock PC can be, e.g., a dual-phase sinusoidal power clock. Each of the nMOS transistors, N3 and N4, has its source terminal connected to GND. The drain terminals of transistors PI and N3 are connected together and to the gate of transistor P2, and this node provides an output of the circuit, out. The drain terminals of transistors P2 and N4 are connected together and to the gate of transistor PI, and this node provides the complementary output of the circuit In addition to the circuit core, the circuits of the present adiabatic family also include a primary logic portion configured to perfonn a logic function, and a complementary logic portion configured to perfonn its complement. The primary and complementary logic portions are each implemented using one or more nMOS transistors. In the case of the inverter circuit shown in Figure 5, the primary logic portion consists of a single transistor Nl that is provided with an input in at its gate. The complementary logic portion consists of a single transistor N2 that is provided with complementary input in at its gate. The output of the primary logic portion is provided to and controls the operation of transistor N3. The output of the complementary logic portion is provided to and controls the operation of transistor N4,

[0023] Still referring to the inverter circuit shown in Figure 5, when the PC swings from

GND to V_dd, the value in the in input get assigned to the ^out output and in gets assigned to the out output, achieving the inverter function. Assuming that in is at V_dd and in is at GND, in will cause N3 to turn ON and out to be at GND level. When out is at GND, P2 is enabled, allowing ^out to follow the PC to V_dd level. On the down-cycle, since out is at GND level,

P2 is enabled, allowing for the energy stored in ^out to be recovered. When the values of the inputs are swapped, the output values are swapped as well,

[0024] For the buffer inverter circuit shown in Figure 5, the transistors N1/N2 provide the controls for the operation of the gate as a whole. The two transistors, Nl and N2 can be replaced by any other switching network composed of nMOS transistors that implements a desired function and its complement function. When one of the two transistors is ON (e.g. l ), transistor N3 will turn ON once the voltage is past the threshold and set node out to GND. This will enable P2 and result in the output out following the PC to V_dd. The current configuration requires the inputs to be stable and complementary for the duration of the clock cycle to guarantee correct operation. If one of the inputs changes from 0 to 1 , there will be an erroneous output because the corresponding transistor will be set to ON and the charge will be dissipated to the GND. If there is a change in an input from 1 to 0 (while the other input stays at 0), the output will not change and the gate operates correctly.

[0025] Unlike other adiabatic families, where the logic function switching networks are in the same path as the output networks, the proposed family decouples the logic function from the core driver circuit. Thus, the circuit's primary logic portion is logically decoupled from the circuit core.

[0026] The power consumption of a buffer / inverter as implemented in Figure 5 and of a conventional CMOS circuit were calculated with a Simulation Program with Integrated Circuit Emphasis (or SPICE simulation)., A 0.25um process was used with a W/L of 0.36pm/0.24um respectively and the PC a sinusoidal clock oscillating between OV and 1.8V, The results of the simulation for a square waveform input at various frequencies are shown in Figure 6. As it can be seen from the simulation results, the adiabatic inverter has a level of energy dissipation about 68% lower than a CMOS inverter at 100MHz.

[0027] In order to test the scalability of the new family, a full-adder circuit was built and again compared with its CMOS version. The full-adder was implemented with AND and XOR gates. Figure 7 shows the implementation of the XOR gate and Figure 8 shows the AND gate. Figure 1 1 shows the implementation of the full-adder ci rcuit.

[0028] An energy comparison was done for both full-adders and the results are shown in

Figure 9. Since the adiabatic gates use both a given input and its complement, additional circuitry in the form of inverters was added in order to make the full-adder produce the correct outputs. Even with the additional circuitry the adiabatic implementation achieves an energy decrease of around 69%.

[0029] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown, and that the invention has other applications in other environments. This application is intended to cover any such adaptations or variations of the present invention.

Claims

CLAIMS WHAT IS CLAIMED IS:

1 . An adiabatic logic circuit comprising:

a circuit core comprising a first p-type transistor PI, a second p-type transistor P2, a first n-type transistor N3, and a second n-type transistor N4;

a primary logic portion configured to perform a logic function;

a complementary logic portion configured to perform a complement of said logic function; and

a periodic power clock configured to drive the adiabatic logic circuit;

wherein the adiabatic logic circuit is configured such that the primary logic portion is logically decoupled from the circuit core.

2. The adiabatic logic circuit of Claim 1, wherein said periodic power clock comprises a sinusoidal power clock.

3. The adiabatic logic circuit of Claim 2, wherein said sinusoidal power clock comprises a dual-phase sinusoidal complementary power clock.

4. The adiabatic logic circuit of Claim 1 , wherein said adiabatic logic circuit comprises an inverter.

5. The adiabatic logic circuit of Claim 4, wherein said adiabatic logic circuit achieves an energy dissipation rate of less than about 1.50 E-l 5 W when operated in a frequency range of between about l Hz and about 100MHz.

6. The adiabatic logic circuit of Claim 1 , wherein said adiabatic logic circuit comprises an XOR gate.

7. The adiabatic logic circuit of Claim 1 , wherein said adiabatic logic circuit comprises an AND gate.

8. The adiabatic logic circuit of Claim 1 , wherein said adiabatic logic circuit comprises an OR gate.

9. The adiabatic logic circuit of Claim 1 , wherein said primary logic portion and said complementary logic portion comprise nMOS-type switching circuits.

10. The adiabatic logic circuit of Claim 1, wherein a source terminal of each of PI and P2 is connected to said periodic power clock, a source terminal of each of N3 and N4 is connected to ground, drain terminals of P I and N3 are connected to one another and to a gate terminal of P2 and define an output node of the adiabatic logic circuit, and drain terminals of P2 and N4 are connected to one another and to a gate of PI and define a complementary output node of the adiabatic logic circuit.

1 1 . The adiabatic logic circuit of Claim 1 , wherein said adiabatic logic circuit comprises a full adder circuit.

12. The adiabatic logic circuit of Claim 1 1 , wherein said adiabatic logic circuit achieves an energy dissipation rate of less than about 1.50E-14 W when operated in a frequency range of between about l MHz and about 100MHz.