CN204633750U - The ring oscillator of self-adapting start - Google Patents
The ring oscillator of self-adapting start Download PDFInfo
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- CN204633750U CN204633750U CN201520181975.9U CN201520181975U CN204633750U CN 204633750 U CN204633750 U CN 204633750U CN 201520181975 U CN201520181975 U CN 201520181975U CN 204633750 U CN204633750 U CN 204633750U
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Abstract
The utility model provides a kind of ring oscillator of self-adapting start, described ring oscillator comprises pierce circuit, starting of oscillation testing circuit and feedback loop, described pierce circuit comprises vibration end and output, and it is for generation of also passing through its output clock signal; Whether whether described starting of oscillation testing circuit judges the starting of oscillation of described pierce circuit based on the clock signal that described pierce circuit exports, and export the detection signal representing the starting of oscillation of described pierce circuit; Described feedback loop exports corresponding starting of oscillation signal to the vibration end of described pierce circuit based on described detection signal.Compared with prior art, the ring oscillator in the utility model adopts adaptive algorithm, does not need system intervention, utilizes the feedback mechanism of oscillator inside to start ring oscillator, does not need system to send pulse and starts, thus simplify System design.
Description
[technical field]
The utility model relates to integrated circuit (IC) design field, particularly a kind of ring oscillator of self-adapting start and the delay cell with start-up circuit wherein.
[background technology]
The starting problem of ring oscillator exists always, and in prior art, common mode processes this thing by arranging a system pulses.Although system pulses shock oscillator can solve the starting problem of ring oscillator, following shortcoming can be brought:
1, the time needing default special, to oscillator shock pulse, understands occupying system resources like this;
2, because system shock is just to a shock pulse, if system shock pulse was lost efficacy under certain conditions, system cannot obtain the current state of oscillator, and therefore, if one-shot is unsuccessful, system can not send out shock pulse again.Like this, still there is the possibility that cannot normally start in ring oscillator.
Therefore, be necessary to provide a kind of technical scheme of improvement to overcome the problems referred to above.
[utility model content]
The purpose of this utility model is to provide a kind of ring oscillator of self-adapting start and the delay cell with start-up circuit wherein, it adopts adaptive algorithm, do not need system intervention, utilize the feedback mechanism of oscillator inside to start ring oscillator, do not need system to send pulse to start, thus simplify System design.
In order to solve the problem, the utility model provides a kind of ring oscillator of self-adapting start, and it comprises pierce circuit, starting of oscillation testing circuit and feedback loop.Described pierce circuit comprises vibration end and output, and it is for generation of also passing through its output clock signal; Whether whether described starting of oscillation testing circuit judges the starting of oscillation of described pierce circuit based on the clock signal that described pierce circuit exports, and export the detection signal representing the starting of oscillation of described pierce circuit; Described feedback loop exports corresponding starting of oscillation signal to the vibration end of described pierce circuit based on described detection signal.
Further, if described starting of oscillation testing circuit detects the starting of oscillation of described pierce circuit, it exports the detection signal representing starting of oscillation, and described feedback loop exports disable starting of oscillation signal based on this, and described pierce circuit normally works; If described starting of oscillation testing circuit detects the non-starting of oscillation of described pierce circuit, it exports and represents the detection signal of non-starting of oscillation, described feedback loop based on the detection signal output enable starting of oscillation signal of the non-starting of oscillation of this expression, to make described pierce circuit starting of oscillation.
Further, described pierce circuit comprises the delay cell of at least two cascades.Wherein, at least one delay cell is the delay cell with start-up circuit, the described delay cell with start-up circuit comprises differential delay circuit and start-up circuit, described differential delay circuit comprises the first delayed branch and the second delayed branch, and described first delayed branch comprises the in-phase input end for receiving differential signal and the in-phase output end for output difference sub-signal; Second delayed branch comprises the inverting input for receiving differential signal and the reversed-phase output for output difference sub-signal; The second output that described start-up circuit comprises Enable Pin, the first output be connected with in-phase input end and is connected with inverting input, when described Enable Pin receives enable starting of oscillation signal, described start-up circuit exports a pair differential signal by its first output and the second output, when described Enable Pin receives disable starting of oscillation signal, described start-up circuit does not work, described in there is the vibration end of Enable Pin as described ring oscillator of the delay cell of start-up circuit.
Further, in described pierce circuit, except the delay cell with start-up circuit, the structure of remaining each delay unit is identical with the structure of the described differential delay circuit had in the delay cell of start-up circuit.
Further, described start-up circuit comprises PMOS transistor MP0A and MP1A, nmos pass transistor MN0A and MN1A, described Enable Pin comprises the first enable port START_P and the second enable port START_N, described PMOS transistor MP1A and nmos pass transistor MN1A is connected between power end V/I_SUPPLY and earth terminal VSS successively, the grid of PMOS transistor MP1A is connected with high level HIGH, the grid of nmos pass transistor MN1A is as the second enable port START_N, connected node between described PMOS transistor MP1A and nmos pass transistor MN1A is as described first output, described PMOS transistor MP0A and nmos pass transistor MN0A is connected between power end V/I_SUPPLY and earth terminal VSS successively, the grid of PMOS transistor MP0A is as the first enable port START_P, the grid of nmos pass transistor MN0A is connected with low level LOW, and the connected node between described PMOS transistor MP0A and nmos pass transistor MN0A is as the second output.
Further, described first delayed branch comprises the first inverter, described first inverter comprises and is connected to PMOS transistor MP1 between power end V/I_SUPPLY and earth terminal VSS and nmos pass transistor MN1 successively, the grid of described PMOS transistor MP1 is connected with the in-phase input end INP of the connected node of the grid of nmos pass transistor MN1 with described first delayed branch, and the connected node between the drain electrode of described PMOS transistor MP1 and the drain electrode of nmos pass transistor MN1 is connected with the in-phase output end VON of described first delayed branch; Described second delayed branch comprises the second inverter, described second inverter comprises and is connected to PMOS transistor MP0 between power end V/I_SUPPLY and earth terminal VSS and nmos pass transistor MN0 successively, the grid of described PMOS transistor MP0 is connected with the inverting input INN of the connected node of the grid of nmos pass transistor MN0 with described second delayed branch, and the connected node between the drain electrode of described PMOS transistor MP0 and the drain electrode of nmos pass transistor MN0 is connected with the reversed-phase output VOP of described second delayed branch.
Further, described differential delay circuit also comprises nmos pass transistor MN0B and MN1B, the drain electrode of described nmos pass transistor MN0B is connected with the connected node between the drain electrode of described PMOS transistor MP0 and the drain electrode of nmos pass transistor MN0, its source electrode is connected with earth terminal VSS, and the connected node between the drain electrode of its grid and PMOS transistor MP1 and the drain electrode of nmos pass transistor MN1 is connected; The drain electrode of described nmos pass transistor MN1B is connected with the connected node between the drain electrode of described PMOS transistor MP1 and the drain electrode of nmos pass transistor MN1, its source electrode is connected with earth terminal VSS, and the connected node between the drain electrode of its grid and PMOS transistor MP0 and the drain electrode of nmos pass transistor MN0 is connected.
Further, described pierce circuit comprises the delay cell of even number cascade, the in-phase output end of previous stage delay cell and reversed-phase output connect in-phase input end and the inverting input of rear stage delay cell, and the in-phase output end of afterbody delay cell and reversed-phase output connect inverting input and the in-phase input end of first order delay cell respectively.
Further, whether described starting of oscillation testing circuit is by detecting the frequency of the clock signal of described pierce circuit output higher than the threshold value preset, to determine the whether starting of oscillation of described pierce circuit, when the frequency of described clock signal being detected higher than the threshold value preset, described starting of oscillation testing circuit exports the first logic level; When the frequency of described clock signal being detected lower than the threshold value preset, described starting of oscillation testing circuit exports the second logic level.
Further, described starting of oscillation testing circuit comprises delayer, XOR gate, inverter INV1, PMOS transistor MP4, current source I1, resistance R1 and electric capacity C1 and Schmidt trigger Smith Trigger, the input of described delayer is connected with the input of described starting of oscillation testing circuit, the output of delayer is connected with the first input end of XOR gate, second input of XOR gate is connected with the input of described starting of oscillation testing circuit, and the output of XOR gate is connected with the input of inverter INV1; The positive pole of current source I1 is connected with power end VDD, its negative pole is connected with the source electrode of PMOS transistor MP4, the grid of PMOS transistor MP4 is connected with the output of inverter INV1, the drain electrode of PMOS transistor MP4 is connected with one end of electric capacity C1, the other end ground connection GND of electric capacity C1, resistance R1 is in parallel with electric capacity C1; The input of described Schmidt trigger Smith Trigger is connected with the drain electrode of PMOS transistor MP4, its output and the output of described starting of oscillation testing circuit.
Further, described feedback circuit comprises inverter INV2 and INV3, the input of inverter INV2 is connected as the input of described feedback circuit, its output is connected with the input of described inverter INV3, the output of inverter INV3 is as its first output port of work, connected node between inverter INV2 and INV3 is as its second output port, wherein, first output port and the second output port use as the output of this feedback circuit, first output port is connected with the first enable port START_P, second output port is connected with the second enable port START_N.
Compared with prior art, whether ring oscillator in the utility model determines the starting of oscillation of this ring oscillator by the clock signal detecting the output of its output, if non-starting of oscillation, send starting of oscillation signal to its vibration end, to start this ring oscillator, because it utilizes the feedback mechanism of oscillator inside to start ring oscillator, do not need system to send pulse to start, thus simplify System design.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the utility model embodiment, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the ring oscillator circuit diagram in one embodiment of the self-adapting start in the utility model;
Fig. 2 is the pierce circuit circuit diagram in one embodiment in the utility model;
Fig. 3 is the delay cell circuit diagram in one embodiment in Fig. 2;
Fig. 4 is the starting of oscillation testing circuit circuit diagram in one embodiment in Fig. 1;
Fig. 5 is the sequential chart of the starting of oscillation testing circuit in Fig. 4;
Fig. 6 is the feedback loop circuit diagram in one embodiment in Fig. 1.
[embodiment]
For enabling above-mentioned purpose of the present utility model, feature and advantage become apparent more, are described in further detail the utility model below in conjunction with the drawings and specific embodiments.
Alleged herein " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the utility model.Different local in this manual " in one embodiment " occurred not all refers to same embodiment, neither be independent or optionally mutually exclusive with other embodiments embodiment.Unless stated otherwise, connection herein, be connected, word that the expression that connects is electrically connected all represents and is directly or indirectly electrical connected.Connection in literary composition, connect, the word such as series connection can be understood as indirectly or directly connects and connect, connect.
Please refer to shown in Fig. 1, it is the ring oscillator circuit diagram in one embodiment of the self-adapting start in the utility model.The ring oscillator of this self-adapting start comprises pierce circuit 110, starting of oscillation testing circuit 120 and feedback loop 130.
Described pierce circuit 110 comprises vibration end 1 and output 2, and it is for generation of also passing through its output 2 clock signal.Whether whether described starting of oscillation testing circuit 120 judges the starting of oscillation (or normal oscillation) of described oscillator based on the clock signal that described pierce circuit 110 exports, and export the detection signal representing the starting of oscillation of described pierce circuit 110.Described feedback loop 130 exports corresponding starting of oscillation signal to the vibration end 1 of described pierce circuit 110 based on described detection signal.If described starting of oscillation testing circuit 120 detects the starting of oscillation of described pierce circuit 110, it exports the detection signal representing starting of oscillation, and described feedback loop 130 exports disable starting of oscillation signal based on this, and described pierce circuit 110 normally works; If described starting of oscillation testing circuit 120 detects the non-starting of oscillation of described pierce circuit 110, it exports the detection signal representing non-starting of oscillation, described feedback loop 130 based on the detection signal output enable starting of oscillation signal of the non-starting of oscillation of this expression, until described pierce circuit 110 starting of oscillation.The ring oscillator of the self-adapting start in the utility model utilizes the feedback mechanism of oscillator inside to start ring oscillator, not only solve existing ring oscillator to exist and cannot normally start possible problem, and do not need system transmission pulse to start, simplify System design.
For the ease of understanding the utility model, specifically introduce the ring oscillator of self-adapting start in Fig. 1 by the following examples.
Described pierce circuit 110 is corn module, and it is for being produced by vibration and exported a standard clock signal, and this standard clock signal is for other module of system.In other words, described ring oscillator circuit 110 can provide a clock to use to system.
Please refer to shown in Fig. 2, it is pierce circuit 110 circuit diagram in one embodiment in Fig. 1.In the present embodiment, described pierce circuit comprises the delay cell DelayStage of 4 cascades, each delay cell includes the first delayed branch and the second delayed branch (not shown), wherein, described first delayed branch includes the in-phase input end for receiving differential signal and the in-phase output end for output difference sub-signal, and described second delayed branch includes the inverting input for receiving differential signal and the reversed-phase output for output difference sub-signal.Wherein, the in-phase output end of first order delay cell 210 is connected with inverting input Phase1B with the in-phase input end Phase1 of second level delay cell 220 respectively with reversed-phase output; The in-phase output end of second level delay cell 220 is connected with inverting input Phase2B with the in-phase input end Phase2 of third level delay cell 230 respectively with reversed-phase output; The in-phase output end of third level delay cell 230 is connected with inverting input Phase3B with the in-phase input end Phase3 of fourth stage delay cell 240 respectively with reversed-phase output; The in-phase output end of fourth stage delay cell 240 is connected with inverting input Phase0B with the in-phase input end Phase0 of first order delay cell 210 respectively with reversed-phase output, thus forms the ring oscillator circuit that can produce standard clock signal.
In other embodiments, the number of the delay cell of cascade that pierce circuit 110 comprises can be 2,3,5 ...It should be noted that, if described pierce circuit 110 comprises the delay cell of odd number of cascaded, the in-phase output end of previous stage delay cell is connected with inverting input with the in-phase input end of rear stage delay cell respectively with reversed-phase output; If described pierce circuit 110 comprises even number delay cell, the in-phase output end of previous stage delay cell and reversed-phase output respectively with in-phase input end and the inverting input of rear stage delay cell, the in-phase output end of afterbody delay cell and reversed-phase output respectively with inverting input and the in-phase input end of first order delay cell.
In summary, the pierce circuit 110 in the utility model comprises the delay cell of more than two-stage, and when meeting Barkhausen criterion, it can starting of oscillation.But, because Barkhausen criterion has a precondition, be exactly oscillator when initial foundation (namely during starting of oscillation), need the working point that is stable.For Fig. 2, when supposing initial foundation, the signal of what the in-phase input end Pase1 of second level delay cell 220 and inverting input Pase1B received is phase 180 degree, so its differential signal has set up, and pierce circuit just can normally work.But if when initial foundation, what the in-phase input end Pase1 of second level delay cell 220 and inverting input Pase1B received is identical signal, and Pase1 signal is just locked in initial phase after 4 grades of inverters; In like manner, Pase1B signal also can be locked in initial phase, and so pierce circuit to obtain a stable working point, and pierce circuit cannot vibrate in this case, also just cannot normally work.That is, can by providing a pair differential signal to the normal phase input end of at least one delay cell in pierce circuit and inverting input, to make pierce circuit 110 starting of oscillation, this delay cell can be described as the delay cell with start-up circuit.
Please refer to shown in Fig. 3, it is the delay cell circuit diagram in one embodiment in the utility model with start-up circuit.This delay cell comprises start-up circuit 310 and differential delay circuit.Described differential delay circuit comprises the first delayed branch, the second delayed branch, in-phase input end INP, in-phase output end VON, inverting input INN, reversed-phase output VOP.
The Enable Pin of described start-up circuit 310 is as the vibration end of described pierce circuit, and its first output 3 is connected with the in-phase input end INP of described first delayed branch, and its second output 4 is connected with the inverting input INN of described second delayed branch.Composition graphs 1 and Fig. 3, when described feedback loop 130 output enable starting of oscillation signal, described start-up circuit 310 is worked, first output 3 of described start-up circuit 310 and the second output 4 export a pair differential signal to the in-phase input end INP of this delay cell and inverting input INN, to make pierce circuit 110 starting of oscillation; When described feedback loop 130 exports disable starting of oscillation signal, described start-up circuit is not worked, now, the first output and second output of described start-up circuit 310 do not output signal.
In the embodiment shown in fig. 3, described start-up circuit 310 comprises PMOS transistor MP0A and MP1A, nmos pass transistor MN0A and MN1A, described Enable Pin comprises the first enable port START_P and the second enable port START_N, described PMOS transistor MP1A and nmos pass transistor MN1A is connected between power end V/I_SUPPLY and earth terminal VSS successively, the grid of PMOS transistor MP1A is connected with high level HIGH, the grid of nmos pass transistor MN1A is as the second enable port START_N, connected node between the drain electrode of described PMOS transistor MP1A and the drain electrode of nmos pass transistor MN1A is connected with described in-phase input end phase INP as the first output 3, described PMOS transistor MP0A and nmos pass transistor MN0A is connected between power end V/I_SUPPLY and earth terminal VSS successively, the grid of PMOS transistor MP0A is as the first enable port START_P, the grid of nmos pass transistor MN0A is connected with low level LOW, and the connected node between the drain electrode of described PMOS transistor MP0A and the drain electrode of nmos pass transistor MN0A is connected with described inverting input INN as the second output 4.Wherein, MP1A and MN0A is as dummy argument, itself be used for Differential Output load, MP0A and MN1A has start-up performance, when described feedback loop 130 output enable starting of oscillation signal, first Enable Pin START_P can be dragged down (i.e. the first Enable Pin current potential START_P=0), second Enable Pin START_N is drawn high (i.e. the second Enable Pin current potential START_N=1), the equal conducting of MP0A and MN1A, the signal that start-up circuit 310 exports to in-phase input end INP and inverting input INN is one low/height (differential signal), like this, pierce circuit 110 has just normally worked, represent that the detection signal of starting of oscillation is to feedback loop 130 when the later testing circuit 120 of the normal work of pierce circuit 110 just sends one, feedback loop 130 exports disable starting of oscillation signal, first Enable Pin START_P can be drawn high (i.e. the first Enable Pin current potential START_P=1), second Enable Pin START_N is dragged down (i.e. the second Enable Pin current potential START_N=0), MP0A and MN1A all ends, now, first output and second output of described start-up circuit 310 do not output signal (namely start-up circuit 310 does not work), thus do not affect the normal work of pierce circuit 110.
Continue with reference to shown in figure 3, in this embodiment, described first delayed branch comprises the first inverter 320, described first inverter 320 comprises and is connected to PMOS transistor MP1 between power end V/I_SUPPLY (this power end can be that voltage/current is powered) and earth terminal VSS and nmos pass transistor MN1 successively, the grid of described PMOS transistor MP1 is connected with the in-phase input end INP of the connected node of the grid of nmos pass transistor MN1 with described first delayed branch, connected node between the drain electrode of described PMOS transistor MP1 and the drain electrode of nmos pass transistor MN1 is connected with the in-phase output end VON of described first delayed branch, described second delayed branch comprises the second inverter 330, described second inverter 330 comprises and is connected to PMOS transistor MP0 between power end V/I_SUPPLY and earth terminal VSS and nmos pass transistor MN0 successively, the grid of described PMOS transistor MP0 is connected with the inverting input INN of the connected node of the grid of nmos pass transistor MN0 with described second delayed branch, and the connected node between the drain electrode of described PMOS transistor MP0 and the drain electrode of nmos pass transistor MN0 is connected with the reversed-phase output VOP of described second delayed branch.
In the embodiment shown in fig. 3, the differential delay circuit with the delay cell of start-up circuit also comprises nmos pass transistor MN0B and MN1B, the drain electrode of described nmos pass transistor MN0B is connected with the connected node between described PMOS transistor MP0 and nmos pass transistor MN0, its source electrode is connected with earth terminal VSS, and the connected node between the drain electrode of its grid and PMOS transistor MP1 and the drain electrode of nmos pass transistor MN1 is connected; The drain electrode of described nmos pass transistor MN1B is connected with the connected node between the drain electrode of described PMOS transistor MP1 and the drain electrode of nmos pass transistor MN1, its source electrode is connected with earth terminal VSS, and its grid is connected with the connected node between PMOS transistor MP0 and nmos pass transistor MN0.Nmos pass transistor MN0B and MN1B is, as LATCH (latch), above-mentioned two inverters are pulled into pseudo differential architectures at this.
Have the structure of a delay cell at least as shown in Figure 3 in multiple delay cells in Fig. 2, remaining each delay cell can not arrange start-up circuit 310, and its structure can be such with the differential delay circuit in Fig. 3.
Please refer to shown in Fig. 4, it is starting of oscillation testing circuit 120 circuit diagram in one embodiment in Fig. 1.Whether this starting of oscillation testing circuit is by detecting the frequency of the clock signal C K of described pierce circuit 110 output higher than the threshold value preset, to determine the whether starting of oscillation of described pierce circuit 110, when the frequency of described clock signal C K being detected higher than the threshold value preset, described starting of oscillation testing circuit exports the first logic level (it represents the starting of oscillation of described pierce circuit 110); When the frequency of described clock signal C K being detected lower than the threshold value preset, described starting of oscillation testing circuit exports the second logic level (it represents the non-starting of oscillation of described pierce circuit 110).
In the embodiment shown in fig. 4, described starting of oscillation testing circuit comprises delayer 410, XOR gate 420, inverter INV1, PMOS transistor MP4, current source I1, resistance R1 and electric capacity C1 and Schmidt trigger Smith Trigger.The input of described delayer 410 is connected with the input of described starting of oscillation testing circuit, the output of delayer 410 is connected with the first input end of XOR gate 420, second input of XOR gate 420 is connected with the input of described starting of oscillation testing circuit, and the output of XOR gate 420 is connected with the input of inverter INV1; The positive pole of current source I1 is connected with power end VDD, its negative pole is connected with the source electrode of PMOS transistor MP4, the grid of PMOS transistor MP4 is connected with the output of inverter 430, the drain electrode of PMOS transistor MP4 is connected with one end of electric capacity C1, the other end ground connection GND of electric capacity C1, resistance R1 is in parallel with electric capacity C1; The input of described Schmidt trigger Smith Trigger is connected with the drain electrode of PMOS transistor MP4, and its output is connected with the output START of described starting of oscillation testing circuit.
In Fig. 4, the clock signal C K that pierce circuit exports accesses the input of starting of oscillation testing circuit, signal A is generated through delayer 410, signal A and clock signal C K is by generating signal B after XOR gate 420 XOR, signal B generates signal C after inverter 430, whether signal C, as switching signal, controls PMOS transistor MP4 conducting or cut-off, charges to control current source I1 to node D.If the frequency height of clock signal C K to certain threshold value (such as, can be 1MHz, also can be 10MHz, determine according to demand), so the voltage of D point will be elevated to certain value/low to certain value, thus activate Schmidt trigger Smith Trigger, send detection signal START, export corresponding starting of oscillation signal by feedback loop 130 based on this detection signal START subsequently.Please refer to shown in Fig. 5, it is the timing waveform of each node signal in Fig. 4, if the frequency of clock signal C K is higher, so the time of unit interval PMOS transistor MP4 conducting is longer, current source I1 fills to the charge number of node D also more, and the voltage of respective nodes D is higher, when the voltage of D point is elevated to certain value, Schmidt trigger Smith Trigger exports 1, represents pierce circuit starting of oscillation; Otherwise, if frequency is lower, so the time of unit interval PMOS transistor MP4 conducting is shorter, current source I1 fills to the charge number of node D also fewer, the voltage of respective nodes D is lower, when the voltage of D point is reduced to certain value, Schmidt trigger Smith Trigger exports 0, represents the non-starting of oscillation of pierce circuit.
It should be noted that, except the embodiment shown in Fig. 4, starting of oscillation testing circuit in the utility model also can adopt any one starting of oscillation detection technique of the prior art, as long as whether its clock signal that can export based on described pierce circuit 110 judges the starting of oscillation of described oscillator.
Described feedback loop 130 exports based on described detection signal and represents that the starting of oscillation signal whether starting described pierce circuit 110 is to the vibration end 1 of described pierce circuit 110.Please refer to shown in Fig. 6, it is feedback loop 130 circuit diagram in one embodiment in Fig. 1, in this embodiment, described feedback circuit comprises inverter INV2 and INV3, the input of inverter INV2 is as the input of described feedback circuit, its output is connected with the input of described inverter INV3, the output of inverter INV3 is as its first output port of work, connected node between inverter INV2 and INV3 is as its second output port, wherein, the first output port and the second output port use as the output of this feedback circuit.The input of this feedback circuit is connected with the output START of described starting of oscillation testing circuit 120, its first output and the second output are connected with the second enable port START_N with the first enable port START_P with start-up circuit delay cell as shown in Figure 3 respectively, when described starting of oscillation testing circuit 120 detects described pierce circuit 110 starting of oscillation, PMOS transistor MP0A in described feedback loop 130 control chart 3 in start-up circuit 310 and nmos pass transistor MN1A ends, thus start-up circuit 310 is not worked; When described starting of oscillation testing circuit 120 detects described pierce circuit 110 non-starting of oscillation, in described feedback loop 130 control chart 3, PMOS transistor MP0A and nmos pass transistor MN1A all conductings in start-up circuit 310, exports a pair differential signal to make described start-up circuit 310.
In sum, the utility model provides and has the delay cell of start-up circuit and the ring oscillator of self-adapting start.The ring oscillator of self-adapting start comprises pierce circuit 110, starting of oscillation testing circuit 120 and feedback loop 130, it utilizes the feedback mechanism of oscillator inside to start ring oscillator, not only solve existing ring oscillator to exist and cannot normally start possible problem, and do not need system transmission pulse to start, simplify System design; Pierce circuit comprises the delay cell with start-up circuit, when the non-starting of oscillation of discovery oscillator, drive described start-up circuit, provide a pair differential signal, to make pierce circuit starting of oscillation by described start-up circuit to the normal phase input end of this delay cell and inverting input.
In the utility model in the utility model, " connection ", be connected, word that " companys ", the expression such as " connecing " are electrical connected, if no special instructions, then represent direct or indirect electric connection.
It is pointed out that the scope be familiar with person skilled in art and any change that embodiment of the present utility model is done all do not departed to claims of the present utility model.Correspondingly, the scope of claim of the present utility model is also not limited only to previous embodiment.
Claims (11)
1. a ring oscillator for self-adapting start, is characterized in that, it comprises pierce circuit, starting of oscillation testing circuit and feedback loop,
Described pierce circuit comprises vibration end and output, and it is for generation of also passing through its output clock signal;
Whether whether described starting of oscillation testing circuit judges the starting of oscillation of described pierce circuit based on the clock signal that described pierce circuit exports, and export the detection signal representing the starting of oscillation of described pierce circuit;
Described feedback loop exports corresponding starting of oscillation signal to the vibration end of described pierce circuit based on described detection signal.
2. the ring oscillator of self-adapting start according to claim 1, is characterized in that,
If described starting of oscillation testing circuit detects the starting of oscillation of described pierce circuit, it exports the detection signal representing starting of oscillation, and described feedback loop exports disable starting of oscillation signal based on this, and described pierce circuit normally works; If described starting of oscillation testing circuit detects the non-starting of oscillation of described pierce circuit, it exports and represents the detection signal of non-starting of oscillation, described feedback loop based on the detection signal output enable starting of oscillation signal of the non-starting of oscillation of this expression, to make described pierce circuit starting of oscillation.
3. the ring oscillator of self-adapting start according to claim 2, is characterized in that,
Described pierce circuit comprises the delay cell of at least two cascades, and wherein, at least one delay cell is the delay cell with start-up circuit,
The described delay cell with start-up circuit comprises differential delay circuit and start-up circuit,
Described differential delay circuit comprises the first delayed branch and the second delayed branch,
Described first delayed branch comprises the in-phase input end for receiving differential signal and the in-phase output end for output difference sub-signal;
Second delayed branch comprises the inverting input for receiving differential signal and the reversed-phase output for output difference sub-signal;
The second output that described start-up circuit comprises Enable Pin, the first output be connected with in-phase input end and is connected with inverting input, when described Enable Pin receives enable starting of oscillation signal, described start-up circuit exports a pair differential signal by its first output and the second output, when described Enable Pin receives disable starting of oscillation signal, described start-up circuit does not work
The described vibration end of Enable Pin as described ring oscillator with the delay cell of start-up circuit.
4. the ring oscillator of self-adapting start according to claim 3, is characterized in that,
In described pierce circuit, except the delay cell with start-up circuit, the structure of remaining each delay unit is identical with the structure of the described differential delay circuit had in the delay cell of start-up circuit.
5. the ring oscillator of self-adapting start according to claim 3, is characterized in that,
Described start-up circuit comprises PMOS transistor MP0A and MP1A, nmos pass transistor MN0A and MN1A, and described Enable Pin comprises the first enable port START_P and the second enable port START_N,
Described PMOS transistor MP1A and nmos pass transistor MN1A is connected between power end V/I_SUPPLY and earth terminal VSS successively, the grid of PMOS transistor MP1A is connected with high level HIGH, the grid of nmos pass transistor MN1A is as the second enable port START_N, and the connected node between described PMOS transistor MP1A and nmos pass transistor MN1A is as described first output; Described PMOS transistor MP0A and nmos pass transistor MN0A is connected between power end V/I_SUPPLY and earth terminal VSS successively, the grid of PMOS transistor MP0A is as the first enable port START_P, the grid of nmos pass transistor MN0A is connected with low level LOW, and the connected node between described PMOS transistor MP0A and nmos pass transistor MN0A is as the second output.
6. the ring oscillator of the self-adapting start according to claim 3,4 or 5, is characterized in that,
Described first delayed branch comprises the first inverter, described first inverter comprises and is connected to PMOS transistor MP1 between power end V/I_SUPPLY and earth terminal VSS and nmos pass transistor MN1 successively, the grid of described PMOS transistor MP1 is connected with the in-phase input end INP of the connected node of the grid of nmos pass transistor MN1 with described first delayed branch, and the connected node between the drain electrode of described PMOS transistor MP1 and the drain electrode of nmos pass transistor MN1 is connected with the in-phase output end VON of described first delayed branch;
Described second delayed branch comprises the second inverter, described second inverter comprises and is connected to PMOS transistor MP0 between power end V/I_SUPPLY and earth terminal VSS and nmos pass transistor MN0 successively, the grid of described PMOS transistor MP0 is connected with the inverting input INN of the connected node of the grid of nmos pass transistor MN0 with described second delayed branch, and the connected node between the drain electrode of described PMOS transistor MP0 and the drain electrode of nmos pass transistor MN0 is connected with the reversed-phase output VOP of described second delayed branch.
7. the ring oscillator of self-adapting start according to claim 6, it is characterized in that, described differential delay circuit also comprises nmos pass transistor MN0B and MN1B, the drain electrode of described nmos pass transistor MN0B is connected with the connected node between the drain electrode of described PMOS transistor MP0 and the drain electrode of nmos pass transistor MN0, its source electrode is connected with earth terminal VSS, and the connected node between the drain electrode of its grid and PMOS transistor MP1 and the drain electrode of nmos pass transistor MN1 is connected; The drain electrode of described nmos pass transistor MN1B is connected with the connected node between the drain electrode of described PMOS transistor MP1 and the drain electrode of nmos pass transistor MN1, its source electrode is connected with earth terminal VSS, and the connected node between the drain electrode of its grid and PMOS transistor MP0 and the drain electrode of nmos pass transistor MN0 is connected.
8. the ring oscillator of self-adapting start according to claim 3, is characterized in that,
Described pierce circuit comprises the delay cell of even number cascade, the in-phase output end of previous stage delay cell and reversed-phase output connect in-phase input end and the inverting input of rear stage delay cell, and the in-phase output end of afterbody delay cell and reversed-phase output connect inverting input and the in-phase input end of first order delay cell respectively.
9. the ring oscillator of self-adapting start according to claim 3, is characterized in that,
Whether described starting of oscillation testing circuit is by detecting the frequency of the clock signal of described pierce circuit output higher than the threshold value preset, to determine the whether starting of oscillation of described pierce circuit, when the frequency of described clock signal being detected higher than the threshold value preset, described starting of oscillation testing circuit exports the first logic level; When the frequency of described clock signal being detected lower than the threshold value preset, described starting of oscillation testing circuit exports the second logic level.
10. the ring oscillator of self-adapting start according to claim 9, it is characterized in that, described starting of oscillation testing circuit comprises delayer, XOR gate, inverter INV1, PMOS transistor MP4, current source I1, resistance R1 and electric capacity C1 and Schmidt trigger Smith Trigger
The input of described delayer is connected with the input of described starting of oscillation testing circuit, the output of delayer is connected with the first input end of XOR gate, second input of XOR gate is connected with the input of described starting of oscillation testing circuit, and the output of XOR gate is connected with the input of inverter INV1; The positive pole of current source I1 is connected with power end VDD, its negative pole is connected with the source electrode of PMOS transistor MP4, the grid of PMOS transistor MP4 is connected with the output of inverter INV1, the drain electrode of PMOS transistor MP4 is connected with one end of electric capacity C1, the other end ground connection GND of electric capacity C1, resistance R1 is in parallel with electric capacity C1;
The input of described Schmidt trigger Smith Trigger is connected with the drain electrode of PMOS transistor MP4, its output and the output of described starting of oscillation testing circuit.
The ring oscillator of 11. self-adapting starts according to claim 3, is characterized in that,
Described feedback loop comprises inverter INV2 and INV3, the input of inverter INV2 is connected as the input of described feedback circuit, its output is connected with the input of described inverter INV3, the output of inverter INV3 is as its first output port of work, connected node between inverter INV2 and INV3 is as its second output port, wherein, the first output port and the second output port use as the output of this feedback circuit
First output port is connected with the first enable port START_P,
Second output port is connected with the second enable port START_N.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734699A (en) * | 2015-03-27 | 2015-06-24 | 灿芯半导体(上海)有限公司 | Delay unit with starting circuit and self-adaptive starting type ring oscillator |
| CN106685417A (en) * | 2016-11-17 | 2017-05-17 | 四川和芯微电子股份有限公司 | Flow control ring oscillator |
-
2015
- 2015-03-27 CN CN201520181975.9U patent/CN204633750U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104734699A (en) * | 2015-03-27 | 2015-06-24 | 灿芯半导体(上海)有限公司 | Delay unit with starting circuit and self-adaptive starting type ring oscillator |
| CN106685417A (en) * | 2016-11-17 | 2017-05-17 | 四川和芯微电子股份有限公司 | Flow control ring oscillator |
| CN106685417B (en) * | 2016-11-17 | 2020-03-24 | 四川和芯微电子股份有限公司 | Fluidic ring oscillator |
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