CN107733402B

CN107733402B - Time sequence monitoring unit and monitoring system for near-threshold low voltage

Info

Publication number: CN107733402B
Application number: CN201710972595.0A
Authority: CN
Inventors: 单伟伟; 毕润东; 肖如吉; 邵帅
Original assignee: Southeast University Wuxi Institute Of Integrated Circuit Technology; Southeast University
Current assignee: Southeast University Wuxi Institute Of Integrated Circuit Technology; Southeast University
Priority date: 2017-10-18
Filing date: 2017-10-18
Publication date: 2020-10-30
Anticipated expiration: 2037-10-18
Also published as: CN107733402A

Abstract

The invention discloses a time sequence monitoring unit and a time sequence monitoring system facing to a near-threshold low voltage, relates to an adaptive frequency adjustment technology based on-chip time sequence detection, and belongs to the technical field of low-power-consumption design of integrated circuits. The monitoring unit provided by the invention realizes the time-lapse monitoring facing to the near-threshold voltage with lower circuit cost, realizes the self-adaptive adjustment of the system frequency by building a monitoring system comprising a frequency control state machine, a phase-locked loop and a rapid clock adjusting module, and solves the technical problems that a time sequence monitoring circuit facing to the conventional voltage design is difficult to work in a near-threshold region correctly, and few time sequence monitoring units capable of working facing to the near-threshold voltage region have large area and high cost.

Description

Time sequence monitoring unit and monitoring system for near-threshold low voltage

Technical Field

The invention discloses a time sequence monitoring unit and a time sequence monitoring system facing to a near-threshold low voltage, relates to an adaptive frequency adjustment technology based on-chip time sequence detection, and belongs to the technical field of low-power-consumption design of integrated circuits.

Background

As Integrated Circuit (IC) Process sizes shrink, Process-Voltage-Temperature (PVT) variations have an increasing effect on the circuits. IC designers typically reserve timing margins to ensure that the chip will operate properly in the worst-case PVT environment. "worst case" refers to the situation where various adverse factors that adversely affect the timing of the circuit occur at the same time, but in the actual operation of the chip, the worst case occurs rarely or not, which results in over-conservative design and waste of chip performance and power consumption.

The on-chip time sequence monitoring technology monitors the influence of PVT deviation on the time sequence of a critical path by adding a time sequence monitoring unit in a circuit, adaptively adjusts the working frequency according to monitored information, effectively releases reserved time sequence allowance so as to improve the performance, and inhibits the influence of the PVT deviation on the circuit. On-chip timing monitoring techniques can be mainly classified into error correction and timing prediction. The timing prediction type monitoring unit needs to reserve a small segment of timing margin before the rising edge of a clock, the reserved small segment of timing margin is called a monitoring window, and if data jumping occurs in the monitoring window, the timing of a key path is already tense, and frequency reduction processing is needed. The timing prediction type monitoring unit is advantageous in that it does not require an additional system level recovery mechanism. The traditional time sequence prediction type monitoring unit generates a monitoring window by artificially building a delay chain on a key data path, but the delay chain brings overlarge area and power consumption cost; meanwhile, in a near-threshold region, the reduction of the power supply voltage causes a larger influence of the PVT deviation on the circuit delay, and even the circuit delay deviation is increased by several times, so that it is more necessary to perform online timing monitoring to reduce the influence of the PVT deviation under a near-threshold low voltage. However, the reduction of the operating voltage causes the delay performance of the circuit to be greatly reduced, which greatly affects the function and stability of the timing monitoring circuit. At present, most timing sequence monitoring circuits are designed for a conventional voltage region and are difficult to work in a near-threshold region correctly; the very few timing monitoring units capable of operating towards the near threshold region suffer from a too large number of transistors, which makes the area cost too high.

Disclosure of Invention

The invention aims to provide a time sequence monitoring unit and a monitoring system facing to a near-threshold low voltage aiming at the defects of the background technology, realize the time monitoring facing to the near-threshold voltage with lower circuit cost, realize the self-adaptive adjustment of the system frequency by building the monitoring system comprising a frequency control state machine, a phase-locked loop and a rapid clock adjusting module, and solve the technical problems that a time sequence monitoring circuit designed facing to the conventional voltage is difficult to work in a near-threshold area correctly and few time sequence monitoring units capable of working in a near-threshold voltage area have large area and high cost.

The invention adopts the following technical scheme for realizing the aim of the invention:

the timing sequence monitoring unit facing the near-threshold low voltage comprises: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, an inverter, and an NAND gate,

the source end of the first PMOS tube is connected with a power supply, the gate end of the first PMOS tube is connected with the gate end of the first NMOS tube in parallel and then connected with the tail end of the critical path, the source end of the first NMOS tube is grounded, the drain end of the first PMOS tube, the drain end of the second NMOS tube and the source end of the second PMOS tube are connected together in parallel, the source end of the second NMOS tube, the drain end of the second PMOS tube and the drain end of the first NMOS tube are connected together in parallel, the gate end of the second NMOS tube is connected with a clock signal, the gate end of the second PMOS tube is connected with a signal which is not in phase with the clock signal, the input end of the phase inverter is connected with the drain end of the first PMOS tube, one input end of the NAND gate is connected with the output end of the phase inverter, the other input end of the NAND gate is connected with the drain end of the first NMOS tube, and the NAND gate monitors the time sequence of.

A near-threshold low-voltage oriented monitoring system comprising:

the time sequence monitoring unit group comprises at least one time sequence monitoring unit, the input end of each time sequence monitoring unit is respectively connected with the tail end of a key path, each time sequence monitoring unit monitors the time sequence of the key path connected with the time sequence monitoring unit when the clock signal is in a low phase and outputs an early warning signal when the time sequence of the key path is tense,

the input end of the dynamic OR gate tree is connected with the output end of the time sequence monitoring unit group, the dynamic OR gate tree enters a working state after receiving a reset signal, a total early warning signal representing on-chip time sequence tension is output when at least one time sequence monitoring unit outputs an early warning signal,

the input end of the frequency control state machine is connected with the output end of the dynamic OR gate tree, the frequency control state machine outputs a frequency reduction signal when receiving the total early warning signal, outputs a configuration signal when not receiving the total early warning signal in a limited number of clock cycles, outputs a reset signal to the control end of the dynamic OR gate tree,

a phase-locked loop, the input end of which is connected with the output end of the frequency control state machine and outputs a high-frequency pulling signal when receiving the configuration signal,

a fast clock adjusting module, the input end of which is connected with the output end of the frequency control state machine and the output end of the phase-locked loop, and the fast clock adjusting module, after receiving the frequency-down signal, performs frequency stretching to the clock signal and outputs the frequency-down processed clock signal to the on-chip main circuit and the time-sequence monitoring unit group according to the monitoring window duty ratio output by the monitoring window configuration module, and when receiving the frequency-up signal, performs frequency compression to the clock signal and outputs the frequency-up processed clock signal to the on-chip main circuit and the time-sequence monitoring unit group according to the monitoring window duty ratio output by the monitoring window configuration module,

and the output end of the monitoring window configuration module is connected with the control end of the rapid clock regulation module and outputs a duty ratio signal of the monitoring window to the rapid clock regulation module.

As a further optimization scheme of the monitoring system facing the near-threshold low voltage, the frequency control state machine outputs a reset signal to a control end of the dynamic OR gate tree at an initial moment and after receiving the total early warning signal.

As a further optimization scheme of the monitoring system facing the near-threshold low voltage, the timing sequence monitoring unit comprises: a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, an inverter, and an NAND gate,

As a further optimization scheme of the monitoring system facing the near-threshold low voltage, the dynamic or gate tree includes:

a charging PMOS tube with its source terminal connected to the power supply and its gate terminal connected to the reset signal,

the grid end is connected with an NMOS tube of the output end of the time sequence monitoring unit, the drain end of each NMOS tube is connected with the drain end of the charging PMOS tube in parallel,

the drain terminal of the discharge NMOS tube is connected with the source terminal of each NMOS tube in parallel, the gate terminal of the discharge NMOS tube is connected with a reset signal, the source terminal of the discharge NMOS tube is grounded,

the drain terminal of the NMOS transistor is kept connected to the drain terminal of the PMOS transistor, the source terminal is grounded, and,

and the input end of the phase inverter is connected with the drain end of the holding NMOS tube, and the output end of the phase inverter is connected with the gate end of the holding NMOS tube in parallel and then serves as the output end of the dynamic OR gate tree.

By adopting the technical scheme, the invention has the following beneficial effects:

(1) the on-chip time sequence monitoring unit can complete the time sequence monitoring function by only using 10 transistors, has the advantages of very simple structure and small area, can effectively reduce the area cost of the whole self-adaptive system, and can work at low to near threshold voltage, thereby being applied to a circuit facing the near threshold application.

(2) The influence of PVT deviation on the time sequence is monitored in real time in a chip, so that the working frequency of the circuit is adjusted, the frequency can be improved when the time sequence is loose, and the clock period is stretched to avoid the error of the time sequence when the time sequence is tense, so that the reserved time sequence allowance in the traditional integrated circuit design can be effectively reduced, and the circuit performance is improved.

Drawings

Fig. 1 is a schematic diagram of a monitoring system.

Fig. 2 is a circuit diagram of a timing monitoring unit.

FIG. 3 is a functional timing diagram of the timing monitor unit.

FIG. 4 is a circuit diagram of a dynamic OR gate tree.

FIG. 5 is a functional timing diagram of a dynamic OR gate tree.

Fig. 6 is a schematic diagram of the whole process of adaptive frequency adjustment at low voltage.

Fig. 7 is a system configuration diagram of the entire monitoring system.

The reference numbers in the figures illustrate: 1 is a time sequence monitoring unit group, 2 is a dynamic OR gate tree, 3 is a frequency control state machine, 4 is a phase-locked loop, 5 is a fast clock adjusting module, 6 is a monitoring window configuration module, M1 is a first PMOS tube, M4 is a second PMOS tube, M2 is a first NMOS tube, M3 is a second NMOS tube, INV1 is an inverter, NAND2 is a NAND gate, MOP1 is a charging PMOS tube, MON1 is a discharging NMOS tube, MON2 is a holding NMOS tube, and MO1 to MON are NMOS tubes with gate terminals connected with the output end of the time sequence monitoring unit.

Detailed Description

The technical scheme of the invention is explained in detail in the following with reference to the attached drawings.

Fig. 1 and 7 show a time sequence monitoring system for a near-threshold low voltage, which includes a time sequence monitoring group unit 1, a Dynamic Or-gate tree (Dynamic Or-tree)2, a frequency control state machine 3, a phase-locked loop 4, a fast clock adjusting module 5, and a monitoring window configuration module 6.

The method comprises the steps of respectively inserting N time sequence monitoring units in a time sequence monitoring unit group 1 into the tail ends of N key paths, connecting the input ends of the time sequence monitoring units with input data (namely key path output data) and monitoring whether the time sequence of the key paths connected with the time sequence monitoring units is tense or not when a clock is in a low phase, if the time sequence is tense, immediately generating an early warning signal Pre _ error in a monitoring window, and correspondingly, generating a group of early warning signals Pre _ error [ N:1] by a group of time sequence monitoring units, wherein N is an integer larger than or equal to 1.

The input end of the dynamic or gate tree 2 receives the early warning signals generated by all the time sequence monitoring units, when at least one time sequence monitoring unit outputs the early warning signals, the early warning signals generated by all the monitoring units distributed in the SoC chip are converged into a total early warning signal Pre _ error _ all representing the on-chip time sequence tension, and the total early warning signal is transmitted to the frequency control state machine 3.

The frequency control state machine 3 changes the working state according to the current system frequency and the total early warning signal Pre _ error _ all, generates a frequency reduction signal Slow and transmits the frequency reduction signal Slow to the fast clock adjusting module 5 when the total early warning signal is at a high level, and if the early warning signal is not detected in continuous K periods (K is an integer larger than 10), which indicates that the timing sequence margin of the circuit is more, the phase-locked loop 4 is configured to improve the working frequency.

The phase locked loop 4 is used to provide an initial clock frequency and to increase the operating speed of the circuit under the control of the frequency control state machine.

And the fast clock adjusting module 5 completes frequency reduction in one period after receiving the frequency reduction signal Slow, modulates the frequency-reduced system clock Clk according to the duty ratio of the monitoring window and then sends the modulated frequency-reduced system clock Clk into the main circuit and the time sequence monitoring unit group, and modulates the frequency-increased system clock Clk according to the duty ratio of the monitoring window and then sends the modulated frequency-increased system clock Clk into the main circuit and the time sequence monitoring unit group after receiving the configuration signal for increasing the working frequency of the phase-locked loop.

And the monitoring window configuration module 6 modulates the duty ratio of the monitoring window according to the PVT environment and outputs the modulated duty ratio of the monitoring window to the rapid clock regulation module 5.

As shown in fig. 2, the timing monitoring unit includes a first PMOS transistor M1, a second PMOS transistor M4, a first NMOS transistor M2, a second NMOS transistor M3, an inverter INV1, and a NAND gate NAND 2. An inverter is formed by the first PMOS transistor M1 and the first NMOS transistor M2, a transmission gate formed by the second NMOS transistor M3 and the second PMOS transistor M4 is connected between the drain terminal a node of the first PMOS transistor M1 and the drain terminal B node of the first NMOS transistor M2, an input signal of the timing monitoring unit is connected to the gate terminals of the first PMOS transistor M1 and the first NMOS transistor M2, the clock signal Clk is connected to the gate terminal of the second NMOS transistor M3, a non-signal of the clock signal Clk is connected to the gate terminal of the second PMOS transistor M4, the drain terminal a node of the first PMOS transistor M1 is connected to the input terminal of the inverter INV1, the output terminal of the inverter INV1 is connected to the first input terminal of the NAND gate 2, the drain terminal B node of the first NMOS transistor M2 is connected to the second input terminal of the NAND gate 2, and an early warning signal output by the NAND gate 2 is the early warning signal of the timing monitoring unit. The timing sequence monitoring unit uses a clock low level as a monitoring window, and during the clock low level, if data Din jumps, Pre _ error is pulled high to be a high level; when the clock signal jumps to the high level, Pre _ error is reset to 0.

The functional timing diagram of the timing monitoring unit is shown in fig. 3: during the high level of the clock, the transmission gates (M3, M4) between the node A and the node B are in a conducting state, and the voltage between the node A and the node B has no threshold loss, namely, the voltage values of the node A and the node B are the same, so that the output early warning signal Pre _ error is always in a low level state; when the clock jumps to low level, the transmission gates (M3, M4) are turned off, and in the 1 st period, the input data does not jump during the low level of the clock, so the charges of the node A and the node B are kept unchanged, and therefore, the early warning signal Pre _ error output after passing through the inverter and the NAND gate still keeps low level.

In the 2 nd cycle, also, during the clock high level period, the transmission gate (M3, M4) between the node a and the node B is in the conducting state, the output Pre _ error signal is at the low level, during the clock low level period, the input data Din has a transition from high to low, at this time, the first PMOS transistor M1 is conducting, the a node is charged to high level by the power supply through the first PMOS transistor M1, and becomes different from the level value of B, and therefore, after passing through the inverter and the nand gate, a high level pulse Pre _ error signal is generated.

In the 3 rd period, also during the high level period of the clock, the voltages of the node a and the node B are the same, so that the output Pre-alarm signal Pre _ error is at the low level, in the low level region of the clock, the data Din has a transition from the low level to the high level, at this time, the charge of the node B is discharged to the ground through the first NMOS transistor M2, so that the values of a and B are different, therefore, after passing through the inverter and the nand gate, a high level pulse Pre-alarm signal is generated, and after Clk reenters the high level region of the clock, the Pre-alarm signal is pulled back to the low level.

The dynamic OR gate tree structure is shown in FIG. 4, where signals Pre _ error [1] to Pre _ error [ N ] are early warning signals generated by timing monitoring unit groups dispersed in a chip, i _ RESET is a RESET signal of the dynamic OR gate, the RESET signal is from a frequency control state machine and is used to RESET the dynamic OR gate to restart its operation after the initial time and the generation of the total early warning signal Pre _ error _ al, and when Pre _ error _ all is high level, the fast clock adjusting circuit 5 should be started to immediately reduce the frequency, thereby avoiding the generation of real timing errors.

When i _ RESET is 0, the dynamic OR gate tree structure does not collect the Pre-warning signal Pre _ error generated by each time sequence monitoring unit, and the total Pre-warning signal Pre _ error _ all is RESET to low level; when i _ RESET is 1, starting an OR gate function, collecting early warning signals Pre _ error generated by each time sequence monitoring unit, if at least one Pre _ error is high level, enabling a total early warning signal Pre _ error _ all to be high level, and adjusting frequency through a rapid clock adjusting circuit; if the Pre-warning signal Pre _ error generated by each timing monitoring unit is at a low level, the total Pre-warning signal is at a low level Pre _ error _ all, and the clock frequency does not need to be adjusted.

The timing diagram of the dynamic OR-tree function is shown in FIG. 5 and includes: the charge PMOS tube MOP1, NMOS tubes MO 1-MON (N is the number of the time sequence monitoring units) with the grid ends connected with the output end of the time sequence monitoring unit, a discharge NMOS tube MON1 and a holding NMOS tube MON 2. The source end of the charging PMOS pipe MOP1 is connected with a power supply, the gate end of the charging PMOS pipe MOP1 is connected with a reset signal, the drain ends of the NMOS pipes MO 1-MON are connected with the drain end of the charging PMOS pipe MOP1 in parallel, the drain end of the discharging NMOS pipe MON1 is connected with the source ends of the NMOS pipes MO 1-MON in parallel, the gate end of the discharging NMOS pipe MON1 is connected with the reset signal, the source end of the discharging NMOS pipe MON1 is grounded, the drain end of the NMOS pipe MON2 is connected with the drain end of the charging PMOS pipe MOP1, the source end of the NMOS pipe MON2 is grounded, the input end of the phase inverter is connected with the drain end of the NMOS pipe MON2, and the output end of the phase inverter is connected with the gate end of the NMOS pipe MON2 in parallel and then serves as the output.

In cycle 1, i _ RESET is lowered, resetting the dynamic OR gate. In the subsequent 2 nd clock cycle, as long as one or more signals from Pre _ error [1] to Pre _ error [ N ] are high level, the PMOS transistor (PMOS transistor MO1, PMOS transistors MO2, …, PMOS transistor MON) controlled by the Pre _ error [ N ] is conducted, so that the middle dynamic node is discharged to low level to ground, and a high level total early warning signal Pre _ error _ all representing the total timing error is generated after passing through the inverter.

In cycle 3, i _ RESET is pulled low, and a RESET operation is performed. At this time, i _ RESET signal is pulled low, and the total Pre-alarm signal Pre _ error _ all is RESET to low level, and the dynamic or gate can accept new data again.

The working flow of the self-adaptive frequency adjusting system is as follows:

and starting the system, adjusting the duty ratio of the clock through the monitoring window configuration module 6 according to the PVT environment to configure the monitoring window, and finishing the initialization of the system.

The system enters a normal operation state, and the working frequency is the current output frequency of the phase-locked loop 4. If the time sequence is tense, the total early warning signal Pre _ error _ all is pulled high, the stretching frequency of the rapid clock adjusting module 5 is started, and the time sequence error caused by sampling of wrong data by the trigger at the tail end of the critical path is prevented. If the time sequence is not tense, the total early warning signal Pre _ error _ all is low, the No _ error _ count signal is used for recording the period of the non-occurrence of the early warning signal, if the early warning signal is not detected in continuous K periods (K is an integer larger than 10), the time sequence allowance of the circuit is large, the phase-locked loop 4 is configured to improve the working frequency, and the time sequence allowance is reduced.

The detailed adaptive Frequency adjustment process can be divided into five states, namely Initial (000), Normal (001), Frequency _ up (010), Frequency _ down (011) and Clk _ stretch (100).

Initial (000) state: and starting the system, adjusting the duty ratio of the clock through the monitoring window configuration module 6 according to the PVT environment, configuring the monitoring window, and finishing the initialization of the system.

Normal (001) state: after the system is initialized, the system enters a normal operation state, the working frequency of the system is the output frequency of the current phase-locked loop, if the time sequence is tense, the total early warning signal Pre _ error _ all is pulled high, the frequency control state machine is switched to a Clk _ stretch state, the stretching frequency of the rapid clock adjusting module is started, and the condition that the trigger at the tail end of the key path samples wrong data to generate time sequence errors is prevented; if the time sequence is loose, and the total early warning signal Pre _ error _ all is low, the No _ error _ count signal is used for recording the period without early warning, if the early warning signal is not detected in continuous K periods at the moment, the time sequence margin of the circuit is large, the circuit enters a Frequency _ up state, the circuit Frequency is increased, and the time sequence margin is reduced.

Frequency _ up (010) state: the system has no time sequence early warning signal for continuous K periods, which shows that the time sequence is very loose, a phase-locked loop can be configured to improve the working Frequency and reduce the time sequence margin, the phase-locked loop outputs a PLL _ lock signal, if the PLL _ lock is low, the phase-locked loop is still stable, the state machine is kept in a Frequency _ up state, if the PLL _ lock is pulled high, the phase-locked loop is configured to be finished, the stable Frequency is output, the state machine is switched back to a Normal state, and the Frequency modulation is finished.

Frequency _ down (011) state: when the phase-locked loop is in a frequency reduction configuration stage, the timing sequence early warning signal is still high at the moment, which indicates that the rapid clock adjusting module adopts frequency stretching with a larger amplitude, the early warning signal still cannot disappear, and indicates that the PVT environment has a larger change at the moment, and the frequency reduction processing of the phase-locked loop is required.

Clk _ stretch (100) state: after the system samples the early warning signal, the Frequency needs to be adjusted quickly, if the early warning signal still exists at the moment, the early warning signal still cannot be eliminated even if the system adopts a larger stretching amplitude, and then the system enters a Frequency _ down state to reduce the Frequency of the phase-locked loop; if no time sequence early warning signal is detected at the moment, the system eliminates the rapid deviation through frequency stretching, if no early warning signal exists all the time, the stretching amplitude Step can be gradually reduced, and when the Step is reduced to 1, no early warning signal still exists, the state machine is switched back to the Normal state; if a timing advance occurs during the Clk _ stretch state again, the stretch magnitude needs to be increased.

In a specific implementation case of the online time sequence monitoring unit and the online time sequence monitoring system for the near-threshold low voltage, the system is applied to an SHA256 encryption chip, and the chip is designed by adopting an SMIC 40nm process and works at the near-threshold voltage of 0.6V.

FIG. 6 shows the whole process of the on-line monitoring and adaptive frequency adjusting system under TT process angle of 0.6V and-25 ℃. Clk is a system clock, and the clock frequency is higher, so that the frequency is not beneficial to observing the frequency rise and fall, so that the frequency change is observed by using a Freq _ show _ id signal, the voltage value of Freq _ show _ id on a waveform diagram is the output frequency of the phase-locked loop, and the initial frequency of the output frequency of Clk is 100 Mhz. Firstly, the adaptive frequency adjusting part in the monitoring system spends K clock cycles to configure the monitoring window, and after the pulse is generated by the Config signal, the configuration of the monitoring window is finished. State machine signals State [2:0] are also switched from the Initial (000) State to the Normal (001) State. And then the system starts to detect the time sequence early warning signal, and the time sequence margin can not be detected by the system because the initial time sequence margin is loose, so that the time sequence margin can be compressed by continuously increasing the frequency. The Freq _ up _ id signal is pulled up once every K clock cycles, the system frequency is gradually increased, and as the time sequence margin is continuously reduced and the clock frequency is 122MHz, the time sequence early warning is started to be generated, the system frequency is not increased any more, and finally the system frequency tends to a stable state. The PLL _ lock _ id is a locking signal of the phase-locked loop, and when the PLL _ lock _ id signal is pulled high, it indicates that the output frequency of the phase-locked loop is locked, and the frequency adjustment system will continue to operate. Pre _ error _ all is the total early warning signal, State [2:0] is the State machine of the adaptive frequency regulation system. In summary, whether the timing of the circuit is short is monitored in real time by the timing monitoring unit, the frequency of the whole adaptive frequency regulation system can be gradually increased according to an expected design until the timing early warning signal appears, and after the timing early warning appears, the AFS system processes the timing early warning signal through the rapid clock regulation circuit to prevent the system from making mistakes, so that the chip can work at the highest possible frequency, and the waste of timing allowance caused by PVT deviation is effectively reduced.

Claims

1. The timing sequence monitoring unit facing the low voltage close to the threshold value is characterized by comprising: a first PMOS tube (M1), a second PMOS tube (M4), a first NMOS tube (M2), a second NMOS tube (M3), an inverter (INV1) and an NAND gate (NAND2),

the source end of the first PMOS tube (M1) is connected with a power supply, the gate end of the first PMOS tube (M1) is connected with the gate end of the first NMOS tube (M2) in parallel and then connected with the tail end of a critical path, the source end of the first NMOS tube (M2) is grounded, the drain end of the first PMOS tube (M1), the drain end of the second NMOS tube (M3) and the source end of the second PMOS tube (M4) are connected together in parallel, the source end of the second NMOS tube (M3), the drain end of the second PMOS tube (M4) and the drain end of the first NMOS tube (M2) are connected together in parallel, the gate end of the second NMOS tube (M3) is connected with a clock signal, the gate end of the second PMOS tube (M4) is connected with a signal which is not in phase with the clock signal, the input end of the inverter (58INV 26) is connected with the drain end of the first PMOS tube (M1), one input end of the inverter (1) of the NAND gate (NAND gate) is connected with a clock signal, the other input end of the Inverter (INV) is connected with the drain end of the NAND gate 638) of the critical path, and the other input end of the NAND gate signal of the NAND gate terminal of the critical path of the .

2. A near-threshold low-voltage oriented monitoring system, comprising:

a time sequence monitoring unit group (1) comprising at least one time sequence monitoring unit, wherein the input end of each time sequence monitoring unit is respectively connected with the tail end of a key path, each time sequence monitoring unit monitors the time sequence of the key path connected with the time sequence monitoring unit when a clock signal is in a low phase and outputs an early warning signal when the time sequence of the key path is tense,

the input end of the dynamic OR gate tree (2) is connected with the output end of the time sequence monitoring unit group (1), the dynamic OR gate tree enters a working state after receiving a reset signal, a total early warning signal representing on-chip time sequence tension is output when at least one time sequence monitoring unit outputs an early warning signal,

a frequency control state machine (3), the input end of which is connected with the output end of the dynamic OR gate tree (2), outputs a frequency reduction signal when receiving the total early warning signal, outputs a configuration signal when not receiving the total early warning signal in a limited number of clock cycles, outputs a reset signal to the control end of the dynamic OR gate tree (2),

a phase-locked loop (4) with an input end connected with an output end of the frequency control state machine (3) and outputting a high-frequency pulling signal when receiving a configuration signal,

a fast clock adjusting module (5), the input end of which is connected with the output end of the frequency control state machine (3) and the output end of the phase-locked loop (4), after receiving the frequency-down signal, performing frequency stretching on the clock signal and outputting the frequency-down processed clock signal to the on-chip main circuit and the time sequence monitoring unit set (1) according to the duty ratio of the monitoring window output by the monitoring window configuration module (6), when receiving the frequency-up signal, performing frequency compression on the clock signal and outputting the frequency-up processed clock signal to the on-chip main circuit and the time sequence monitoring unit set (1) according to the duty ratio of the monitoring window output by the monitoring window configuration module (6), and,

and the output end of the monitoring window configuration module (6) is connected with the control end of the rapid clock regulation module and outputs a duty ratio signal of the monitoring window to the rapid clock regulation module.

3. The near-threshold low-voltage-oriented monitoring system according to claim 2, wherein the frequency control state machine (3) outputs a reset signal to the control end of the dynamic OR-gate tree (2) at an initial time and after receiving the total early warning signal.

4. The near-threshold low-voltage-oriented monitoring system according to claim 2 or 3, wherein the timing monitoring unit comprises: a first PMOS tube (M1), a second PMOS tube (M4), a first NMOS tube (M2), a second NMOS tube (M3), an inverter (INV1) and an NAND gate (NAND2),

5. The near-threshold low-voltage oriented monitoring system according to claim 2 or 3, wherein the dynamic OR-gate tree comprises:

a charging PMOS tube (MOP1), the source terminal of which is connected with the power supply, the gate terminal of which is connected with the reset signal,

the grid ends are connected with NMOS tubes (MO 1-MON) of the output end of a time sequence monitoring unit, the drain ends of the NMOS tubes (MO 1-MON) are connected with the drain end of a charging PMOS tube (MOP1) in parallel, N is the number of the time sequence monitoring units,

a discharge NMOS (MON1), the drain terminal of which is connected with the source terminal of each NMOS (MO 1-MON) in parallel, the gate terminal of which is connected with the reset signal, the source terminal of which is grounded,

a holding NMOS transistor (MON2), whose drain terminal is connected to the drain terminal of the charging PMOS transistor (MOP1), whose source terminal is grounded, and,

and the input end of the inverter is connected with the drain end of the holding NMOS tube (MON2), and the output end of the inverter is connected with the gate end of the holding NMOS tube (MON2) in parallel and then serves as the output end of the dynamic OR gate tree.