CN106603042A - Fully symmetrical online monitoring unit capable of stable working within near-threshold region and control circuit - Google Patents
Fully symmetrical online monitoring unit capable of stable working within near-threshold region and control circuit Download PDFInfo
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- CN106603042A CN106603042A CN201611159659.7A CN201611159659A CN106603042A CN 106603042 A CN106603042 A CN 106603042A CN 201611159659 A CN201611159659 A CN 201611159659A CN 106603042 A CN106603042 A CN 106603042A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
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- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00078—Fixed delay
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Abstract
The invention discloses a fully symmetrical online monitoring unit capable of stable working within a near-threshold region and a control circuit. Compared with common online monitoring units, according to the invention, the online monitoring unit does not need to reserve a time delay unit and replaces an original trigger in the common online monitoring unit with a latch, and designs a data jump monitor which has fewer transistors than a shadow latch in the common online monitoring unit. The data jump monitor can work stably within the near-threshold region, has a time delay of inverter magnitudes, has the characteristics of fastness and stability which enable the control system to rapidly respond to alerts, avoids actual time-sequence errors, and finally reduces the area and power consumption of the online monitoring unit maximumly. In addition, according to the invention, since the online monitoring unit uses the latch of which the time borrowing characteristics enable the online monitoring unit to resist errors of circuit time-sequence caused by PVT deviation under near-threshold, the online monitoring unit completely eliminates the time-sequence residual reserved when designed, and has ensured higher power consumption. Also, the invention discloses a control circuit which is in cooperation to the online monitoring unit so as to better achieve functions of the entire system.
Description
Technical field
The present invention relates to IC design Low-power Technology field, is based especially on the self adaptation electricity of online sequential monitoring
Voltage-frequency rate regulation technology field.
Background technology
With developing rapidly for integrated circuit technique, Advanced Manufacturing Technology steps into nanometer era, SoC（System on
Chip）The function of chip is stronger and stronger, and high-performance and low-power consumption are two to pursue a goal greatly all the time, and the two indexs are mutual
Mutually pin down, simple pursuit low-power consumption can cause the huge deterioration of performance.Research discovery, the lowest energy consumption of circuit under advanced technologies
Point is typically in sub-threshold region, and the highest energy efficiency of circuit is then in nearly threshold zone, and supply voltage is from atmospheric area（Also known as superthreshold
Area, STC）When dropping to nearly threshold value up to subthreshold value, circuit delay continues to increase, and index is presented during to nearly threshold value and sub-threshold region
Decline, and efficiency is then presented and first increases the trend for subtracting afterwards, wherein nearly threshold zone efficiency is best.
However, nearly threshold value SoC circuit yet suffers from present important unsolved problem：In conventional voltage area, due to technique
The PVT that the lasting diminution of size causes（Process, Voltage, Temperature）Offset issue, causes traditional VLSI
Temporal constraint under reserved certain time sequence allowance is needed in design to meet worst case.However, into nearly threshold voltage area,
Impact of the PVT deviations to circuit delay is bigger, causes side circuit to reduce except the performance brought in itself due to voltage decline（One
As for conventional voltage 1/10）Outward, the deviation of path delay is also multiplied.So as to need in the design of nearly threshold value it is reserved compared with
The bigger time sequence allowance of traditional design to tackle nearly threshold value under timing skew problem, and these time sequence allowances can cause circuit
Running voltage or frequency are overly conservative, or even offset the efficiency income that nearly threshold zone is come due to voltage drop low strap.
On-line monitoring technique can monitor key path time sequence, and the electricity of real-time regulation chip using monitoring unit on piece
Pressure, frequency, become the powerful measure for capturing time sequence allowance problems of too in traditional integrated circuit design.Online sequential monitoring technology
Can be largely classified into error to correct mistakes type and the class of time series forecasting type two.Wherein, timing error forecasting type monitoring means are not due to needing
Additionally increase system-level Restoration Mechanism and there is advantage, prolong by the way that artificial on crucial data path addition is extra
Late, carry out the possible sequential of prediction circuit nervous, adjust such that it is able to carry out voltage, frequency in advance, prevent what real error from introducing
Recover expense.
Because change is affected bigger by various deviations when low-voltage is downward, common on-line monitoring unit is faced with nothing
Method covers the problem of deviation.Further, since various bigger deviations cause the monitoring window needs of monitoring means under low-voltage
It is reserved greatlyyer, can so make common monitoring means to add more delay units to guarantee monitoring window stomatopod in design
Enough big, this may result in more areas and power dissipation overhead, so as to reduce the income of online sequential monitoring technology.Further, since
Forecasting type on-line monitoring unit needs to ensure the correct of systemic-function, therefore after on-line monitoring unit sends early warning signal, needs
To take measures as quickly as possible, prevent systemic-function from really malfunctioning, this requires that the fast response time of monitoring means, time delay are most
It is possibly little, while requiring that monitoring means sheet being capable of steady operation in nearly threshold zone.Therefore, more small area, lower work(are designed
Consumption, less time delay, nearly threshold zone steady operation on-line monitoring unit it is very necessary.
The content of the invention
Goal of the invention：Supervise in online sequential monitoring system for the super large-scale integration of above-mentioned nearly threshold zone work
Survey the problem and shortage that unit is present, the purpose of the present invention is that design is a kind of being capable of effective observation circuit sequential in nearly threshold zone
Monitoring means, compare common monitoring means, it nearly threshold zone can steady operation, and its area is less, and power consumption is lower, time delay
It is less.For this present invention is alternatively directed to this on-line monitoring unit provides a set of control circuit, realize online so as to significantly more efficient
Sequential is monitored and corresponding voltage-regulation.
Technical scheme
In order to realize foregoing invention purpose, the present invention devises a kind of holohedral symmetry on-line monitoring unit of nearly threshold zone steady operation
With control circuit.The effect of monitoring means is the data transmission scenarios for monitoring critical path end depositor, when circuit sequence it is tight
Zhang Shi, data can just be reached when near rising edge clock, or even reached after rising edge and caused timing error, by prison
Whether the sequential for surveying data jump situation of the critical path end depositor between clock high period to determine circuit is nervous, when
Between clock high period there is saltus step in data, and the early warning signal that monitoring means send is high level.The on-line monitoring unit phase
Than in traditional monitoring unit, devising a kind of data jump monitor, the depositor of former timing path end is substituted for into latch
Device, is controlled by it the process and control of circuit realiration monitoring means early warning signal.
The input signal of described on-line monitoring unit is system operating clock signals and data input signal.Output signal
For data output signal and early warning signal, data input signal is connected to the data input pin of latch and data jump monitor
Data input pin 1, clock signal is connected to the input end of clock of latch and data jump monitor, inside latch
The non-signal of data input signal draws the data input pin 2 for being connected to data jump monitor, and latch is output as data
Output signal, data jump monitor is output as early warning signal；
The data jump monitor is made up of 4 NMOS tubes, 3 PMOSs and 3 phase inverters, and its input is data input letter
Number, the non-signal of data input signal, system operating clock signals, output signal is early warning signal.Wherein, clock signal with
The grid connection of PMOS M1, the source electrode of PMOS M1 is connected with power vd D, the drain electrode of PMOS M1 and the source of PMOS M2
Pole, the source electrode of PMOS M6, the drain electrode of NMOS tube M3, the drain electrode of NMOS tube M5 are connected, while the drain electrode of PMOS M1 is also connected with
To the input of phase inverter INV3；Data input signal is connected with the grid of PMOS M2 and the grid of NMOS tube M4；PMOS
The drain electrode of M2 is connected with the drain electrode of the source electrode of NMOS tube M3 and NMOS tube M4, at the same the drain electrode of PMOS M2 be also connected to it is anti-phase
The input of device INV1；The drain electrode of PMOS M6 is connected with the drain electrode of the source electrode of NMOS tube M5 and NMOS tube M7, at the same V3 with
The input of phase inverter INV2 is connected；The source electrode of NMOS tube M4 and the source electrode of NMOS tube M7 are connected with ground VSS；Data input is believed
Number non-signal be connected with the grid of PMOS M6 and NMOS tube M7, the output of phase inverter INV1 connects with the grid of NMOS tube M5
Connect, the output of phase inverter INV2 is connected with the grid of NMOS tube M3, the output of phase inverter INV3 is early warning signal.
When circuit sequence is nervous, data can just be reached when near rising edge clock, or even be reached after rising edge
And produce saltus step（0 to 1 or 1 to 0）, data jump monitor detects this saltus step and produces early warning signal and be transferred to next
Level circuit.
A kind of holohedral symmetry of nearly threshold zone steady operation monitors the control circuit of unit on-line, mainly includes three parts：X
On-line monitoring unit, m n input dynamic OR gates, clock control and dynamic gate reset signal generation module.The m n inputs are dynamic
The x early warning signal that the on-line monitoring unit of state OR gate real-time collecting x bar critical path end is produced（Pre_error01~Pre_
errorx）And carry out or operate, x, m and n are positive integer（General x>N, works as x<During=n, then only need to 1 n input dynamic or
Door）, produce a total early warning signal and be transferred to clock control and dynamic gate reset signal generation module；Clock control and dynamic gate
Reset signal generation module is received after total early warning signal, immediately system work clock is suspended into a cycle, to ensure circuit
Data do not malfunction, while produce dynamic gate reset signal and pass to the dynamic OR gate of n inputs, for controlling the dynamic OR gate of n inputs
Switch, when reset signal is 1, the dynamic OR gate of n inputs is opened, and is performed in real time or is operated, when reset signal is 0, n inputs
Dynamic OR gate is closed, and low level is exported all the time.
The dynamic OR gate of n inputs is made up of 3 PMOS, n+1 NMOS and phase inverter INV, wherein, NMOS tube MN1 is extremely
The grid of NMOS tube MNn respectively with n early warning signal（Pre_error01~Pre_errorn）It is connected, NMOS tube MN1 to NMOS
The source electrode of pipe MNn is connected with the drain electrode of NMOS tube MN0, drain electrode and PMOS MP0 and the PMOS of NMOS tube MN1 to NMOS tube MNn
The drain electrode connection of pipe MP2, while input of the drain electrode as phase inverter INV；The grid of NMOS tube MN0 and PMOS MP0 with it is dynamic
State door reset signal connects, the source electrode of NMOS tube MN0 with VSS be connected, the source electrode and grid of PMOS MP1, PMOS MP0
Source electrode is connected with power vd D, and the drain electrode of PMOS MP1 is connected with the source electrode of PMOS MP2, the grid of PMOS MP2 with it is anti-
The output connection of phase device INV, the output of phase inverter INV is total early warning signal.
Clock control and dynamic gate reset signal generation module are adopted by clock gating unit PREICG, a rising edge
Sample d type flip flop DFF, phase inverter INVC, two buffer BUF1, BUF2 compositions.The input signal of module is input clock
Signal and total early warning signal, are output as system operating clock signals and dynamic gate reset signal.When input clock signal is connected to
The clock end of clock door control unit and d type flip flop DFF；Total early warning signal as phase inverter INVC input, the output connection of INVC
To the data terminal and the control end of clock gating unit of d type flip flop DFF, the output of d type flip flop DFF is connected to buffer BUF1's
Input, the output of BUF1 is connected to the input of BUF2, and the output of BUF2 is dynamic gate reset signal, clock gating unit
Output be system operating clock signals.
Beneficial effect：Compared to common on-line monitoring unit, the present invention：（1）Number of transistors is less, and area and power consumption reduce.No
The time delay chain for early warning is needed, the d type flip flop in common on-line monitoring unit is substituted for into latch, have also been devised 13 crystalline substances
The data jump monitor of body pipe, in VLSI Design, the cost that replacement monitoring means bring is lower；（2）Work
Make voltage lower, can be in nearly threshold zone steady operation.Symmetrical cmos transmission gate structure is increased inside data jump monitor,
Can be worked more stable with Lossless transport level；（3）Time delay is less, can realize quick early warning.Symmetrical cmos transmission gate design
Fast charging and discharging can be realized, time delay is only phase inverter magnitude；（4）Resist fast speed deviation（Fast variation）, disappear completely
Except time sequence allowance.System can with steady operation near rising edge clock, when due to PVT deviations cause data next clock week
Reach after the rising edge of phase, by the time borrowing of latch（Time borrowing）Characteristic causes circuit data still not have
There is error, so as to the time sequence allowance reserved for PVT deviations is completely eliminated.Based on above-mentioned 4 points, the present invention can enter in nearly threshold zone
The online sequential monitoring of row, further reduces power consumption and improves performance, it is ensured that higher efficiency income.
Description of the drawings
Fig. 1 is monitoring means structure chart；
Fig. 2 is the control circuit structure chart of monitoring means；
Fig. 3 is that n is input into dynamic OR gate structure chart；
Fig. 4 is on-line monitoring unit and its control system overall applicability system diagram；
Fig. 5 is under conventional voltage（1.1V）The integrally-regulated design sketch of system；
Fig. 6 is under low-voltage（0.54V）The integrally-regulated design sketch of system；
Fig. 7 is under low-voltage（0.6V）On-line monitoring technique concrete application regulating effect figure.
Specific embodiment
Illustrate below in conjunction with the accompanying drawings to be described in detail technical solution of the present invention, but protection scope of the present invention not office
It is limited to the embodiment.
As shown in figure 1, a kind of holohedral symmetry on-line monitoring unit of nearly threshold zone steady operation mainly includes：One latch
Device, a data jump monitor.When input signal D is the time of advent later, the rising edge of next clock cycle is alreadyd exceed
When, now monitor unit on-line and be able to detect that this changes and produce early warning signal.Because former trigger has been substituted for lock
Storage, and latch has the characteristic of time borrowing, even if so data are reached after rising edge clock, correct data are still
So next stage trigger, therefore sequential can be passed to still without in violation of rules and regulations by latch.So on-line monitoring unit can be with
Opposing is due to sequential error caused by PVT deviations.
For data jump monitor, when when the system is operating clock signal CK is low level, the conducting of PMOS M1, its drain electrode
It is low level that VVDD exports early warning signal Pre_error by power source charges to high level, after phase inverter INV3 is anti-phase；When
System operating clock signals CK be high level when, PMOS M1 shut-off, if now data input signal D rising edge clock it
After there is saltus step（Whether 0 to 1 or 1 to 0）, will all the early warning signal of high level be produced, make a concrete analysis of as follows：
When data input signal D is initially " 0 ", non-signal DN of the data input signal D drawn from latch inside is
The grid DN of " 1 ", i.e. metal-oxide-semiconductor M6, M7 is " 1 ", and drain electrode V3 is " 0 ", and the output V4 of phase inverter INV2 is " 1 ", when clock rises
Along after data input signal D from " 0 " saltus step to " 1 " when, PMOS M2 is gradually turned off, and NMOS tube M4 is gradually turned on, now by
It is high level in the output V4 of phase inverter INV2, the conducting of NMOS tube M3 will so form the drain electrode VVDD Jing of PMOS M1
The path of metal-oxide-semiconductor M2, M3, M4 to ground VSS electric discharges is crossed, the electric charge of its storage will be released quickly；The non-letter of data input signal D
, from " 1 " saltus step to " 0 ", PMOS M6 is gradually turned on for number DN, but because the electric charge of VVDD is discharged quickly, therefore PMOS M6
Drain electrode V3 remains " 0 ", and now the output V4 of phase inverter INV2 is maintained as " 1 ", and NMOS tube M3 is held on, final PMOS
The electric charge of M1 drain electrode storages is completely released, anti-phase through phase inverter INV3, and saltus step is height by output early warning signal Pre_error
Level.
When data input signal D is initially " 1 ", the conducting of NMOS tube M4, its drain electrode V1 is " 0 ", and phase inverter INV1's is defeated
It is " 1 " to go out V2, and now when data input signal D is from " 1 " saltus step to " 0 " after rising edge clock, data input signal D's is non-
From " 0 " saltus step to " 1 ", PMOS M6 is gradually turned off signal DN, and NMOS tube M7 is gradually turned on, now defeated due to phase inverter INV1
Go out（V2）For high level, the conducting of NMOS tube M5, will so the drain electrode of PMOS M1 be formed（VVDD）Through metal-oxide-semiconductor M5, M6,
The path of M7 to ground VSS electric discharges, the electric charge of its storage will gradually be released；PMOS M2 is gradually turned on, but due to the electricity of VVDD
Lotus is discharged quickly, therefore the drain electrode of PMOS M2（V1）" 0 " is remained, now the output V2 of phase inverter INV1 is maintained as
" 1 ", M5 is held on, and the electric charge of final PMOS M1 drain electrode storage is completely released, output anti-phase through phase inverter INV3
Saltus step is high level by Pre_error.
So can monitor the data jump situation between clock high period to determine circuit by data jump monitor
Whether sequential is nervous, when data generation saltus step is monitored between clock high period, monitors the early warning signal that unit sends on-line
For high level.
The control circuit of the on-line monitoring unit shown in Fig. 2 is mainly made up of three parts：X on-line monitoring unit, m n
The dynamic OR gate of input, clock control and dynamic gate reset signal generation module.Wherein m n input dynamic OR gate real-time collecting x bar
X early warning signal Pre_error01 ~ Pre_errorx of the on-line monitoring unit generation of critical path end is simultaneously carried out or grasped
Make, x, m and n are positive integer（General x>N, works as x<During=n, then 1 n input dynamic OR gate is only needed to）, produce a total early warning letter
Number Or_error is transferred to clock control and reset signal generation module；Clock control and dynamic gate reset signal generation module connect
After receiving total early warning signal Or_error, immediately system work clock is suspended into a cycle, while produce dynamic gate and reset believing
Number irstn simultaneously passes to the dynamic OR gate of n inputs, and for controlling the switch of the dynamic OR gate of n inputs, when irstn is 1, n inputs are dynamic
State OR gate is opened, and is performed in real time or is operated, and when irstn is 0, the dynamic OR gate of n inputs is closed, and low level is exported all the time.
The dynamic OR gate of n inputs shown in Fig. 3, when dynamic gate reset signal irstn is low level, the conducting of PMOS MP0,
Its drain electrode V is charged to high level, and low level is exported after phase inverter INV is anti-phase, and the dynamic OR gate of n inputs is output as low electricity
It is flat, now it is input into dynamic OR gate equivalent to n and is closed；When dynamic gate reset signal irstn is high level, PMOS MP0 is closed
It is disconnected, the conducting of NMOS tube MN0, now when in early warning signal Pre_error01 to Pre_errorn any one signal be high level,
The NMOS tube of its correspondence control will be turned on so that the electric charge on drain electrode V is released into 0, export high after phase inverter INV is anti-phase
Level, the dynamic OR gate output of n inputs keeps high level, now defeated equivalent to n until dynamic gate reset signal irstn reset
Enter dynamic "or" to open, and realize the logic function of "or".
A whole set of sequential monitoring system is applied in physical circuit, its entire block diagram is as shown in figure 4, on-line monitoring unit is inserted
Enter the critical path end that x bar grizzl(e)ies are chosen in circuit core, usual x>N, needs m n input dynamic OR gate, and m and n is just whole
Number, x early warning signal of generation（pre_error01~pre_errorx）It is linked into the dynamic OR gate of multiple n inputs（If x<=n is then
Only need a n input dynamic OR gate）, the total early warning signal Or_error of final output one, is transferred to clock control and reset is believed
Number generation module；Clock control and dynamic gate reset signal generation module are received after total early warning signal Or_error, immediately will
System work clock suspends a cycle, while produce dynamic gate reset signal irstn and pass to the dynamic OR gate of n inputs, with
Guarantee the correct of systemic-function.
One concrete case
A kind of holohedral symmetry on-line monitoring unit of nearly threshold zone steady operation is embodied as in case with one of control circuit, if
A test circuit is counted, and this set system has been applied to into test circuit system.The n that the design is adopted is input into the defeated of dynamic OR gate
Enter number and be equal to 1 for 8, m, based on SMIC 40nm technology libraries, its process corner is TT, and temperature is 25 degrees Celsius.
Fig. 5 is under conventional voltage（1.1V）The integrally-regulated design sketch of system, in figure, abscissa is time shafts, and unit is
Second, vertical coordinate is voltage axis, and unit is volt, and input_clk is its exterior input clock, and CK is to be after control system
System work clock, D is data input signal, and pre_error is the pre- of the on-line monitoring unit output of wherein one critical path
Alert signal, Or_error is the total early warning signal after the dynamic OR gate of 8 inputs is processed, and irstn is answering for 8 inputs dynamic OR gate
Position signal.As seen from the figure, the saltus step of data D for occurring during clock low, monitors the early warning signal of unit output on-line
For " 0 ", and " 0 " of data D occurred between clock high period monitors unit on-line to " 1 " saltus step or " 1 " to " 0 " saltus step
The early warning signal pre_error of output be " 1 ", then pass through 8 inputs dynamic OR gate or operation after output signal Or_error
For " 1 ", clock control and dynamic gate reset signal generation module are sampled after " 1 " of Or_error, by the system next cycle
System work clock CK suspend a cycle, immediately will system work clock CK suspend a cycle after recover again, to avoid
The continuous transmission of time borrowing, so as to ensure that the time that data have abundance before next rising edge clock is reached correctly is transferred to
The next stage depositor of latch, while producing low level dynamic OR gate reset signal irstn, by Or_error low electricity is set to
It is flat, complete the control of whole system.
Fig. 6 is under nearly threshold zone low-voltage（0.54V）The integrally-regulated design sketch of system, it is similar with Fig. 5, it is whole in 0.54V
Set system still can well complete function, when data saltus step between clock high period, the high electricity of on-line monitoring unit output
Flat early warning signal, the dynamic OR gate of 8 inputs receives the signal and is transferred to clock control and the dynamic gate reset letter of next stage
Number generation module, finally realizes a whole set of control.
Fig. 7 is the regulating effect figure that nearly threshold zone the whole series on-line monitoring technique is applied to physical circuit, and in figure, abscissa is
Time shafts, vertical coordinate is voltage axis, and VDD is supply voltage, the drop voltage signal that Volt_down sends for on-line monitoring system,
Volt_up is up voltage signal, and pre_error is to monitor total effective early warning signal that unit sends on-line, and CK is system work
Make clock, op_out is system functional verification signal（High level represents that function is correct, initial a period of time for low level be due to
System is in initial phase）.As seen from the figure, when present operating voltage is 600mV, without early warning signal, on-line monitoring technique
Detecting system still has surplus, therefore sends buck signal to reduce power consumption, and when voltage is reduced to 560mV, monitoring means are sent out
Go out effective early warning signal, on-line monitoring system sends immediately boost signal, while system clock is suspended one by clock control system
The individual cycle is correct with assurance function, when boosting and buck signal cross occurrence represent that system margin is farthest disappeared
Remove, the stable running voltage in 580mV of final system, in said process, op_out keeps drawing high, and systemic-function is correct.
Fig. 5, Fig. 6 and Fig. 7 can be seen that the present invention and be applied in actual prediction matrix in monitoring technology, can include
Row clock and voltage-regulation are entered according to the real work situation of circuit under the super wide voltage of nearly threshold zone, so as to ensure in circuit work(
Correctly situation time sequence allowance can be as far as possible reduced, so as to reduce power consumption.
Claims (5)
1. a kind of holohedral symmetry on-line monitoring unit of nearly threshold zone steady operation, is monitored by a latch, a data jump
Device is constituted, and the input signal of described on-line monitoring unit is system operating clock signals（CK）And data input signal（D）；It is defeated
Go out signal for data output signal（QF）And early warning signal（Pre_error）, data input signal（D）It is connected to the number of latch
According to the data input pin 1 of input and data jump monitor, clock signal（CK）It is connected to latch and data jump monitoring
The input end of clock of device, by the data input signal inside latch（D）Non-signal（DN）Extraction is connected to data jump prison
The data input pin 2 of device is surveyed, latch is output as data output signal（QF）, data jump monitor is output as early warning to be believed
Number（Pre_error）；
It is characterized in that：The data jump monitor is made up of 4 NMOS tubes, 3 PMOSs and 3 phase inverters, its input
For data input signal（D）, data input signal（D）Non-signal（DN）, system operating clock signals（CK）, output signal is
Early warning signal（Pre_error）；Wherein, clock signal（CK）It is connected with the grid of PMOS M1, source electrode and the electricity of PMOS M1
Source VDD is connected, the drain electrode of PMOS M1（VVDD）With the source electrode of PMOS M2（VVDD）, PMOS M6 source electrode（VVDD）,
The drain electrode of NMOS tube M3（VVDD）, NMOS tube M5 drain electrode（VVDD）It is connected, while the drain electrode of PMOS M1（VVDD）It is also connected with
To the input of phase inverter INV3；Data input signal（D）It is connected with the grid of PMOS M2 and the grid of NMOS tube M4；PMOS
The drain electrode of pipe M2（V1）With the source electrode of NMOS tube M3（V1）And the drain electrode of NMOS tube M4（V1）It is connected, while the leakage of PMOS M2
Pole（V1）It is also connected to the input of phase inverter INV1；The drain electrode of PMOS M6（V3）With the source electrode of NMOS tube M5（V3）And
The drain electrode of NMOS tube M7（V3）It is connected, while the drain electrode of PMOS M6（V3）Also it is connected with the input of phase inverter INV2； NMOS
The source electrode of pipe M4 and the source electrode of NMOS tube M7 are connected with ground VSS；Data input signal（D）Non-signal（DN）With PMOS M6
The grid connection of grid and NMOS tube M7, the output of phase inverter INV1（V2）It is connected with the grid of NMOS tube M5, phase inverter INV2
Output（V4）It is connected with the grid of NMOS tube M3, the output of phase inverter INV3 is early warning signal（Pre_error）.
2. a kind of holohedral symmetry of nearly threshold zone steady operation monitors the control circuit of unit on-line, mainly includes three parts：Respectively
It is arranged on x on-line monitoring unit of x bar critical paths end, m n input dynamic OR gates, clock control and dynamic gate to reset
Signal generator module, x, m and n are positive integer, it is characterised in that：
The x early warning signal that x on-line monitoring unit described in the m n inputs dynamic OR gate real-time collecting is produced（Pre_
error01~Pre_errorx）And carry out or operate, produce a total early warning signal（Or_error）Be transferred to clock control and
Dynamic gate reset signal generation module；Clock control and dynamic gate reset signal generation module receive effectively total early warning signal
（Or_error）Afterwards, immediately by system work clock（CK）Suspend a cycle and be then passed to each sequential logic, while
Produce dynamic gate reset signal（irstn）And pass to the dynamic OR gate of each n input.
3. a kind of holohedral symmetry of nearly threshold zone steady operation according to claim 2 monitors the control circuit of unit on-line,
It is characterized in that：
The n inputs dynamic OR gate is made up of 3 PMOS, n+1 NMOS and phase inverter INV, wherein, NMOS tube MN1 is extremely
The grid of NMOS tube MNn respectively with n early warning signal（Pre_error01~Pre_errorn）It is connected, NMOS tube MN1 to NMOS
The source electrode of pipe MNn is connected with the drain electrode of NMOS tube MN0, the drain electrode of NMOS tube MN1 to NMOS tube MNn（V）With PMOS MP0 and
The drain electrode of PMOS MP2（V）Connection, while the drain electrode（V）As the input of phase inverter INV；NMOS tube MN0 and PMOS MP0
Grid and dynamic gate reset signal（irstn）Connection, the source electrode of NMOS tube MN0 is connected with ground VSS, the source electrode of PMOS MP1
It is connected with power vd D with the source electrode of grid, PMOS MP0, the drain electrode of PMOS MP1 is connected with the source electrode of PMOS MP2,
The grid of PMOS MP2 and the output of phase inverter INV（Or_error）Connection, the output of phase inverter INV（Or_error）As
Total early warning signal.
4. a kind of holohedral symmetry of nearly threshold zone steady operation according to claim 2 monitors the control circuit of unit on-line,
It is characterized in that：
The clock control and dynamic gate reset signal generation module are by a clock gating unit（PREICG）, a rising edge
Sampling d type flip flop DFF, phase inverter INVC, two buffer BUF1, BUF2 compositions；The input signal of module is for during input
Clock signal（input_clk）With total early warning signal（Or_error）, it is output as system operating clock signals（CK）It is multiple with dynamic gate
Position signal（irstn）；Input clock signal（input_clk）It is connected to the clock end of clock gating unit and d type flip flop DFF；
Total early warning signal（Or_error）As the input of phase inverter INVC, the output of INVC be connected to the data terminal of d type flip flop DFF and
The control end of clock gating unit, the output of d type flip flop DFF is connected to the input of buffer BUF1, and buffer BUF1's is defeated
Go out to be connected to the input of buffer BUF2, the output of buffer BUF2 is dynamic gate reset signal（irstn）, Clock gating
The output of unit is system operating clock signals（CK）.
5. a kind of holohedral symmetry of nearly threshold zone steady operation according to claim 2 monitors the control circuit of unit on-line,
It is characterized in that the on-line monitoring unit, is made up of, described on-line monitoring a latch, a data jump monitor
The input signal of unit is system operating clock signals（CK）And data input signal（D）；Output signal is data output signal
（QF）And early warning signal（Pre_error）, data input signal（D）It is connected to the data input pin and data jump prison of latch
Survey the data input pin 1 of device, clock signal（CK）It is connected to the input end of clock of latch and data jump monitor, latch
Internal data input signal（D）Non-signal（DN）Be connected to the data input pin 2 of data jump monitor, latch it is defeated
Go out for data output signal（QF）, data jump monitor is output as early warning signal（Pre_error）；
The data jump monitor is made up of 4 NMOS tubes, 3 PMOSs and 3 phase inverters, and its input is data input letter
Number（D）, data input signal（D）Non-signal（DN）, system work clock（CK）, output signal is early warning signal（Pre_
error）；Wherein, clock signal（CK）It is connected with the grid of PMOS M1, the source electrode of PMOS M1 is connected with power vd D, PMOS
The drain electrode of pipe M1（VVDD）With the source electrode of PMOS M2（VVDD）, PMOS M6 source electrode（VVDD）, the drain electrode of NMOS tube M3
（VVDD）, NMOS tube M5 drain electrode（VVDD）It is connected, while the drain electrode of PMOS M1（VVDD）It is also connected to phase inverter INV3's
Input；Data input signal 1（D）It is connected with the grid of PMOS M2 and the grid of NMOS tube M4；The drain electrode of PMOS M2
（V1）With the source electrode of NMOS tube M3（V1）And the drain electrode of NMOS tube M4（V1）It is connected, while the drain electrode of PMOS M2（V1）Also connect
It is connected to the input of phase inverter INV1；The drain electrode of PMOS M6（V3）With the source electrode of NMOS tube M5（V3）And the leakage of NMOS tube M7
Pole（V3）It is connected, while the drain electrode of PMOS M6（V3）Also it is connected with the input of phase inverter INV2；The source electrode of NMOS tube M4 and
The source electrode of NMOS tube M7 is connected with ground VSS；Data input signal（D）Non-signal（DN）With the grid and NMOS tube of PMOS M6
The grid connection of M7, the output of phase inverter INV1（V2）It is connected with the grid of NMOS tube M5, the output of phase inverter INV2（V4）With
The grid connection of NMOS tube M3, the output of phase inverter INV3 is early warning signal（Pre_error）.
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