CN101951256A - Single-phase clock pass transistor adiabatic logic circuit, full adder and 5-2 compressor - Google Patents

Abstract

The invention discloses a single-phase clock pass transistor adiabatic logic circuit. The circuit is characterized by comprising a logic assignment circuit and an energy regeneration circuit, wherein the energy regeneration circuit consists of two pMOS transistors, namely a first pMOS transistor and a second pMOS transistor; the source of the first pMOS transistor and the source of the second pMOS transistor are connected in parallel with a power clock end; and the logic assignment circuit consists of four nMOS pass transistors, namely, a fifth nMOS pass transistor, a sixth nMOS pass transistor, a seventh nMOS pass transistor and an eighth nMOS pass transistor. The circuit has the advantages of combining the advantages of the single-phase power clock adiabatic logic (CAL) and complementary pass transistor logic (CPL), only one power clock CLK is needed, an auxiliary clock (CX and CX') alternately controls each stage of logic circuit, and the frequency of the circuit is half that of the power clock CLK; the single-phase power clock is used by a full adder on the basis, so that complexity of the clock circuit is reduced, the clock circuit is easier to generate, and the area of the circuit is greatly reduced; and a 5-2 compressor only consists of the full adder and has a simple and normative circuit structure and can compress more digits at one time.

Description

A kind of single phase clock transfer tube heat insulation logic circuit and full adder and 5-2 compressor reducer

Technical field

The present invention relates to a kind of 5-2 compressor reducer, especially relate to a kind of single phase clock transfer tube heat insulation logic circuit and full adder and 5-2 compressor reducer.

Background technology

At present VLSI (very large scale integrated circuit) designs technology has entered the nanometer stage, no matter from the performance and the cost consideration of chip itself, or the consideration of the angle in electronic product market, power consumption has become a key index of performance of integrated circuits gradually.The low power consumption integrated circuit design has become the focus and the difficult point of present integrated circuit (IC) design.Traditional cmos circuit employing DC power supply, its energy are with the irreversible formal transformation of electric energy to heat energy, though can be by reducing supply voltage, reduction node capacitor and the redundant saltus step of minimizing switch reduce power consumption, and its Power Cutback amplitude is limited.Energy recovery type circuit also claims adiabatic circuits, it is a kind of brand-new Low-power Technology of rising in recent ten years, it is a kind of new type integrated circuit designing technique that obtains low-power consumption from the angle that changes power conversion, its basic principle is to adopt ac power supply, by reclaiming the electric charge of node capacitor, energy in the recycling circuit, thus realize low-power consumption, so the energy consumption of energy recovery type digital integrated circuit significantly reduces.Adiabatic circuits has obtained very big achievement through nearly ten years development on circuit design, proposed a lot of heat insulation logic circuit types at present, as PAL-2N, ECRL, 2N-2N2P, and CAL and CPAL etc.These circuit all have good low-power consumption characteristic, but these circuit all need the polyphase ac power clock.The polyphase ac power clock produces circuit need produce a plurality of sinusoidal power clocks with fixed skew, and the circuit structure complexity has increased circuit power consumption.Adopt the adiabatic circuits of polyphase ac power clock need insert a lot of buffers in addition in circuit, to realize correct pile line operation, this has increased the power consumption of circuit undoubtedly again, and therefore circuit area also can increase.

Summary of the invention

Technical problem to be solved by this invention provides a kind of single phase clock transfer tube heat insulation logic circuit and full adder and 5-2 compressor reducer, and its clock circuit more is easy to generate, and the area of circuit reduces greatly, has correct logic functions and low-power consumption feature.

The present invention solves the problems of the technologies described above the technical scheme that is adopted: a kind of single phase clock transfer tube heat insulation logic circuit, comprise logical assignment circuit and energy recovery circuit, described energy recovery circuit is that pMOS pipe and the 2nd pMOS pipe constitute by two pMOS pipes, the source electrode of the source electrode of a described pMOS pipe and described the 2nd pMOS pipe is connected to the power clock end, the drain electrode of a described pMOS pipe is connected with the source electrode of a nMOS pipe, the drain electrode of described the 2nd pMOS pipe is connected with the source electrode of the 2nd nMOS pipe, the drain electrode of the drain electrode of a described nMOS pipe and described the 2nd nMOS pipe is connected to ground, the grid of described the 2nd pMOS pipe, the drain electrode of the grid of described the 2nd nMOS pipe and a described pMOS pipe is connected to signal output part, the grid of a described pMOS pipe, the drain electrode of the grid of a described nMOS pipe and described the 2nd pMOS pipe is connected to the inversion signal output, described signal output part is connected with the source electrode of the 3rd nMOS pipe, the grid of described the 3rd nMOS pipe is connected with the auxiliary clock signal end, described inversion signal output is connected with the source electrode of the 4th nMOS pipe, the grid of described the 4th nMOS pipe is connected with anti-phase auxiliary clock signal end, described logical assignment circuit is the 5th a nMOS pipe by four nMOS transfer tubes, the 6th nMOS pipe, the 7th nMOS pipe and the 8th nMOS pipe constitute, the source electrode of the source electrode of described the 5th nMOS pipe and the 6th nMOS pipe is connected with the drain electrode of described the 3rd nMOS pipe, the source electrode of the source electrode of described the 7th nMOS pipe and described the 8th nMOS pipe is connected with the drain electrode of described the 4th nMOS pipe, the drain electrode of described the 5th nMOS pipe is connected with first signal input part, the drain electrode of described the 6th nMOS pipe is connected with the secondary signal input, the drain electrode of described the 7th nMOS pipe is connected with the 3rd signal input part, the drain electrode of described the 8th nMOS pipe is connected with the 4th signal input part, the grid of the grid of described the 5th nMOS pipe and described the 8th nMOS pipe is connected to the 5th signal input part, and the grid of the grid of described the 6th nMOS pipe and described the 7th nMOS pipe is connected to the 6th signal input part.

Use the full adder of above-mentioned single phase clock transfer tube heat insulation logic circuit, comprise that carry signal produces circuit and summing signal produces circuit, it is the 9th nMOS pipe by the first single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipes that described carry signal produces circuit, the tenth nMOS pipe, the 11 nMOS pipe, the 12 nMOS pipe, the 13 nMOS pipe, the 14 nMOS pipe, the 15 nMOS pipe and the 16 nMOS pipe constitute, the described first single phase clock transfer tube heat insulation logic circuit comprises the first logical assignment circuit and first energy recovery circuit, described first energy recovery circuit is that pMOS pipe and the 2nd pMOS pipe constitute by two pMOS pipes, the drain electrode of a described pMOS pipe is connected with the source electrode of a nMOS pipe, the drain electrode of described the 2nd pMOS pipe is connected with the source electrode of the 2nd nMOS pipe, the drain electrode of the drain electrode of a described nMOS pipe and described the 2nd nMOS pipe is connected to ground, the grid of described the 2nd pMOS pipe, the drain electrode of the grid of described the 2nd nMOS pipe and a described pMOS pipe is connected to the carry signal output, the grid of a described pMOS pipe, the drain electrode of the grid of a described nMOS pipe and described the 2nd pMOS pipe is connected to anti-phase carry signal output, described carry signal output is connected with the source electrode of the 3rd nMOS pipe, described anti-phase carry signal output is connected with the source electrode of the 4th nMOS pipe, the described first logical assignment circuit is the 5th a nMOS pipe by four nMOS transfer tubes, the 6th nMOS pipe, the 7th nMOS pipe and the 8th nMOS pipe constitute, the source electrode of the source electrode of described the 5th nMOS pipe and the 6th nMOS pipe is connected with the drain electrode of described the 3rd nMOS pipe, the source electrode of the source electrode of described the 7th nMOS pipe and described the 8th nMOS pipe is connected with the drain electrode of described the 4th nMOS pipe, the source electrode of the source electrode of the drain electrode of described the 5th nMOS pipe and described the 9th nMOS pipe and described the tenth nMOS pipe also connects, the source electrode of the drain electrode of described the 6th nMOS pipe and the source electrode of described the 11 nMOS pipe and described the 12 nMOS pipe also connects, the source electrode of the drain electrode of described the 7th nMOS pipe and the source electrode of described the 13 nMOS pipe and described the 14 nMOS pipe also connects, the source electrode of the drain electrode of described the 8th nMOS pipe and the source electrode of described the 15 nMOS pipe and described the 16 nMOS pipe also connects, it is the 25 nMOS pipe by the second single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipes that described summing signal produces circuit, the 26 nMOS pipe, the 27 nMOS pipe, the 28 nMOS pipe, the 29 nMOS pipe, the 30 nMOS pipe, the 31 nMOS pipe and the 32 nMOS pipe constitute, the described second single phase clock transfer tube heat insulation logic circuit comprises the second logical assignment circuit and second energy recovery circuit, described second energy recovery circuit is that the 3rd pMOS pipe and the 4th pMOS pipe constitute by two pMOS pipes, the drain electrode of described the 3rd pMOS pipe is connected with the source electrode of the 17 nMOS pipe, the drain electrode of described the 4th pMOS pipe is connected with the source electrode of the 18 nMOS pipe, the drain electrode of described the 17 nMOS pipe and the drain electrode of described the 18 nMOS pipe are connected to ground, the grid of described the 4th pMOS pipe, the drain electrode of the grid of described the 18 nMOS pipe and described the 3rd pMOS pipe is connected to the summing signal output, the grid of described the 3rd pMOS pipe, the drain electrode of the grid of described the 17 nMOS pipe and described the 4th pMOS pipe is connected to anti-phase summing signal output, described summing signal output is connected with the source electrode of the 19 nMOS pipe, described anti-phase summing signal output is connected with the source electrode of the 20 nMOS pipe, the described second logical assignment circuit is the 21 a nMOS pipe by four nMOS transfer tubes, the 22 nMOS pipe, the 23 nMOS pipe and the 24 nMOS pipe constitute, the source electrode of described the 21 nMOS pipe is connected with the drain electrode of described the 19 nMOS pipe with the source electrode of the 22 nMOS pipe, the source electrode of described the 23 nMOS pipe is connected with the drain electrode of described the 20 nMOS pipe with the source electrode of the 24 nMOS pipe, the source electrode of the drain electrode of described the 21 nMOS pipe and the source electrode of described the 25 nMOS pipe and described the 26 nMOS pipe also connects, the source electrode of the drain electrode of described the 22 nMOS pipe and the source electrode of described the 27 nMOS pipe and described the 28 nMOS pipe also connects, the source electrode of the drain electrode of described the 23 nMOS pipe and the source electrode of described the 29 nMOS pipe and described the 30 nMOS pipe also connects, the source electrode of the drain electrode of described the 24 nMOS pipe and the source electrode of described the 31 nMOS pipe and described the 32 nMOS pipe also connects, the source electrode of a described pMOS pipe, the source electrode of described the 2nd pMOS pipe, the source electrode of the source electrode of described the 3rd pMOS pipe and described the 4th pMOS pipe is connected to the power clock end, the grid of described the 3rd nMOS pipe is connected with the auxiliary clock signal end with the grid of described the 19 nMOS pipe, the grid of described the 4th nMOS pipe is connected with anti-phase auxiliary clock signal end with the grid of described the 20 nMOS pipe, the grid of described the 6th nMOS pipe, the grid of described the 7th nMOS pipe, the drain electrode of described the 9th nMOS pipe, the drain electrode of described the 11 nMOS pipe, the drain electrode of described the 25 nMOS pipe, the drain electrode of described the 27 nMOS pipe, the drain electrode of described the 29 nMOS pipe and the drain electrode of described the 31 nMOS pipe are connected to the first addend input, the grid of described the 5th nMOS pipe, the grid of described the 8th nMOS pipe, the drain electrode of described the 13 nMOS pipe, the drain electrode of described the 15 nMOS pipe, the drain electrode of described the 26 nMOS pipe, the drain electrode of described the 28 nMOS pipe, the drain electrode of described the 30 nMOS pipe and the drain electrode of described the 32 nMOS pipe are connected to the first addend inverting input, the grid of described the tenth nMOS pipe, the grid of described the 11 nMOS pipe, the grid of described the 13 nMOS pipe, the grid of described the 16 nMOS pipe, the grid of described the 26 nMOS pipe, the grid of described the 27 nMOS pipe, the grid of described the 30 nMOS pipe and the grid of described the 31 nMOS pipe are connected to the second addend input, the grid of described the 9th nMOS pipe, the grid of described the 12 nMOS pipe, the grid of described the 14 nMOS pipe, the grid of described the 15 nMOS pipe, the grid of described the 25 nMOS pipe, the grid of described the 28 nMOS pipe, the grid of described the 29 nMOS pipe and the grid of described the 32 nMOS pipe are connected to the second addend inverting input, the drain electrode of described the tenth nMOS pipe, the drain electrode of described the 12 nMOS pipe, the grid of described the 22 nMOS pipe and the grid of described the 23 nMOS pipe are connected to the 3rd addend input, the drain electrode of described the 14 nMOS pipe, the drain electrode of described the 16 nMOS pipe, the grid of described the 21 nMOS pipe and the grid of described the 24 nMOS pipe are connected to the 3rd addend inverting input.

Use the 5-2 compressor reducer of above-mentioned full adder, it is by first full adder, second full adder and the 3rd full adder cascade form, the first addend input of described first full adder is connected with first input signal, the second addend input of described first full adder is connected with second input signal, the 3rd addend input of described first full adder is connected with the 3rd input signal, the first addend input of described second full adder is connected with the carry signal output of first full adder of upper level 5-2 compressor reducer, the second addend input of described second full adder is connected with the summing signal output of described first full adder, the 3rd addend input of described second full adder is connected with the 4th input signal, the first addend input of described the 3rd full adder is connected with the carry signal output of second full adder of upper level 5-2 compressor reducer, the second addend input of described the 3rd full adder is connected with the summing signal output of described second full adder, and the 3rd addend input of described the 3rd full adder is connected with the 5th input signal.

Compared with prior art, the invention has the advantages that the advantage of single phase clock transfer tube heat insulation logic circuit of the present invention in conjunction with single-phase power clock adiabatic logic (CAL) and complementary transfer tube logic (CPL), only need same power clock CLK, and auxiliary clock (CX and

) alternately control each level logic circuit, its frequency is half of power clock CLK frequency; Only need to change the connection of the input signal of four transfer tubes of CAL-CPL logical assignment part among Fig. 1, and the structure of unnecessary change basic circuit can obtain as Fig. 2, Fig. 3 and 2 inputs and door shown in Figure 4,2 inputs or door, 2 input XOR gate.

Full adder of the present invention uses the single-phase power clock, has reduced the complexity of clock circuit, and clock circuit more is easy to generate like this, and the area of circuit also can reduce greatly simultaneously.In addition, because the utilization of the logical assignment circuit part of circuit of the present invention is the structure of CPL circuit, this circuit structure has modular characteristics, they all take identical topological structure, be the arrangement difference of input, so the design of circuit is fairly simple, structure also compares standard, this makes that the design of this class cell library is very simple, and the area of circuit is also littler.Compare with traditional full adder circuit based on static CMOS, because element circuit of the present invention has identical circuit structure, so the time-delay of its circuit, line is all relative with area to be reduced.

The present invention is applied to single-phase adiabatic full adder circuit in the element circuit 5-2 compressor reducer of multiplier, and the 5-2 compressor circuit only is made of full adder, the circuit structure simple specification.Than the 4-2 compressor reducer, the once compressible figure place of 5-2 compressor reducer is more, can reduce the number of compressor reducer like this, optimizes the structure of multiplier circuit, simultaneously, because adiabatic circuits has lower power consumption, can realize the design of low-consumption multiplier like this.Single-phase adiabatic full adder and 5-2 compressor reducer are carried out simulating, verifying, and they have correct logic functions and low-power consumption feature the simulation result proof.

Adopt PTM 90nm and PTM 45nm CMOS technology device parameters, above-mentioned single-phase adiabatic full adder and 5-2 compressor reducer are carried out functional simulation.Fig. 7 has provided the analog waveform based on the single-phase adiabatic full adder of single-phase transfer tube clock adiabatic logic, analog result shows that the single-phase adiabatic full adder based on single phase clock transfer tube adiabatic logic has correct logic functions, Fig. 8 and Fig. 9 have provided single-phase adiabatic full adder circuit of the present invention and static CMOS full adder respectively under the different operating frequency, the comparison of phase energy consumption weekly, compare with the full adder of static CMOS, by Fig. 8 and Fig. 9 as can be known, single-phase adiabatic full adder circuit of the present invention has good low-power consumption effect.

Figure 10 is the structural representation of 5-2 compressor reducer of the present invention, the functional simulation figure that Figure 11 is the 5-2 compressor reducer under given five inputs and two prime carry signals, and analog result shows that single-phase adiabatic 5-2 compressor reducer of the present invention has correct logic functions.Figure 12 and Figure 13 are respectively 5-2 compressor reducer (the adiabatic 5-2 compressor reducers of single phase clock transfer tube of three kinds of Different Logic structures, single phase clock adiabatic logic CAL 5-2 compressor reducer and static CMOS 5-2 compressor reducer), the energy consumption comparison diagram of phase weekly under different process and different operating frequency.Under the 90nm CMOS technology, under the 100MHz operating frequency, the adiabatic 5-2 compressor reducer of single phase clock transfer tube is with respect to static CMOS 5-2 compressor reducer, the phase energy consumption saves about 72.8% weekly, under the 45nm CMOS technology, under the 100MHz operating frequency, the adiabatic 5-2 compressor reducer of single phase clock transfer tube is with respect to static CMOS 5-2 compressor reducer, and the phase energy consumption saves about 63.6% weekly.We also will compare with respect to the energy consumption saving situation of 5-2 compressor reducer under identical operating frequency based on CAL based on the 5-2 compressor reducer of CAL-CPL simultaneously, under the 90nm CMOS technology, Power Cutback rate maximum can reach 18.34%, under the 45nm CMOS technology, Power Cutback rate maximum can reach 15.01%.

Description of drawings

Fig. 1 is structural representation, expression graphical diagram and the clock figure of single-phase transfer tube clock adiabatic logic basic circuit;

Fig. 2 is the structural representation and the expression graphical diagram of single-phase transfer tube clock adiabatic logic and door;

Fig. 3 is the structural representation and the expression graphical diagram of single-phase transfer tube clock adiabatic logic or door;

Fig. 4 is the structural representation and the expression graphical diagram of single-phase transfer tube clock adiabatic logic XOR gate;

Fig. 5 is for to represent graphical diagram based on the single-phase adiabatic full adder of CAL-CPL;

Fig. 6 (a) is the carry signal generation circuit based on the single-phase adiabatic full adder of CAL-CPL;

Fig. 6 (b) is the summing signal generation circuit based on the single-phase adiabatic full adder of CAL-CPL;

Fig. 7 is the functional simulation waveform of full adder of the present invention;

Fig. 8 for full adder of the present invention when 90nm technology under the different operating frequency with the static CMOS full adder energy consumption comparison diagram of phase weekly;

Fig. 9 for full adder of the present invention when 45nm technology under the different operating frequency with the static CMOS full adder energy consumption comparison diagram of phase weekly;

Figure 10 is the structural representation of 5-2 compressor reducer of the present invention;

Figure 11 is the functional simulation waveform of 5-2 compressor reducer of the present invention;

Figure 12 for 5-2 compressor reducer of the present invention when 90nm technology under the different operating frequency with the static CMOS 5-2 compressor reducer energy consumption comparison diagram of phase weekly;

Figure 13 for 5-2 compressor reducer of the present invention when 45nm technology under the different operating frequency with the static CMOS 5-2 compressor reducer energy consumption comparison diagram of phase weekly.

Embodiment

Embodiment describes in further detail the present invention below in conjunction with accompanying drawing.

Embodiment one: as shown in Figure 1, single phase clock transfer tube heat insulation logic circuit, form by logical assignment circuit and energy recovery circuit, wherein energy recovery circuit is made of pMOS pipe P1 and the 2nd pMOS pipe P2, clamper is made of nMOS pipe N1 and the 2nd nMOS pipe N2, be used to avoid output node unsettled, CX is used for control input signals and the auxiliary clock signal introduced, it is to control by the 3rd nMOS pipe N3 and the 4th nMOS pipe N4, the source electrode of the one pMOS pipe P1 and the 2nd pMOS pipe P2 all is connected to power clock end CLK, substrate is connected on the high level, the drain electrode of the one pMOS pipe P1 is connected with the source electrode of nMOS pipe N1, the drain electrode of the 2nd pMOS pipe P2 is connected with the source electrode of the 2nd nMOS pipe N2, the drain electrode of the drain electrode of the one nMOS pipe N1 and the 2nd nMOS pipe N2 is connected to ground, the grid of the 2nd pMOS pipe P2, the drain electrode of the grid of the 2nd nMOS pipe N2 and pMOS pipe P1 is connected to signal output part OUT, the grid of pMOS pipe P1, the drain electrode of the grid of the one nMOS pipe N1 and the 2nd pMOS pipe P2 is connected to the inversion signal output

Signal output part OUT is connected with the source electrode of the 3rd nMOS pipe N3, and the grid of the 3rd nMOS pipe N3 is connected the inversion signal output with auxiliary clock signal end CX

Be connected grid and the anti-phase auxiliary clock signal end of the 4th nMOS pipe N4 with the source electrode of the 4th nMOS pipe N4

Connect, the logical assignment circuit is the 5th nMOS pipe N5 by four nMOS transfer tubes, the 6th nMOS manages N6, the 7th nMOS pipe N7 and the 8th nMOS pipe N8 constitute, the source electrode of the source electrode of the 5th nMOS pipe N5 and the 6th nMOS pipe N6 is connected with the drain electrode of the 3rd nMOS pipe N3, the source electrode of the source electrode of the 7th nMOS pipe N7 and the 8th nMOS pipe N8 is connected with the drain electrode of the 4th nMOS pipe N4, the drain electrode of the 5th nMOS pipe N5 is connected with the first signal input part IN1, the drain electrode of the 6th nMOS pipe N6 is connected with secondary signal input IN2, the drain electrode of the 7th nMOS pipe N7 is connected with the 3rd signal input part IN3, the drain electrode of the 8th nMOS pipe N8 is connected with the 4th signal input part IN4, the grid of the grid of the 5th nMOS pipe N5 and the 8th nMOS pipe N8 is connected to the 5th signal input part IN5, and the grid of the grid of the 6th nMOS pipe N6 and the 7th nMOS pipe N7 is connected to the 6th signal input part IN6.

Single phase clock transfer tube heat insulation logic circuit in the present embodiment only needs to change the assignment of input port, just can obtain 2 inputs as shown in Figure 2 and door, 2 inputs shown in Figure 3 or door and shown in Figure 42 and import XOR gate.

Embodiment two: the graphical diagram of single-phase adiabatic full adder of the present invention as shown in Figure 5, A, B, C _iBe three addend input ports of full adder, CLK is the power clock end, CX is the auxiliary clock signal end, C is the carry signal output of full adder, S is the summing signal output of full adder, it produces circuit by carry signal and summing signal generation circuit is formed, carry signal produces circuit shown in Fig. 6 (a), by the first single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipes is the 9th nMOS pipe N9, the tenth nMOS manages N10, the 11 nMOS manages N11, the 12 nMOS manages N12, the 13 nMOS manages N13, the 14 nMOS manages N14, the 15 nMOS pipe N15 and the 16 nMOS pipe N16 constitute, the first single phase clock transfer tube heat insulation logic circuit comprises the first logical assignment circuit and first energy recovery circuit, first energy recovery circuit is made of pMOS pipe P1 and the 2nd pMOS pipe P2, clamper is made of nMOS pipe N1 and the 2nd nMOS pipe N2, be used to avoid output node unsettled, the drain electrode of the one pMOS pipe P1 is connected with the source electrode of nMOS pipe N1, the drain electrode of the 2nd pMOS pipe P2 is connected with the source electrode of the 2nd nMOS pipe N2, the drain electrode of the drain electrode of the one nMOS pipe N1 and the 2nd nMOS pipe N2 is connected to ground, the grid of the 2nd pMOS pipe P2, the drain electrode of the grid of the 2nd nMOS pipe N2 and pMOS pipe P1 is connected to carry signal output C, the grid of pMOS pipe P1, the drain electrode of the grid of the one nMOS pipe N1 and the 2nd pMOS pipe P2 is connected to anti-phase carry signal output , carry signal output C is connected anti-phase carry signal output with the source electrode of the 3rd nMOS pipe N3

Be connected with the source electrode of the 4th nMOS pipe N4, the described first logical assignment circuit is the 5th nMOS pipe N5 by four nMOS transfer tubes, the 6th nMOS manages N6, the 7th nMOS pipe N7 and the 8th nMOS pipe N8 constitute, the source electrode of the source electrode of the 5th nMOS pipe N5 and the 6th nMOS pipe N6 is connected with the drain electrode of the 3rd nMOS pipe N3, the source electrode of the source electrode of the 7th nMOS pipe N7 and the 8th nMOS pipe N8 is connected with the drain electrode of the 4th nMOS pipe N4, the source electrode of the source electrode of the drain electrode of the 5th nMOS pipe N5 and the 9th nMOS pipe N9 and the tenth nMOS pipe N10 also connects, the source electrode of the source electrode of the drain electrode of the 6th nMOS pipe N6 and the 11 nMOS pipe N11 and the 12 nMOS pipe N12 also connects, the source electrode of the source electrode of the drain electrode of the 7th nMOS pipe N7 and the 13 nMOS pipe N13 and the 14 nMOS pipe N14 also connects, the source electrode of the source electrode of the drain electrode of the 8th nMOS pipe N8 and the 15 nMOS pipe N15 and the 16 nMOS pipe N16 also connects, summing signal produces circuit shown in Fig. 6 (b), by the second single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipes is the 25 nMOS pipe N25, the 26 nMOS manages N26, the 27 nMOS manages N27, the 28 nMOS manages N28, the 29 nMOS manages N29, the 30 nMOS manages N30, the 31 nMOS pipe N31 and the 32 nMOS pipe N32 constitute, the second single phase clock transfer tube heat insulation logic circuit comprises the second logical assignment circuit and second energy recovery circuit, second energy recovery circuit is that the 3rd pMOS pipe P3 and the 4th pMOS pipe P4 constitute by two pMOS pipes, clamper is made of the 17 nMOS pipe N17 and the 18 nMOS pipe N18, be used to avoid output node unsettled, the drain electrode of the 3rd pMOS pipe P3 is connected with the source electrode of the 17 nMOS pipe N17, the drain electrode of the 4th pMOS pipe P2 is connected with the source electrode of the 18 nMOS pipe N18, the drain electrode of the drain electrode of the 17 nMOS pipe N17 and the 18 nMOS pipe N18 is connected to ground, the grid of the 4th pMOS pipe P4, the drain electrode of the grid of the 18 nMOS pipe N18 and the 3rd pMOS pipe P3 is connected to summing signal output S, the grid of the 3rd pMOS pipe P3, the drain electrode of the grid of the 17 nMOS pipe N17 and the 4th pMOS pipe P4 is connected to anti-phase summing signal output

, summing signal output S is connected anti-phase summing signal output with the source electrode of the 19 nMOS pipe N19

Be connected with the source electrode of the 20 nMOS pipe N20, the second logical assignment circuit is the 21 nMOS pipe N21 by four nMOS transfer tubes, the 22 nMOS manages N22, the 23 nMOS pipe N23 and the 24 nMOS pipe N24 constitute, the source electrode of the source electrode of the 21 nMOS pipe N20 and the 22 nMOS pipe N20 is connected with the drain electrode of the 19 nMOS pipe N20, the source electrode of the source electrode of the 23 nMOS pipe N20 and the 24 nMOS pipe N20 is connected with the drain electrode of the 20 nMOS pipe N20, the source electrode of the source electrode of the drain electrode of the 21 nMOS pipe N21 and the 25 nMOS pipe N25 and the 26 nMOS pipe N26 also connects, the source electrode of the source electrode of the drain electrode of the 22 nMOS pipe N22 and the 27 nMOS pipe N27 and the 28 nMOS pipe N28 also connects, the source electrode of the source electrode of the drain electrode of the 23 nMOS pipe N23 and the 29 nMOS pipe N29 and the 30 nMOS pipe N30 also connects, the source electrode of the source electrode of the drain electrode of the 24 nMOS pipe N24 and the 31 nMOS pipe N31 and the 32 nMOS pipe N32 also connects, the source electrode of the one pMOS pipe, the source electrode of the 2nd pMOS pipe, the source electrode of the source electrode of the 3rd pMOS pipe and the 4th pMOS pipe is connected to power clock end CLK, the grid of the 3rd nMOS pipe N3 is connected with auxiliary clock signal end CX with the grid of the 19 nMOS pipe N19, grid and the anti-phase auxiliary clock signal end of the grid of the 4th nMOS pipe N4 and the 20 nMOS pipe N20

Connect, the grid of the 6th nMOS pipe N6, the grid of the 7th nMOS pipe N7, the drain electrode of the 9th nMOS pipe N9, the drain electrode of the 11 nMOS pipe N11, the drain electrode of the 25 nMOS pipe N25, the drain electrode of the 27 nMOS pipe N27, the drain electrode of the drain electrode of the 29 nMOS pipe N29 and the 31 nMOS pipe N31 is connected to the first addend input A, the grid of the 5th nMOS pipe N5, the grid of the 8th nMOS pipe N8, the drain electrode of the 13 nMOS pipe N13, the drain electrode of the 15 nMOS pipe N15, the drain electrode of the 26 nMOS pipe N26, the drain electrode of the 28 nMOS pipe N28, the drain electrode of the drain electrode of the 30 nMOS pipe N30 and the 32 nMOS pipe N32 is connected to the first addend inverting input

The grid of the tenth nMOS pipe N10, the grid of the 11 nMOS pipe N11, the grid of the 13 nMOS pipe N13, the grid of the 16 nMOS pipe N16, the grid of the 26 nMOS pipe N26, the grid of the 27 nMOS pipe N27, the grid of the grid of the 30 nMOS pipe N30 and the 31 nMOS pipe N31 is connected to the second addend input B, the grid of the 9th nMOS pipe N9, the grid of the 12 nMOS pipe N12, the grid of the 14 nMOS pipe N14, the grid of the 15 nMOS pipe N15, the grid of the 25 nMOS pipe N25, the grid of the 28 nMOS pipe N28, the grid of the grid of the 29 nMOS pipe N29 and the 32 nMOS pipe N32 is connected to the second addend inverting input The grid of the grid of the drain electrode of the drain electrode of the tenth nMOS pipe N10, the 12 nMOS pipe N12, the 22 nMOS pipe N22 and the 23 nMOS pipe N23 is connected to the 3rd addend input Ci, and the grid of the drain electrode of the drain electrode of the 14 nMOS pipe N14, the 16 nMOS pipe N16, the grid of the 21 nMOS pipe N21 and the 24 nMOS pipe N24 is connected to the 3rd addend inverting input

Full adder circuit than static CMOS full adder circuit and CAL logic, the structure of single-phase adiabatic full adder circuit of the present invention is very regular, it is the same with the logical construction that summing signal produces circuit substantially that carry signal produces circuit, just the assignment of input port is different, thereby produce different output, design is just very simple like this, only needs one of them structure of design to get final product, and area can reduce greatly.

Embodiment three: the structure of single-phase adiabatic 5-2 compressor reducer of the present invention as shown in figure 10, its basic principle is with 7 numbers (five actual input data I 1, I2, I3, I4, I5, two carry input Cin1, Cin2) addition produces 4 number Sum, Carry, Cout1, Cout2 output, wherein carry Cout1, Cout2 can be to the next stage transmission, but as the input signal Cin1 of an adjacent high position, Cin2, thus realize the 5-2 compression function.It is formed by the first full adder I, the second full adder II and the 3rd full adder III cascade, the first addend input A1 of the first full adder I is connected with first input signal I1, the second addend input B1 of the first full adder I is connected with second input signal I2, the 3rd addend input C of the first full adder I _i1 is connected with the 3rd input signal I3, the carry signal output C1 of the first full adder I exports the first carry output signals Cout1 and gives next stage 5-2 compressor reducer as the first carry input signal, the first addend input A2 of the second full adder II is connected with the first carry input signal Cin1 of the carry signal output of first full adder of upper level 5-2 compressor reducer output, the second addend input B2 of the second full adder II is connected with the summing signal output S1 of the first full adder I, the 3rd addend input C of the second full adder II _i2 are connected with the 4th input signal I4, the carry signal output C2 of the second full adder II exports the second carry output signals Cout2 and gives next stage 5-2 compressor reducer as the second carry input signal, the first addend input A3 of the 3rd full adder III is connected with the second carry input signal Cin2 of the carry signal output of second full adder of upper level 5-2 compressor reducer output, the second addend input B3 of the 3rd full adder III is connected with the summing signal output S2 of the second full adder II, the 3rd addend input C of the 3rd full adder III _i3 are connected with the 5th input signal I5, the carry signal Carry of the carry signal output C3 output 5-2 compressor reducer of the 3rd full adder III, the summing signal Sum of the summing signal output S3 output 5-2 compressor reducer of the 3rd full adder III.

The functional verification formula of 5-2 compressor reducer is as follows:

$\mathrm{Sum}=I1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">I</figure-callout>}2\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png"\; state="\{\{state\}\}">I</figure-callout>}3\&CirclePlus;I4\&CirclePlus;I5\&CirclePlus;\mathrm{Cin}1\&CirclePlus;\mathrm{Cin}2---\left(3\right)$

$\mathrm{Carry}=(I1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">I</figure-callout>}2\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png"\; state="\{\{state\}\}">I</figure-callout>}3\&CirclePlus;I4\&CirclePlus;I5\&CirclePlus;\mathrm{Cin}1)\&CenterDot;\mathrm{<figure-callout\; id="2"\; label="Cin"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">Cin</figure-callout>}2+\stackrel{\&OverBar;}{(I1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">I</figure-callout>}2\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png"\; state="\{\{state\}\}">I</figure-callout>}3\&CirclePlus;I4\&CirclePlus;\mathrm{Cin}1)}\&CenterDot;I5---\left(4\right)$

$\mathrm{Cout}1=(I1\&CirclePlus;I2)\&CenterDot;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png"\; state="\{\{state\}\}">I</figure-callout>}3+\stackrel{\&OverBar;}{(I1+I2)}\&CenterDot;I1---\left(5\right)$

$\mathrm{<figure-callout\; id="2"\; label="Cout"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">Cout</figure-callout>}2=(I1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">I</figure-callout>}2\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png"\; state="\{\{state\}\}">I</figure-callout>}3\&CirclePlus;I4)\&CenterDot;\mathrm{Cin}1+\stackrel{\&OverBar;}{(I1\&CirclePlus;\mathrm{<figure-callout\; id="2"\; label="I"\; filenames="HDA0000026619960000042.png"\; state="\{\{state\}\}">I</figure-callout>}2\&CirclePlus;\mathrm{<figure-callout\; id="3"\; label="I"\; filenames="HDA0000026619960000041.png"\; state="\{\{state\}\}">I</figure-callout>}3\&CirclePlus;I4)}\&CenterDot;I4---\left(6\right)$

Our single-phase adiabatic full adder circuit of having designed of utilization by the 5-2 compressor configuration schematic diagram of Figure 10, just can very simple combination obtains our single-phase adiabatic 5-2 compressor circuit.Figure 11 is a 5-2 compressor reducer functional simulation waveform, and the functional verification formula of utilization 5-2 compressor reducer verifies that to it it is functional as can be known, can realize the 5-2 compressor circuit of single-phase power clock control.

Claims (3)

1. single phase clock transfer tube heat insulation logic circuit, it is characterized in that comprising logical assignment circuit and energy recovery circuit, described energy recovery circuit is that pMOS pipe and the 2nd pMOS pipe constitute by two pMOS pipes, the source electrode of the source electrode of a described pMOS pipe and described the 2nd pMOS pipe is connected to the power clock end, the drain electrode of a described pMOS pipe is connected with the source electrode of a nMOS pipe, the drain electrode of described the 2nd pMOS pipe is connected with the source electrode of the 2nd nMOS pipe, the drain electrode of the drain electrode of a described nMOS pipe and described the 2nd nMOS pipe is connected to ground, the grid of described the 2nd pMOS pipe, the drain electrode of the grid of described the 2nd nMOS pipe and a described pMOS pipe is connected to signal output part, the grid of a described pMOS pipe, the drain electrode of the grid of a described nMOS pipe and described the 2nd pMOS pipe is connected to the inversion signal output, described signal output part is connected with the source electrode of the 3rd nMOS pipe, the grid of described the 3rd nMOS pipe is connected with the auxiliary clock signal end, described inversion signal output is connected with the source electrode of the 4th nMOS pipe, the grid of described the 4th nMOS pipe is connected with anti-phase auxiliary clock signal end, described logical assignment circuit is the 5th a nMOS pipe by four nMOS transfer tubes, the 6th nMOS pipe, the 7th nMOS pipe and the 8th nMOS pipe constitute, the source electrode of the source electrode of described the 5th nMOS pipe and the 6th nMOS pipe is connected with the drain electrode of described the 3rd nMOS pipe, the source electrode of the source electrode of described the 7th nMOS pipe and described the 8th nMOS pipe is connected with the drain electrode of described the 4th nMOS pipe, the drain electrode of described the 5th nMOS pipe is connected with first signal input part, the drain electrode of described the 6th nMOS pipe is connected with the secondary signal input, the drain electrode of described the 7th nMOS pipe is connected with the 3rd signal input part, the drain electrode of described the 8th nMOS pipe is connected with the 4th signal input part, the grid of the grid of described the 5th nMOS pipe and described the 8th nMOS pipe is connected to the 5th signal input part, and the grid of the grid of described the 6th nMOS pipe and described the 7th nMOS pipe is connected to the 6th signal input part.

2. full adder that uses the described single phase clock transfer tube of claim 1 heat insulation logic circuit, it is characterized in that comprising that carry signal produces circuit and summing signal produces circuit, it is the 9th nMOS pipe by the first single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipes that described carry signal produces circuit, the tenth nMOS pipe, the 11 nMOS pipe, the 12 nMOS pipe, the 13 nMOS pipe, the 14 nMOS pipe, the 15 nMOS pipe and the 16 nMOS pipe constitute, the described first single phase clock transfer tube heat insulation logic circuit comprises the first logical assignment circuit and first energy recovery circuit, described first energy recovery circuit is that pMOS pipe and the 2nd pMOS pipe constitute by two pMOS pipes, the drain electrode of a described pMOS pipe is connected with the source electrode of a nMOS pipe, the drain electrode of described the 2nd pMOS pipe is connected with the source electrode of the 2nd nMOS pipe, the drain electrode of the drain electrode of a described nMOS pipe and described the 2nd nMOS pipe is connected to ground, the grid of described the 2nd pMOS pipe, the drain electrode of the grid of described the 2nd nMOS pipe and a described pMOS pipe is connected to the carry signal output, the grid of a described pMOS pipe, the drain electrode of the grid of a described nMOS pipe and described the 2nd pMOS pipe is connected to anti-phase carry signal output, described carry signal output is connected with the source electrode of the 3rd nMOS pipe, described anti-phase carry signal output is connected with the source electrode of the 4th nMOS pipe, the described first logical assignment circuit is the 5th a nMOS pipe by four nMOS transfer tubes, the 6th nMOS pipe, the 7th nMOS pipe and the 8th nMOS pipe constitute, the source electrode of the source electrode of described the 5th nMOS pipe and the 6th nMOS pipe is connected with the drain electrode of described the 3rd nMOS pipe, the source electrode of the source electrode of described the 7th nMOS pipe and described the 8th nMOS pipe is connected with the drain electrode of described the 4th nMOS pipe, the source electrode of the source electrode of the drain electrode of described the 5th nMOS pipe and described the 9th nMOS pipe and described the tenth nMOS pipe also connects, the source electrode of the drain electrode of described the 6th nMOS pipe and the source electrode of described the 11 nMOS pipe and described the 12 nMOS pipe also connects, the source electrode of the drain electrode of described the 7th nMOS pipe and the source electrode of described the 13 nMOS pipe and described the 14 nMOS pipe also connects, the source electrode of the drain electrode of described the 8th nMOS pipe and the source electrode of described the 15 nMOS pipe and described the 16 nMOS pipe also connects, it is the 25 nMOS pipe by the second single phase clock transfer tube heat insulation logic circuit and 8 nMOS pipes that described summing signal produces circuit, the 26 nMOS pipe, the 27 nMOS pipe, the 28 nMOS pipe, the 29 nMOS pipe, the 30 nMOS pipe, the 31 nMOS pipe and the 32 nMOS pipe constitute, the described second single phase clock transfer tube heat insulation logic circuit comprises the second logical assignment circuit and second energy recovery circuit, described second energy recovery circuit is that the 3rd pMOS pipe and the 4th pMOS pipe constitute by two pMOS pipes, the drain electrode of described the 3rd pMOS pipe is connected with the source electrode of the 17 nMOS pipe, the drain electrode of described the 4th pMOS pipe is connected with the source electrode of the 18 nMOS pipe, the drain electrode of described the 17 nMOS pipe and the drain electrode of described the 18 nMOS pipe are connected to ground, the grid of described the 4th pMOS pipe, the drain electrode of the grid of described the 18 nMOS pipe and described the 3rd pMOS pipe is connected to the summing signal output, the grid of described the 3rd pMOS pipe, the drain electrode of the grid of described the 17 nMOS pipe and described the 4th pMOS pipe is connected to anti-phase summing signal output, described summing signal output is connected with the source electrode of the 19 nMOS pipe, described anti-phase summing signal output is connected with the source electrode of the 20 nMOS pipe, the described second logical assignment circuit is the 21 a nMOS pipe by four nMOS transfer tubes, the 22 nMOS pipe, the 23 nMOS pipe and the 24 nMOS pipe constitute, the source electrode of described the 21 nMOS pipe is connected with the drain electrode of described the 19 nMOS pipe with the source electrode of the 22 nMOS pipe, the source electrode of described the 23 nMOS pipe is connected with the drain electrode of described the 20 nMOS pipe with the source electrode of the 24 nMOS pipe, the source electrode of the drain electrode of described the 21 nMOS pipe and the source electrode of described the 25 nMOS pipe and described the 26 nMOS pipe also connects, the source electrode of the drain electrode of described the 22 nMOS pipe and the source electrode of described the 27 nMOS pipe and described the 28 nMOS pipe also connects, the source electrode of the drain electrode of described the 23 nMOS pipe and the source electrode of described the 29 nMOS pipe and described the 30 nMOS pipe also connects, the source electrode of the drain electrode of described the 24 nMOS pipe and the source electrode of described the 31 nMOS pipe and described the 32 nMOS pipe also connects, the source electrode of a described pMOS pipe, the source electrode of described the 2nd pMOS pipe, the source electrode of the source electrode of described the 3rd pMOS pipe and described the 4th pMOS pipe is connected to the power clock end, the grid of described the 3rd nMOS pipe is connected with the auxiliary clock signal end with the grid of described the 19 nMOS pipe, the grid of described the 4th nMOS pipe is connected with anti-phase auxiliary clock signal end with the grid of described the 20 nMOS pipe, the grid of described the 6th nMOS pipe, the grid of described the 7th nMOS pipe, the drain electrode of described the 9th nMOS pipe, the drain electrode of described the 11 nMOS pipe, the drain electrode of described the 25 nMOS pipe, the drain electrode of described the 27 nMOS pipe, the drain electrode of described the 29 nMOS pipe and the drain electrode of described the 31 nMOS pipe are connected to the first addend input, the grid of described the 5th nMOS pipe, the grid of described the 8th nMOS pipe, the drain electrode of described the 13 nMOS pipe, the drain electrode of described the 15 nMOS pipe, the drain electrode of described the 26 nMOS pipe, the drain electrode of described the 28 nMOS pipe, the drain electrode of described the 30 nMOS pipe and the drain electrode of described the 32 nMOS pipe are connected to the first addend inverting input, the grid of described the tenth nMOS pipe, the grid of described the 11 nMOS pipe, the grid of described the 13 nMOS pipe, the grid of described the 16 nMOS pipe, the grid of described the 26 nMOS pipe, the grid of described the 27 nMOS pipe, the grid of described the 30 nMOS pipe and the grid of described the 31 nMOS pipe are connected to the second addend input, the grid of described the 9th nMOS pipe, the grid of described the 12 nMOS pipe, the grid of described the 14 nMOS pipe, the grid of described the 15 nMOS pipe, the grid of described the 25 nMOS pipe, the grid of described the 28 nMOS pipe, the grid of described the 29 nMOS pipe and the grid of described the 32 nMOS pipe are connected to the second addend inverting input, the drain electrode of described the tenth nMOS pipe, the drain electrode of described the 12 nMOS pipe, the grid of described the 22 nMOS pipe and the grid of described the 23 nMOS pipe are connected to the 3rd addend input, the drain electrode of described the 14 nMOS pipe, the drain electrode of described the 16 nMOS pipe, the grid of described the 21 nMOS pipe and the grid of described the 24 nMOS pipe are connected to the 3rd addend inverting input.

3. 5-2 compressor reducer that uses the described full adder of claim 2, it is characterized in that it is by first full adder, second full adder and the 3rd full adder cascade form, the first addend input of described first full adder is connected with first input signal, the second addend input of described first full adder is connected with second input signal, the 3rd addend input of described first full adder is connected with the 3rd input signal, the first addend input of described second full adder is connected with the carry signal output of first full adder of upper level 5-2 compressor reducer, the second addend input of described second full adder is connected with the summing signal output of described first full adder, the 3rd addend input of described second full adder is connected with the 4th input signal, the first addend input of described the 3rd full adder is connected with the carry signal output of second full adder of upper level 5-2 compressor reducer, the second addend input of described the 3rd full adder is connected with the summing signal output of described second full adder, and the 3rd addend input of described the 3rd full adder is connected with the 5th input signal.

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