CN104734691B - A kind of single track input double track output heat insulation logic circuit and one-bit full addres - Google Patents
A kind of single track input double track output heat insulation logic circuit and one-bit full addres Download PDFInfo
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- CN104734691B CN104734691B CN201510028432.8A CN201510028432A CN104734691B CN 104734691 B CN104734691 B CN 104734691B CN 201510028432 A CN201510028432 A CN 201510028432A CN 104734691 B CN104734691 B CN 104734691B
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Abstract
The invention discloses a kind of single track input double track output heat insulation logic circuit and one-bit full addres, it is two-phase without alternating power clock signal that single track input double track, which exports outside kHz clock signal and outside anti-phase kHz clock signal in heat insulation logic circuit, clock and power supply effect are played simultaneously, and two-phase mutually controls single track to input the operation that double track exports heat insulation logic circuit without clock signal is intersected；Realize that single track inputs assignment by assignment module, avoid output hanging by two NMOS tubes, single track input double track output heat insulation logic circuit is used in one-bit full addres；Advantage is that output can reach full swing, and adiabatic energy is lost nothing but, and capacity usage ratio is high, with obvious low power consumption characteristic.
Description
Technical field
The present invention relates to a kind of heat insulation logic circuit, more particularly, to a kind of single track input double track output heat insulation logic circuit
And one-bit full addres.
Background technology
In recent years, with the rise of portable mobile termianl, mobile terminal gives people easily simultaneously, also to make ours in band
Life is more rich and varied, mobile terminal it is convenient with efficiently so that it is very popular.But at the same time, another is asked
Topic is produced therewith, it is known that mobile terminal is battery-powered, but the power-on time of mobile terminal only has one or two mostly now
My god, thus extension product stand-by time just into our very concerns, then low-power consumption problem is become as contemporary society
A research focus.Traditional cmos circuit has developed nearly 30 years on low-power consumption, high-performance, the direction of big density, but
It is constantly reduced due to process, and supply voltage is constantly reduced, and causes the threshold voltage of transistor also constantly to reduce, but threshold value
Voltage causes the leakage current of transistor in exponential increase while reduction, and then causes the leakage power consumption of circuit constantly to increase, therefore
New heat insulation logic circuit turns into the new research direction of modern society.
Full adder is widely used in large-scale IC design as a kind of elementary cell of electronic system.
Such as in the higher microprocessor of performance requirement and SCM system, the size of full adder power consumption is to whole system performance
Influence is especially important.Existing full adder mainly uses traditional CMOS technology, and conventional CMOS circuit is supplied using dc source
Electricity, the energy of circuit is all converted to heat energy and distributed, and produces irreversible formal argument, and power consumption is larger.
Heat insulation logic circuit can reduce circuit power consumption, and extensive concern has been obtained in low consumption circuit research field, profit
The full adder that low-power consumption is designed with heat insulation logic circuit has achieved first-stage success.Traditional heat insulation logic circuit is that double track is defeated
Enter double track output heat insulation logic circuit, such as the circuit such as ECRL, CAL, 2N-2N2P inputs the symmetrical of double track output using double track
Logical assignment mode, the transistor size that double track input double track output heat insulation logic circuit needs is relatively more, to actual domain
Design adds difficulty.Single track input double track output heat insulation logic circuit (abbreviation SRIALDRO) is to double track input double track output
Heat insulation logic circuit be improved after a kind of heat insulation logic circuit.Existing single track input double track output heat insulation logic circuit is such as
Shown in Fig. 1, a part uses cross coupling structure in single track input double track output heat insulation logic circuit, causes it in power
When clock signal CLK voltage is less than the threshold voltage of PMOS, part energy can not be recycled to CLK, but with heat energy
Form is spread out, and single track input double track output heat insulation logic circuit has nonadiabatic energy loss, thus causes it to export
Also full swing is unable to reach, capacity usage ratio is not high.
In view of this, designing a kind of relatively low single track input double track output heat insulation logic circuit of power consumption and one-bit full addres has weight
Want meaning.
The content of the invention
It is adiabatic that one of technical problems to be solved by the invention are to provide a kind of relatively low single track input double track output of power consumption
Logic circuit.Nonadiabatic energy loss is not present in single track input double track output heat insulation logic circuit, and output can reach full pendulum
Width, capacity usage ratio is high, with obvious low power consumption characteristic.
The present invention solve technical scheme that one of above-mentioned technical problem used for：A kind of single track input double track output is adiabatic
Logic circuit, it is characterised in that including the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube, the 3rd NMOS tube
With assignment module；
The draining of the first described PMOS, the substrate of the first described PMOS, the drain electrode of the second described PMOS,
The substrate of the second described PMOS, the drain electrode of the first described NMOS tube and the drain electrode of the second described NMOS tube are connected and it
Connection end exports the kHz clock signal input of heat insulation logic circuit for described single track input double track, for accessing circumferential work
Rate clock signal；The grid of the first described NMOS tube and the grid of the second described NMOS tube connection and its connection end is described
Single track input double track export heat insulation logic circuit anti-phase kHz clock signal input, for accessing during outside anti-phase power
Clock signal；
Described assignment module has at least one input, output end and earth terminal；The input of described assignment module
Hold the signal input part that heat insulation logic circuit is exported for described single track input double track；The grid of the first described PMOS, institute
The drain electrode connection of the source electrode for the second PMOS stated, the source electrode of the second described NMOS tube and the 3rd described NMOS tube and its company
Connect the signal output part that end exports heat insulation logic circuit for described single track input double track；The source electrode of the first described PMOS,
The grid of the second described PMOS, the source electrode of the first described NMOS tube, the grid of the 3rd described NMOS tube and described
The output end of assignment module is connected and its connection end exports the inversion signal of heat insulation logic circuit for described single track input double track
Output end；The substrate of the first described NMOS tube, the substrate of the second described NMOS tube, the source electrode of the 3rd described NMOS tube and
The substrate of the 3rd described NMOS tube is grounded.
Described assignment module has an input, and described assignment module includes the 4th NMOS tube, the described the 4th
The grid of NMOS tube is the input of described assignment module, and the drain electrode of the 4th described NMOS tube is described assignment module
Output end, the source electrode of described the 4th NMOS tube is the earth terminal of described assignment module, the earth terminal of described assignment module
It is grounded with the substrate of the 4th described NMOS tube.
Described assignment module has two inputs, respectively first input end and the second input, described assignment
Module includes the 4th NMOS tube and the 5th NMOS tube, and the grid of described the 4th NMOS tube is first defeated for described assignment module
Enter end, the grid of described the 5th NMOS tube is the second input of described assignment module, the leakage of described the 4th NMOS tube
The output end of extremely described assignment module, the drain electrode of the source electrode of described the 4th NMOS tube and the 5th described NMOS tube connects
Connect, the source electrode of described the 5th NMOS tube is the earth terminal of described assignment module, it is the earth terminal of described assignment module, described
The substrate of the 4th NMOS tube and the substrate of described the 5th NMOS tube be grounded.
Described assignment module has two inputs, respectively first input end and the second input, described assignment
Module includes the 4th NMOS tube and the 5th NMOS tube, and the grid of described the 4th NMOS tube is first defeated for described assignment module
Enter end, the grid of described the 5th NMOS tube is the second input of described assignment module, the leakage of described the 4th NMOS tube
The drain electrode of pole and the 5th described NMOS tube is connected and its connection end is the output end of described assignment module, the described the 4th
The source electrode of NMOS tube and the source electrode of the 5th described NMOS tube are connected and its connection end is the earth terminal of described assignment module, institute
The substrate of the earth terminal for the assignment module stated, the substrate of the 4th described NMOS tube and the 5th described NMOS tube is grounded.
Described assignment module has four inputs, respectively first input end, the first inverting input, the second input
End and the second inverting input；Described assignment module includes the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube and the 7th
NMOS tube, the grid of described the 4th NMOS tube is the first input end of described assignment module, described the 6th NMOS tube
Grid is the first inverting input of described assignment module, and the grid of the 5th described NMOS tube is described assignment module
Second inverting input, the grid of the 7th described NMOS tube is the second input of described assignment module, the described the 4th
The drain electrode of NMOS tube and the drain electrode of the 6th described NMOS tube are connected and its connection end is the output end of described assignment module, institute
The drain electrode connection of the source electrode for the 4th NMOS tube stated and the 5th described NMOS tube, the source electrode of described the 6th NMOS tube and described
The 7th NMOS tube drain electrode connection, the source electrode of described the 5th NMOS tube and the source electrode connection of the 7th described NMOS tube and its
Connection end is the earth terminal of described assignment module, the earth terminal of described assignment module, the substrate of the 4th described NMOS tube,
The substrate of the substrate of the 5th described NMOS tube, the substrate of the 6th described NMOS tube and the 7th described NMOS tube is grounded.
Compared with prior art, when single track of the invention input double track output heat insulation logic circuit advantage is external power
Clock signal and outside anti-phase kHz clock signal be two-phase without alternating power clock signal, while play clock and power supply effect,
Two-phase mutually controls single track to input the operation that double track exports heat insulation logic circuit without clock signal is intersected；Realized by assignment module
Single track inputs assignment, the drain electrode access external power clock signal of the first NMOS tube, the grid access outer counter of the first NMOS tube
Phase kHz clock signal, the source electrode of the first NMOS tube is located at single track and inputs the reversed-phase output that double track exports heat insulation logic circuit,
The outside anti-phase power clock letter of grid access of the drain electrode access external power clock signal, the second NMOS tube of second NMOS tube
Number, the source electrode of the second NMOS tube is located at single track and inputs the output end that double track exports heat insulation logic circuit, thus avoids single track from inputting
The output of double track output heat insulation logic circuit is hanging, its output is reached full swing, adiabatic energy is lost nothing but, energy profit
It is high with rate, with obvious low power consumption characteristic；The phase inverter that the single track input double track output heat insulation logic circuit of the present invention is built
Under SMIC 45nm standard technologies compared with traditional SRIALDRO phase inverters, ECEL phase inverters and static CMOS inverter circuit,
Power dissipation ratio STATIC inverter circuits power consumption averagely have dropped about 63%, averagely have dropped greatly than ECRL inverter circuits power consumption
About 46%, it averagely have dropped about 24% than traditional SRIALDRO inverter circuits power consumption.
The two of the technical problems to be solved by the invention are to provide a kind of relatively low one-bit full addres of power consumption.This adds entirely
Device includes single track input double track output heat insulation logic circuit, and nonadiabatic energy is not present in single track input double track output heat insulation logic circuit
Amount loss, output can reach full swing, and capacity usage ratio is high, and the one-bit full addres have obvious low power consumption characteristic.
The present invention solve above-mentioned technical problem two technical schemes used for：A kind of one-bit full addres, including carry
Signal generating circuit and summing signal generation circuit；Described carry signal generation circuit includes the input double track output of the first single track
Heat insulation logic circuit, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube and the 7th NMOS tube；Described summing signal is produced
Circuit includes the second single track input double track output heat insulation logic circuit, the 12nd NMOS tube, the 13rd NMOS tube, the 14th NMOS
Pipe and the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube and the 18th NMOS tube；
Described the first single track input double track output heat insulation logic circuit includes the first PMOS, the second PMOS, first
NMOS tube, the second NMOS tube, the 3rd NMOS tube and the first assignment module；The draining of the first described PMOS, described first
The substrate of PMOS, the draining of the second described PMOS, the substrate of the second described PMOS, described the first NMOS tube
Drain electrode and the drain electrode of the second described NMOS tube are connected and its connection end is patrolled for described the first single track input double track output thermal insulation
The kHz clock signal input of circuit is collected, for accessing external power clock signal；The grid of the first described NMOS tube and
The grid of the second described NMOS tube is connected and its connection end is described the first single track input double track output heat insulation logic circuit
Anti-phase kHz clock signal input, for accessing outside anti-phase kHz clock signal；The first described assignment module has
Input, output end and earth terminal；The input of the first described assignment module is described the first single track input double track output
The signal input part of heat insulation logic circuit；It is the grid of the first described PMOS, the source electrode of the second described PMOS, described
The drain electrode of the source electrode of second NMOS tube and the 3rd described NMOS tube is connected and its connection end is double for described the first single track input
Rail exports the signal output part of heat insulation logic circuit；The source electrode of the first described PMOS, the grid of the second described PMOS,
The output end connection of the source electrode of the first described NMOS tube, the grid of the 3rd described NMOS tube and the first described assignment module
And its connection end exports the inversion signal output end of heat insulation logic circuit for described the first single track input double track；Described first
The substrate of NMOS tube, the substrate of the second described NMOS tube, the source electrode of the 3rd described NMOS tube and the 3rd described NMOS tube
Substrate be grounded；
Described the second single track input double track output heat insulation logic circuit includes the 3rd PMOS, the 4th PMOS, the 9th
NMOS tube, the tenth NMOS tube, the 11st NMOS tube and the second assignment module；The draining of the 3rd described PMOS, described
The substrate of three PMOSs, the draining of the 4th described PMOS, the substrate of the 4th described PMOS, the 9th described NMOS tube
Drain electrode and described the tenth NMOS tube drain electrode connection and its connection end is adiabatic for described the second single track input double track output
The kHz clock signal input of logic circuit, for accessing external power clock signal；The grid of the 9th described NMOS tube
Grid connection and its connection end with the tenth described NMOS tube are described the second single track input double track output adiabatic logic electricity
The anti-phase kHz clock signal input on road, for accessing outside anti-phase kHz clock signal；Described the second assignment module tool
There are input, output end and earth terminal；The input of the second described assignment module is defeated for described the second single track input double track
Go out the signal input part of heat insulation logic circuit；It is the grid of the 3rd described PMOS, the source electrode of the 4th described PMOS, described
The source electrode of the tenth NMOS tube and the drain electrode connection of described the 11st NMOS tube and its connection end is defeated for the second described single track
Enter the signal output part that double track exports heat insulation logic circuit；The source electrode of the 3rd described PMOS, described the 4th PMOS
Grid, the source electrode of the 9th described NMOS tube, the grid of the 11st described NMOS tube and the second described assignment module it is defeated
Go out end connection and its connection end inputs the inversion signal output end that double track exports heat insulation logic circuit for the second described single track；Institute
The substrate for the 9th NMOS tube stated, the substrate of the tenth described NMOS tube, the source electrode of the 11st described NMOS tube and described
The substrate of 11st NMOS tube is grounded；
The earth terminal of the first described assignment module, the source electrode of the 4th described NMOS tube and the 6th described NMOS tube
Drain electrode connection, the drain electrode connection of the source electrode of described the 5th NMOS tube and the 7th described NMOS tube, the 6th described NMOS tube
Source electrode and the source electrode connection of described the 7th NMOS tube and its connection end be grounded；The drain electrode of the 12nd described NMOS tube and institute
The inversion signal output end connection for the second single track input double track output heat insulation logic circuit stated；The 12nd described NMOS tube
Source electrode, the drain electrode of the 13rd described NMOS tube and the drain electrode of the 16th described NMOS tube connection；The 14th described NMOS
The earth terminal connection of the draining of pipe, the drain electrode of the 15th described NMOS tube and the second described assignment module, the described the tenth
The drain electrode connection of the source electrode of four NMOS tubes, the source electrode of the 13rd described NMOS tube and the 17th described NMOS tube, it is described
The drain electrode connection of the source electrode of 15th NMOS tube, the source electrode of the 16th described NMOS tube and the 18th described NMOS tube, institute
The source grounding of the source electrode for the 17th NMOS tube stated and the 18th described NMOS tube；
The grid of the grid of the 4th described NMOS tube, the grid of the 7th described NMOS tube and the 12nd described NMOS tube
Pole is connected and its connection end is the first addend signal input part of described one-bit full addres；The grid of the 5th described NMOS tube
Pole, the signal input part of described the first single track input double track output heat insulation logic circuit, the grid of the 13rd described NMOS tube
The grid of pole and the 15th described NMOS tube is connected and its connection end is defeated for the second addend signal of described one-bit full addres
Enter end；The signal input part of described second single track input double track output heat insulation logic circuit is the of described one-bit full addres
One anti-phase addend signal input part；The grid of the 14th described NMOS tube and the grid of the 16th described NMOS tube connection and
Its connection end is the second anti-phase addend signal input part of described one-bit full addres；The drain electrode of the 4th described NMOS tube and institute
The drain electrode for the 5th NMOS tube stated exports the inversion signal output end of heat insulation logic circuit with described the first single track input double track
Connection；Signal output part the asking for described one-bit full addres of described the second single track input double track output heat insulation logic circuit
And signal output part；The signal output part of described the first single track input double track output heat insulation logic circuit is complete for described one
Plus the high-order carry signal output end of device；The grid of the 6th described NMOS tube and the connection of the grid of the 17th described NMOS tube
And its connection end is the low order carry signal input part of described one-bit full addres；The grid of the 18th described NMOS tube is institute
The anti-phase low order carry signal input part for the one-bit full addres stated.
The first described assignment module includes the 8th NMOS tube, and the grid of the 8th described NMOS tube is assigned for described first
It is worth the input of module, the drain electrode of the 8th described NMOS tube is the output end of the first described assignment module, the described the 8th
The source electrode of NMOS tube is the earth terminal of the first described assignment module；The second described assignment module includes the 19th NMOS tube,
The grid of the 19th described NMOS tube is the input of the second described assignment module, the drain electrode of described the 19th NMOS tube
For the output end of the second described assignment module, the source electrode of the 19th described NMOS tube is connecing for the second described assignment module
Ground terminal.
The channel length of the first described PMOS, the channel length of the second described PMOS, the 3rd described PMOS
The channel length of the channel length of pipe and the 4th described PMOS be PMOS minimum channel length under standard technology 1~
1.2 again；
The channel length of the first described NMOS tube, the channel length of the second described NMOS tube, the 3rd described NMOS
The channel length of pipe, the channel length of the 4th described NMOS tube, the channel length of the 5th described NMOS tube, the described the 6th
The channel length of NMOS tube, the channel length of the 7th described NMOS tube, the channel length of the 8th described NMOS tube, the 9th
It is the channel length of NMOS tube, the channel length of the tenth described NMOS tube, the channel length of the 11st described NMOS tube, described
The channel length of the 12nd NMOS tube, the channel length of described 13rd NMOS tube, the ditch of the 14th described NMOS tube
Road length, the channel length of the 15th described NMOS tube, the channel length of the 16th described NMOS tube, the described the 17th
The channel length of the channel length of NMOS tube, the channel length of the 18th described NMOS tube and the 19th described NMOS tube is equal
For 1~1.2 times of NMOS tube minimum channel length under standard technology.
Compared with prior art, the advantage of one-bit full addres of the invention is to be provided with carry signal generation circuit
It is exhausted that the input double track output of the second single track is provided with one single track input double track output heat insulation logic circuit, summing signal generation circuit
Hot logic circuit, the first single track input double track output heat insulation logic circuit and the second single track input double track output heat insulation logic circuit
Middle outside kHz clock signal and outside anti-phase kHz clock signal be two-phase without alternating power clock signal, while playing clock
With power supply effect, two-phase mutually controls the first single track to input double track output heat insulation logic circuit and the second list without clock signal is intersected
Rail input double track exports the operation of heat insulation logic circuit；First NMOS tube in first single track input double track output heat insulation logic circuit
Drain electrode access external power clock signal, the outside anti-phase kHz clock signal of grid access of the first NMOS tube, the first NMOS
The source electrode of pipe is located at single track and inputs the reversed-phase output that double track exports heat insulation logic circuit, and the drain electrode access of the second NMOS tube is outside
The outside anti-phase kHz clock signal of grid access of kHz clock signal, the second NMOS tube, the source electrode of the second NMOS tube is located at the
One single track input double track exports the output end of heat insulation logic circuit, thus avoids the first single track from inputting double track output adiabatic logic electricity
The output on road is hanging, its output is reached full swing, and adiabatic energy is lost nothing but, and capacity usage ratio is high, and the second single track is defeated
Enter drain electrode access external power clock signal, the grid of the 9th NMOS tube of the 9th NMOS tube in double track output heat insulation logic circuit
The outside anti-phase kHz clock signal of access, the source electrode of the 9th NMOS tube is located at the second single track input double track output heat insulation logic circuit
Reversed-phase output, the drain electrode access external power clock signal of the tenth NMOS tube, the grid access outer counter of the tenth NMOS tube
Phase kHz clock signal, the source electrode of the tenth NMOS tube is located at the second single track and inputs the output end that double track exports heat insulation logic circuit,
Thus avoid the output that the second single track inputs double track output heat insulation logic circuit vacantly, its output is reached full swing, nothing
Nonadiabatic energy loss, capacity usage ratio is high, and one-bit full addres of the invention have obvious low power consumption characteristic, in SMIC45nm
With the one-bit full addres based on traditional SRIALDRO, ECEL one-bit full addres and static state CMOS one-bit full addres electricity under standard technology
Road is compared, and power dissipation ratio static state CMOS one-bit full addres circuit power consumption averagely have dropped about 65%, than ECRL one-bit full addres electricity
Road power consumption averagely have dropped about 40%, and about 18% is averagely have dropped than traditional SRIALDRO one-bit full addres circuit power consumption.
Brief description of the drawings
Fig. 1 exports the circuit diagram of heat insulation logic circuit for traditional single track input double track；
Fig. 2 exports the circuit diagram of the embodiment one of heat insulation logic circuit for the single track input double track of the present invention；
Fig. 3 exports the analogous diagram of the embodiment one of heat insulation logic circuit for the single track input double track of the present invention；
Fig. 4 is the power consumption comparison diagram of circuit shown in Fig. 2 and existing three kinds of phase inverters；
Fig. 5 exports the circuit diagram of the embodiment two of heat insulation logic circuit for the single track input double track of the present invention；
Fig. 6 exports the circuit diagram of the embodiment three of heat insulation logic circuit for the single track input double track of the present invention；
Fig. 7 exports the circuit diagram of the example IV of heat insulation logic circuit for the single track input double track of the present invention；
Fig. 8 (a) is the circuit diagram of the carry signal generation circuit of the one-bit full addres of the present invention；
Fig. 8 (b) is the circuit diagram of the summing signal generation circuit of the one-bit full addres of the present invention；
Fig. 8 (c) is the graphical diagram of the one-bit full addres of the present invention；
Fig. 9 is the analogous diagram of the one-bit full addres of the present invention；
Figure 10 (a) is the carry signal generation circuit of the one-bit full addres based on traditional SRIALDRO；
Figure 10 (b) is the summing signal generation circuit of the one-bit full addres based on traditional SRIALDRO；
Figure 11 (a) is the carry signal generation circuit based on ECRL adiabatic logic full adders；
Figure 11 (b) is the summing signal generation circuit based on ECRL adiabatic logic full adders；
Figure 12 is the one-bit full addres electrical block diagram based on static complementary CMOS structure；
Figure 13 is the one-bit full addres of the present invention and the power consumption comparison diagram of existing three kinds of one-bit full addres.
Embodiment
Further detailed is made to the single track input double track output heat insulation logic circuit of the present invention below in conjunction with accompanying drawing embodiment
Description.
Embodiment one：As shown in Fig. 2 a kind of single track input double track output heat insulation logic circuit, including the first PMOS P1,
Second PMOS P2, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3 and assignment module；First PMOS P1's
Drain electrode, the first PMOS P1 substrate, the second PMOS P2 drain electrode, the second PMOS P2 substrate, the first NMOS tube N1
When drain electrode connection and its connection end of the drain electrode with the second NMOS tube N2 are that single track inputs the power of double track output heat insulation logic circuit
Clock signal input part, for accessing external power clock signal clk；The grid of first NMOS tube N1 grid and the second NMOS tube N2
Pole is connected and its connection end is that single track inputs the anti-phase kHz clock signal input that double track exports heat insulation logic circuit, for connecing
Enter outside anti-phase kHz clock signal CLKb；KHz clock signal CLK's and anti-phase kHz clock signal CLKb differs only in
Both phase difference 180 degrees；Assignment module has at least one input, output end and earth terminal；The input of assignment module
Hold and input the signal input part that double track exports heat insulation logic circuit for single track；First PMOS P1 grid, the second PMOS P2
Source electrode, the second NMOS tube N2 source electrode and the 3rd NMOS tube N3 drain electrode connection and its connection end be single track input double track output
The signal output part of heat insulation logic circuit；First PMOS P1 source electrode, the second PMOS P2 grid, the first NMOS tube N1
The output end of source electrode, the 3rd NMOS tube N3 grid and assignment module is connected and its connection end is that single track input double track output is adiabatic
The inversion signal output end of logic circuit；First NMOS tube N1 substrate, the second NMOS tube N2 substrate, the 3rd NMOS tube N3
Source electrode and the 3rd NMOS tube N3 substrate are grounded.
In the present embodiment, assignment module has an input, and assignment module includes the 4th NMOS tube N4, the 4th NMOS tube
N4 grid is the input of assignment module, and the 4th NMOS tube N4 drain electrode is the output end of assignment module, the 4th NMOS tube N4
Source electrode be assignment module earth terminal, the earth terminal of assignment module and the 4th NMOS tube N4 substrate is grounded.
The single track input double track output heat insulation logic circuit of the present embodiment is phase inverter or buffer, and its analogous diagram is as schemed
Shown in 3, analysis chart 3 understands that the phase inverter or buffer have correct logic.
Using Hspice emulation tools, under SMIC 45nm standard technologies, phase inverter respectively to the present embodiment, tradition
The power consumption of SRIALDRO phase inverters, ECEL phase inverters and static CMOS inverter circuit produced by within a clock cycle is carried out
Emulation, power consumption comparison diagram of the above-mentioned four kinds of phase inverters within a work period under different frequency is as shown in Figure 4.Analysis chart 4 can
Know, the phase inverter of the present embodiment under SMIC 45nm standard technologies with traditional SRIALDRO phase inverters, ECEL phase inverters and static state
CMOS inverter circuit is compared, and power dissipation ratio STATIC inverter circuits power consumption averagely have dropped about 63%, than ECRL phase inverter
Circuit power consumption averagely have dropped about 46%, and about 24% is averagely have dropped than traditional SRIALDRO inverter circuits power consumption.By
Above-mentioned comparison data are visible, on the premise of circuit performance is not influenceed, and the single track input double track output thermal insulation of embodiment one is patrolled
Collecting the inverter circuit of circuit composition has obvious low-power consumption feature.
Embodiment two：As shown in figure 5, a kind of single track input double track output heat insulation logic circuit, including the first PMOS P1,
Second PMOS P2, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3 and assignment module；First PMOS P1's
Drain electrode, the first PMOS P1 substrate, the second PMOS P2 drain electrode, the second PMOS P2 substrate, the first NMOS tube N1
When drain electrode connection and its connection end of the drain electrode with the second NMOS tube N2 are that single track inputs the power of double track output heat insulation logic circuit
Clock signal input part, for accessing external power clock signal clk；The grid of first NMOS tube N1 grid and the second NMOS tube N2
Pole is connected and its connection end is that single track inputs the anti-phase kHz clock signal input that double track exports heat insulation logic circuit, for connecing
Enter outside anti-phase kHz clock signal CLKb；KHz clock signal CLK's and anti-phase kHz clock signal CLKb differs only in
Both phase difference 180 degrees；Assignment module has at least one input, output end and earth terminal；The input of assignment module
Hold and input the signal input part that double track exports heat insulation logic circuit for single track；First PMOS P1 grid, the second PMOS P2
Source electrode, the second NMOS tube N2 source electrode and the 3rd NMOS tube N3 drain electrode connection and its connection end be single track input double track output
The signal output part of heat insulation logic circuit；First PMOS P1 source electrode, the second PMOS P2 grid, the first NMOS tube N1
The output end of source electrode, the 3rd NMOS tube N3 grid and assignment module is connected and its connection end is that single track input double track output is adiabatic
The inversion signal output end of logic circuit；First NMOS tube N1 substrate, the second NMOS tube N2 substrate, the 3rd NMOS tube N3
Source electrode and the 3rd NMOS tube N3 substrate are grounded.
In the present embodiment, assignment module has two inputs, respectively first input end and the second input, assignment mould
Block includes the 4th NMOS tube N4 and the 5th NMOS tube N5, and the 4th NMOS tube N4 grid is the first input end of assignment module, the
Five NMOS tube N5 grid is the second input of assignment module, and the 4th NMOS tube N4 drain electrode is the output end of assignment module,
The drain electrode connection of 4th NMOS tube N4 source electrode and the 5th NMOS tube N5, the 5th NMOS tube N5 source electrode is the ground connection of assignment module
End, the substrate of the earth terminal of assignment module, the 4th NMOS tube N4 substrate and the 5th NMOS tube N5 is grounded.
In the present embodiment, single track input double track output heat insulation logic circuit is 2 inputs and/and not circuit.
Embodiment three：As shown in fig. 6, a kind of single track input double track output heat insulation logic circuit, including the first PMOS P1,
Second PMOS P2, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3 and assignment module；First PMOS P1's
Drain electrode, the first PMOS P1 substrate, the second PMOS P2 drain electrode, the second PMOS P2 substrate, the first NMOS tube N1
When drain electrode connection and its connection end of the drain electrode with the second NMOS tube N2 are that single track inputs the power of double track output heat insulation logic circuit
Clock signal input part, for accessing external power clock signal clk；The grid of first NMOS tube N1 grid and the second NMOS tube N2
Pole is connected and its connection end is that single track inputs the anti-phase kHz clock signal input that double track exports heat insulation logic circuit, for connecing
Enter outside anti-phase kHz clock signal CLKb；KHz clock signal CLK's and anti-phase kHz clock signal CLKb differs only in
Both phase difference 180 degrees；Assignment module has at least one input, output end and earth terminal；The input of assignment module
Hold and input the signal input part that double track exports heat insulation logic circuit for single track；First PMOS P1 grid, the second PMOS P2
Source electrode, the second NMOS tube N2 source electrode and the 3rd NMOS tube N3 drain electrode connection and its connection end be single track input double track output
The signal output part of heat insulation logic circuit；First PMOS P1 source electrode, the second PMOS P2 grid, the first NMOS tube N1
The output end of source electrode, the 3rd NMOS tube N3 grid and assignment module is connected and its connection end is that single track input double track output is adiabatic
The inversion signal output end of logic circuit；First NMOS tube N1 substrate, the second NMOS tube N2 substrate, the 3rd NMOS tube N3
Source electrode and the 3rd NMOS tube N3 substrate are grounded.
In the present embodiment, assignment module has two inputs, respectively first input end and the second input, assignment mould
Block includes the 4th NMOS tube N4 and the 5th NMOS tube N5, and the 4th NMOS tube N4 grid is the first input end of assignment module, the
Five NMOS tube N5 grid is the second input of assignment module, the 4th NMOS tube N4 drain electrode and the 5th NMOS tube N5 drain electrode
Connection and its connection end are the output end of assignment module, the 4th NMOS tube N4 source electrode and the 5th NMOS tube N5 source electrode connection and
Its connection end is the earth terminal of assignment module, the earth terminal of assignment module, the 4th NMOS tube N4 substrate and the 5th NMOS tube N5
Substrate be grounded.
In the present embodiment, single track input double track output heat insulation logic circuit is 2 inputs or/OR-NOT circuit.
Example IV：As shown in fig. 7, a kind of single track input double track output heat insulation logic circuit, including the first PMOS P1,
Second PMOS P2, the first NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3 and assignment module；First PMOS P1's
Drain electrode, the first PMOS P1 substrate, the second PMOS P2 drain electrode, the second PMOS P2 substrate, the first NMOS tube N1
When drain electrode connection and its connection end of the drain electrode with the second NMOS tube N2 are that single track inputs the power of double track output heat insulation logic circuit
Clock signal input part, for accessing external power clock signal clk；The grid of first NMOS tube N1 grid and the second NMOS tube N2
Pole is connected and its connection end is that single track inputs the anti-phase kHz clock signal input that double track exports heat insulation logic circuit, for connecing
Enter outside anti-phase kHz clock signal CLKb；KHz clock signal CLK's and anti-phase kHz clock signal CLKb differs only in
Both phase difference 180 degrees；Assignment module has at least one input, output end and earth terminal；The input of assignment module
Hold and input the signal input part that double track exports heat insulation logic circuit for single track；First PMOS P1 grid, the second PMOS P2
Source electrode, the second NMOS tube N2 source electrode and the 3rd NMOS tube N3 drain electrode connection and its connection end be single track input double track output
The signal output part of heat insulation logic circuit；First PMOS P1 source electrode, the second PMOS P2 grid, the first NMOS tube N1
The output end of source electrode, the 3rd NMOS tube N3 grid and assignment module is connected and its connection end is that single track input double track output is adiabatic
The inversion signal output end of logic circuit；First NMOS tube N1 substrate, the second NMOS tube N2 substrate, the 3rd NMOS tube N3
Source electrode and the 3rd NMOS tube N3 substrate are grounded.
In the present embodiment, assignment module has four inputs, respectively first input end, the first inverting input, the
Two inputs and the second inverting input；Assignment module include the 4th NMOS tube N4, the 5th NMOS tube N5, the 6th NMOS tube N6
With the 7th NMOS tube N7, the 4th NMOS tube N4 grid is the first input end of assignment module, and the 6th NMOS tube N6 grid is
First inverting input of assignment module, the 5th NMOS tube N5 grid is the second inverting input of assignment module, the 7th
NMOS tube N7 grid is the second input of assignment module, and the 4th NMOS tube N4 drain electrode and the 6th NMOS tube N6 drain electrode connect
Connect and its connection end be assignment module output end, the 4th NMOS tube N4 source electrode and the 5th NMOS tube N5 drain electrode connection, the
The drain electrode connection of six NMOS tube N6 source electrode and the 7th NMOS tube N7, the 5th NMOS tube N5 source electrode and the 7th NMOS tube N7 source
Pole is connected and its connection end is the earth terminal of assignment module, the earth terminal of assignment module, the 4th NMOS tube N4 substrate, the 5th
The substrate of NMOS tube N5 substrate, the 6th NMOS tube N6 substrate and the 7th NMOS tube N7 is grounded.
In the present embodiment, single track input double track output heat insulation logic circuit is 2 input XOR/same to OR circuits.
The single track input double track output heat insulation logic circuit of the present invention, changes assignment circuit therein and (changes input port
Amplitude), different gate circuits can be obtained.
Above-mentioned single track is used to input the one-bit full addres that double track exports heat insulation logic circuit present invention also offers a kind of, with
Lower combination accompanying drawing embodiment is described in further detail to the one-bit full addres of the present invention.
Embodiment：One-bit full addres, including carry signal generation circuit and summing signal generation circuit；As shown in Fig. 8 (a)
Carry signal generation circuit includes the first single track input double track output heat insulation logic circuit, the 4th NMOS tube N4, the 5th NMOS tube
N5, the 6th NMOS tube N6 and the 7th NMOS tube N7；As shown in Fig. 8 (b), it is double that summing signal generation circuit includes the input of the second single track
Rail output heat insulation logic circuit, the 12nd NMOS tube N12, the 13rd NMOS tube N13, the 14th NMOS tube N14 and the 15th
NMOS tube N15, the 16th NMOS tube N16, the 17th NMOS tube N17 and the 18th NMOS tube N18；The graphical diagram of one-bit full addres
As shown in Fig. 8 (c).
First single track input double track output heat insulation logic circuit includes the first PMOS P1, the second PMOS P2, first
NMOS tube N1, the second NMOS tube N2, the 3rd NMOS tube N3 and the first assignment module；First PMOS P1 drain electrode, the first PMOS
Pipe P1 substrate, the second PMOS P2 drain electrode, the second PMOS P2 substrate, the first NMOS tube N1 drain electrode and the 2nd NMOS
Pipe N2 drain electrode is connected and its connection end is that the first single track inputs the kHz clock signal input that double track exports heat insulation logic circuit
End, for accessing external power clock signal clk；First NMOS tube N1 grid and the second NMOS tube N2 grid are connected and it
Connection end is that the first single track inputs the anti-phase kHz clock signal input that double track exports heat insulation logic circuit, for accessing outside
Anti-phase kHz clock signal CLKb；First assignment module has input, output end and earth terminal；The input of first assignment module
Hold and input the signal input part that double track exports heat insulation logic circuit for the first single track；First PMOS P1 grid, the 2nd PMOS
The drain electrode of pipe P2 source electrode, the second NMOS tube N2 source electrode and the 3rd NMOS tube N3 is connected and its connection end is that the first single track is inputted
Double track exports the signal output part of heat insulation logic circuit；First PMOS P1 source electrode, the second PMOS P2 grid, first
The output end of NMOS tube N1 source electrode, the 3rd NMOS tube N3 grid and the first assignment module is connected and its connection end is first single
Rail input double track exports the inversion signal output end of heat insulation logic circuit；First NMOS tube N1 substrate, the second NMOS tube N2
The substrate of substrate, the 3rd NMOS tube N3 source electrode and the 3rd NMOS tube N3 is grounded；
Second single track input double track output heat insulation logic circuit includes the 3rd PMOS P3, the 4th PMOS P4, the 9th
NMOS tube N9, the tenth NMOS tube N10, the 11st NMOS tube N11 and the second assignment module；3rd PMOS P3 drain electrode, the 3rd
PMOS P3 substrate, the 4th PMOS P4 drain electrode, the 4th PMOS P4 substrate, the 9th NMOS tube N9 drain electrode and the tenth
NMOS tube N10 drain electrode is connected and its connection end is that the second single track inputs the kHz clock signal that double track exports heat insulation logic circuit
Input, for accessing external power clock signal clk；KHz clock signal CLK and anti-phase kHz clock signal CLKb area
Both phase difference 180 degrees are not only that；The grid connection of 9th NMOS tube N9 grid and the tenth NMOS tube N10 and its company
Connect end and input the anti-phase kHz clock signal input that double track exports heat insulation logic circuit for the second single track, for accessing outer counter
Phase kHz clock signal CLKb；Second assignment module has input, output end and earth terminal；The input of second assignment module
The signal input part that double track exports heat insulation logic circuit is inputted for the second single track；3rd PMOS P3 grid, the 4th PMOS
The drain electrode of P4 source electrode, the tenth NMOS tube N10 source electrode and the 11st NMOS tube N11 is connected and its connection end is that the second single track is defeated
Enter the signal output part that double track exports heat insulation logic circuit；3rd PMOS P3 source electrode, the 4th PMOS P4 grid, the 9th
The output end connection of NMOS tube N9 source electrode, the 11st NMOS tube N11 grid and the second assignment module and its connection end is the
Two single tracks input double track exports the inversion signal output end of heat insulation logic circuit；9th NMOS tube N9 substrate, the tenth NMOS tube
The substrate of N10 substrate, the 11st NMOS tube N11 source electrode and the 11st NMOS tube N11 is grounded；
The earth terminal of first assignment module, the drain electrode of the 4th NMOS tube N4 source electrode and the 6th NMOS tube N6 are connected, and the 5th
NMOS tube N5 source electrode and the 7th NMOS tube N7 drain electrode connection, the 6th NMOS tube N6 source electrode and the 7th NMOS tube N7 source electrode
Connection and its connection end ground connection；12nd NMOS tube N12 drain electrode and the second single track input double track output heat insulation logic circuit
Inversion signal output end is connected；12nd NMOS tube N12 source electrode, the 13rd NMOS tube N13 drain electrode and the 16th NMOS tube
N16 drain electrode connection；The ground connection of 14th NMOS tube N14 drain electrode, the 15th NMOS tube N15 drain electrode and the second assignment module
End connection, the 14th NMOS tube N14 source electrode, the drain electrode of the 13rd NMOS tube N13 source electrode and the 17th NMOS tube N17 connect
Connect, the 15th NMOS tube N15 source electrode, the drain electrode of the 16th NMOS tube N16 source electrode and the 18th NMOS tube N18 are connected, the
17 NMOS tube N17 source electrode and the 18th NMOS tube N18 source grounding；
The grid connection of 4th NMOS tube N4 grid, the 7th NMOS tube N7 grid and the 12nd NMOS tube N12 and its
Connection end is the first addend signal input part of one-bit full addres, accesses the first addend signal X；5th NMOS tube N5 grid,
First single track input double track exports signal input part, the 13rd NMOS tube N13 grid and the 15th of heat insulation logic circuit
NMOS tube N15 grid is connected and its connection end is the second addend signal input part of one-bit full addres, access the second addend letter
Number Y；The signal input part of second single track input double track output heat insulation logic circuit is believed for the first anti-phase addend of one-bit full addres
Number input, accesses the first anti-phase addend signal Xb, and Xb is X inversion signal；14th NMOS tube N14 grid and the 16th
NMOS tube N16 grid is connected and its connection end is the second anti-phase addend signal input part of one-bit full addres, and access second is anti-
Addition number signal Yb, Yb are Y inversion signal；4th NMOS tube N4 drain electrode and the 5th NMOS tube N5 drain electrode and the first single track
Input the inversion signal output end connection of double track output heat insulation logic circuit；Second single track input double track output heat insulation logic circuit
Signal output part be one-bit full addres summing signal output end, output summing signal S；The input double track output of first single track is exhausted
The signal output part of hot logic circuit is the high-order carry signal output end of one-bit full addres, for exporting high-order carry to a high position
Signal C0；6th NMOS tube N6 grid and the 17th NMOS tube N17 grid are connected and its connection end is one-bit full addres
Low order carry signal input part, the low order carry signal Ci for inputting low level；18th NMOS tube N18 grid is one complete
Plus the anti-phase low order carry signal input part of device, the anti-phase low order carry signal Cib for inputting low level, Cib is anti-phase for Ci's
Signal.
In the present embodiment, the first assignment module includes the 8th NMOS tube N8, and the 8th NMOS tube N8 grid is the first assignment
The input of module, the 8th NMOS tube N8 drain electrode is the output end of the first assignment module, and the 8th NMOS tube N8 source electrode is the
The earth terminal of one assignment module；Second assignment module includes the 19th NMOS tube N19, and the 19th NMOS tube N19 grid is the
The input of two assignment modules, the 19th NMOS tube N19 drain electrode is the output end of the second assignment module, the 19th NMOS tube
N19 source electrode is the earth terminal of the second assignment module.
In the present embodiment, the first PMOS P1 channel length, the second PMOS P2 channel length, the 3rd PMOS P3
Channel length and the 4th PMOS P4 channel length be 1~1.2 times of minimum channel length under PMOS standard technology；
First NMOS tube N1 channel length, the second NMOS tube N2 channel length, the 3rd NMOS tube N3 channel length, the 4th NMOS
Pipe N4 channel length, the 5th NMOS tube N5 channel length, the 6th NMOS tube N6 channel length, the 7th NMOS tube N7 ditch
Road length, the 8th NMOS tube N8 channel length, the 9th NMOS tube N9 channel length, the tenth NMOS tube N10 channel length,
11st NMOS tube N11 channel length, the 12nd NMOS tube N12 channel length, the 13rd NMOS tube N13 raceway groove it is long
Degree, the 14th NMOS tube N14 channel length, the 15th NMOS tube N15 channel length, the 16th NMOS tube N16 raceway groove
Length, the 17th NMOS tube N17 channel length, the 18th NMOS tube N18 channel length and the 19th NMOS tube N19 ditch
Road length is 1~1.2 times of minimum channel length under NMOS tube standard technology.
Using Hspice emulation tools, under SMIC 45nm standard technologies, one-bit full addres respectively to the present embodiment,
One-bit full addres based on traditional SRIALDRO such as Figure 10 (a) and shown in Figure 10 (b), as shown in Figure 11 (a) and Figure 11 (b)
ECEL one-bit full addres and static CMOS one-bit full addres structural circuit as shown in figure 12 are produced by within a clock cycle
Power consumption emulated, the power consumption comparison diagram such as Figure 13 of above-mentioned four kinds of one-bit full addres within a work period under different frequency
It is shown.Analysis chart 13 understands that one-bit full addres of the invention are under SMIC 45nm standard technologies and based on traditional SRIALDRO's
One-bit full addres, ECEL one-bit full addres and static state CMOS one-bit full addres circuits are compared, and power dissipation ratio static state CMOS mono- is complete to be added
Device circuit power consumption averagely have dropped about 65%, and about 40% is averagely have dropped than ECRL one-bit full addres circuit power consumption, than passing
System SRIALDRO one-bit full addres circuit power consumption averagely have dropped about 18%.
From above-mentioned comparison data, on the premise of circuit performance is not influenceed, one-bit full addres of the invention are (referred to as
ISRIALDRO) relative to the one-bit full addres based on traditional SRIALDRO, ECEL one-bit full addres and static state CMOS (STATIC)
One-bit full addres circuit, with obvious low power consumption characteristic.
Claims (4)
1. a kind of single track input double track output heat insulation logic circuit, it is characterised in that including the first PMOS, the second PMOS, the
One NMOS tube, the second NMOS tube, the 3rd NMOS tube and assignment module；
It is the draining of the first described PMOS, the substrate of the first described PMOS, the draining of the second described PMOS, described
The second PMOS substrate, the drain electrode of described first NMOS tube and the drain electrode of the second described NMOS tube connection and its connect
The kHz clock signal input that heat insulation logic circuit is exported for described single track input double track is held, for accessing during external power
Clock signal；The grid of the first described NMOS tube and the grid of the second described NMOS tube are connected and its connection end is described list
Rail input double track exports the anti-phase kHz clock signal input of heat insulation logic circuit, for accessing outside anti-phase power clock letter
Number；
Described assignment module has two input, output ends and earth terminal, and the input described in two is respectively first defeated
Enter end and the second input, two inputs of described assignment module are described single track input double track output adiabatic logic electricity
Two signal input parts on road；The grid of the first described PMOS, the source electrode of the second described PMOS, described second
The drain electrode of the source electrode of NMOS tube and the 3rd described NMOS tube is connected and its connection end is exhausted for described single track input double track output
The signal output part of hot logic circuit；The source electrode of the first described PMOS, the grid of the second described PMOS, described
The output end of the source electrode of one NMOS tube, the grid of the 3rd described NMOS tube and described assignment module is connected and its connection end is
Described single track input double track exports the inversion signal output end of heat insulation logic circuit；The substrate of the first described NMOS tube, institute
The substrate of the substrate for the second NMOS tube stated, the source electrode of the 3rd described NMOS tube and the 3rd described NMOS tube is grounded；
Described assignment module includes the 4th NMOS tube and the 5th NMOS tube, and the grid of the 4th described NMOS tube is described tax
It is worth the first input end of module, the grid of the 5th described NMOS tube is the second input of described assignment module, described
The drain electrode of 4th NMOS tube is the output end of described assignment module, the source electrode and the described the 5th of described the 4th NMOS tube
The drain electrode connection of NMOS tube, the source electrode of the 5th described NMOS tube is the earth terminal of described assignment module, described assignment mould
The substrate of the earth terminal of block, the substrate of the 4th described NMOS tube and the 5th described NMOS tube is grounded.
2. the single track input double track described in a kind of usage right requirement 1 exports the one-bit full addres of heat insulation logic circuit, its feature
It is to include carry signal generation circuit and summing signal generation circuit；Described carry signal generation circuit includes the first single track
Input double track output heat insulation logic circuit, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube and the 7th NMOS tube；Described
Summing signal generation circuit includes the second single track input double track output heat insulation logic circuit, the 12nd NMOS tube, the 13rd NMOS
Pipe, the 14th NMOS tube and the 15th NMOS tube, the 16th NMOS tube, the 17th NMOS tube and the 18th NMOS tube；
Described the first single track input double track output heat insulation logic circuit includes the first PMOS, the second PMOS, the first NMOS
Pipe, the second NMOS tube, the 3rd NMOS tube and the first assignment module；The draining of the first described PMOS, the first described PMOS
The substrate of pipe, the draining of the second described PMOS, the substrate of the second described PMOS, the drain electrode of the first described NMOS tube
Drain electrode connection and its connection end with the second described NMOS tube are described the first single track input double track output adiabatic logic electricity
The kHz clock signal input on road, for accessing external power clock signal；The grid of the first described NMOS tube and described
The second NMOS tube grid connection and its connection end is the anti-of described first single track input double track output heat insulation logic circuit
Phase kHz clock signal input, for accessing outside anti-phase kHz clock signal；The first described assignment module has input
End, output and ground；The input of the first described assignment module is adiabatic for described the first single track input double track output
The signal input part of logic circuit；The grid of the first described PMOS, the source electrode of the second described PMOS, described second
The drain electrode of the source electrode of NMOS tube and the 3rd described NMOS tube is connected and its connection end is defeated for described the first single track input double track
Go out the signal output part of heat insulation logic circuit；It is the source electrode of the first described PMOS, the grid of the second described PMOS, described
The first NMOS tube source electrode, the grid of described 3rd NMOS tube and the output end connection of the first described assignment module and its
Connection end exports the inversion signal output end of heat insulation logic circuit for described the first single track input double track；The first described NMOS
The substrate of pipe, the substrate of the second described NMOS tube, the lining of the source electrode of the 3rd described NMOS tube and the 3rd described NMOS tube
Bottom is grounded；
Described the second single track input double track output heat insulation logic circuit includes the 3rd PMOS, the 4th PMOS, the 9th NMOS
Pipe, the tenth NMOS tube, the 11st NMOS tube and the second assignment module；The draining of the 3rd described PMOS, the described the 3rd
The substrate of PMOS, the draining of the 4th described PMOS, the substrate of the 4th described PMOS, described the 9th NMOS tube
Drain electrode and the drain electrode of the tenth described NMOS tube are connected and its connection end is patrolled for described the second single track input double track output thermal insulation
The kHz clock signal input of circuit is collected, for accessing external power clock signal；The grid of the 9th described NMOS tube and
The grid of the tenth described NMOS tube is connected and its connection end is described the second single track input double track output heat insulation logic circuit
Anti-phase kHz clock signal input, for accessing outside anti-phase kHz clock signal；The second described assignment module has
Input, output end and earth terminal；The input of the second described assignment module is described the second single track input double track output
The signal input part of heat insulation logic circuit；It is the grid of the 3rd described PMOS, the source electrode of the 4th described PMOS, described
The drain electrode of the source electrode of tenth NMOS tube and the 11st described NMOS tube is connected and its connection end inputs for the second described single track
Double track exports the signal output part of heat insulation logic circuit；The grid of the source electrode of the 3rd described PMOS, the 4th described PMOS
Pole, the source electrode of the 9th described NMOS tube, the output of the grid of the 11st described NMOS tube and the second described assignment module
End is connected and its connection end exports the inversion signal output end of heat insulation logic circuit for described the second single track input double track；It is described
The 9th NMOS tube substrate, the substrate of described tenth NMOS tube, the source electrode and described of the 11st described NMOS tube
The substrate of 11 NMOS tubes is grounded；
The drain electrode of the earth terminal of the first described assignment module, the source electrode of the 4th described NMOS tube and the 6th described NMOS tube
Connection, the drain electrode connection of the source electrode of described the 5th NMOS tube and the 7th described NMOS tube, the source of described the 6th NMOS tube
The source electrode connection of pole and the 7th described NMOS tube and its connection end ground connection；The 12nd described NMOS tube drain electrode and it is described
The inversion signal output end connection of second single track input double track output heat insulation logic circuit；The source of the 12nd described NMOS tube
Pole, the drain electrode of the 13rd described NMOS tube and the drain electrode of the 16th described NMOS tube connection；The 14th described NMOS tube
Drain, the drain electrode of described 15th NMOS tube and the earth terminal connection of the second described assignment module, the described the 14th
The drain electrode connection of the source electrode of NMOS tube, the source electrode of the 13rd described NMOS tube and the 17th described NMOS tube, described the
The drain electrode connection of the source electrode of 15 NMOS tubes, the source electrode of the 16th described NMOS tube and the 18th described NMOS tube, it is described
The 17th NMOS tube source electrode and the source grounding of described the 18th NMOS tube；
The grid of the grid of the 4th described NMOS tube, the grid of the 7th described NMOS tube and the 12nd described NMOS tube connects
Connect and its connection end be described one-bit full addres the first addend signal input part；The grid of the 5th described NMOS tube, institute
The signal input part for the first single track input double track output heat insulation logic circuit stated, the grid of the 13rd described NMOS tube and institute
The grid for the 15th NMOS tube stated is connected and its connection end is the second addend signal input part of described one-bit full addres；Institute
The signal input part for the second single track input double track output heat insulation logic circuit stated is the first anti-phase of described one-bit full addres
Addend signal input part；The grid of the 14th described NMOS tube and the connection of the grid of the 16th described NMOS tube and its connection
Hold the second anti-phase addend signal input part for described one-bit full addres；The drain electrode of the 4th described NMOS tube and described the
The drain electrode of five NMOS tubes is connected with the inversion signal output end of described the first single track input double track output heat insulation logic circuit；Institute
The signal output part for the second single track input double track output heat insulation logic circuit stated is the summing signal of described one-bit full addres
Output end；The signal output part of described the first single track input double track output heat insulation logic circuit is described one-bit full addres
High-order carry signal output end；The grid of the 6th described NMOS tube and the connection of the grid of the 17th described NMOS tube and its company
Connect low order carry signal input part of the end for described one-bit full addres；The grid of the 18th described NMOS tube is described one
The anti-phase low order carry signal input part of position full adder.
3. a kind of one-bit full addres according to claim 2, it is characterised in that the first described assignment module includes the 8th
NMOS tube, the grid of described the 8th NMOS tube is the input of the first described assignment module, described the 8th NMOS tube
Drain as the output end of the first described assignment module, the source electrode of the 8th described NMOS tube is the first described assignment module
Earth terminal；The second described assignment module includes the 19th NMOS tube, and the grid of described the 19th NMOS tube is described the
The input of two assignment modules, the drain electrode of the 19th described NMOS tube is the output end of the second described assignment module, described
The 19th NMOS tube source electrode be the second described assignment module earth terminal.
4. a kind of one-bit full addres according to claim 3, it is characterised in that the channel length of the first described PMOS,
The raceway groove of the channel length of the second described PMOS, the channel length of the 3rd described PMOS and the 4th described PMOS
Length is 1~1.2 times of minimum channel length under PMOS standard technology；
The channel length of the first described NMOS tube, the channel length of the second described NMOS tube, described the 3rd NMOS tube
Channel length, the channel length of the 4th described NMOS tube, the channel length of the 5th described NMOS tube, the 6th described NMOS
The channel length of pipe, the channel length of the 7th described NMOS tube, channel length, the 9th NMOS tube of the 8th described NMOS tube
Channel length, the channel length of described tenth NMOS tube, the channel length of the 11st described NMOS tube, the described the tenth
The channel length of two NMOS tubes, the channel length of the 13rd described NMOS tube, the channel length of the 14th described NMOS tube,
Channel length, the 17th described NMOS tube of the channel length of the 15th described NMOS tube, the 16th described NMOS tube
Channel length, the channel length of the channel length of described 18th NMOS tube and the 19th described NMOS tube be NMOS
1~1.2 times of minimum channel length under pipe standards technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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| CN105720969B (en) * | 2016-01-22 | 2018-08-14 | 宁波大学 | A kind of one-bit full addres based on FinFET |
| CN113726331B (en) * | 2021-07-22 | 2023-12-12 | 杭州师范大学 | Power consumption constancy gate circuit unit based on double mask technology |
| CN116896594B (en) * | 2023-09-05 | 2023-11-21 | 深圳时识科技有限公司 | Conversion device, chip and electronic equipment between two-phase binding and two-phase double-track protocol |
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