CN113726331B - Power consumption constancy gate circuit unit based on double mask technology - Google Patents
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- H—ELECTRICITY
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- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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Abstract
The invention discloses a power consumption constancy gate circuit unit based on a double-mask technology, which consists of two single-rail double-mask precharge gate circuit units, and is characterized in that the single-rail double-mask precharge gate circuit units are as follows: a single-track positive logic double-mask or gate logic unit or a single-track negative logic double-mask or gate logic unit; the composition mode is as follows: the single-track positive logic double-mask OR gate logic unit consists of a single-track positive logic double-mask OR gate logic unit and a single-track negative logic double-mask OR gate logic unit. To make the circuit output signals f and f during the precharge phaseAre all precharged low level 0 signals; when the circuit enters the evaluation phase, two output signals f andalways and only one of them will have output inversion, satisfying a constant signal inversion rate, so that the power consumption of the circuit is constant under different input signals. The double-mask technology with the bridge structure can enable the output of the circuit to have randomness, and when the mask value cannot be accurately obtained, an attacker cannot obtain the accurate circuit output value, so that the power consumption analysis attack resistance of the circuit is further improved.
Description
Technical Field
The invention belongs to the field of circuit electronics, and particularly relates to a power consumption constancy gate circuit unit based on a double-mask technology.
Background
Aiming at the power consumption attack of the password chip, an attacker generally adopts the power consumption fluctuation characteristic of the power supply end of the password chip during working to acquire key information, so that the design of a circuit with constant power consumption is one of effective methods for defending the type of attack.
The constant power consumption technology mainly utilizes a double-rail precharge logic structure, and the structure can ensure that the power consumption of a logic circuit does not change along with the change of an operation result, so that the power consumption is relatively stable in operation. The double-mask technique utilizes four mask combinations, different mask combinations can enable the output of the circuit to generate different values, and the mask values are converted into correct logic when the chip is output. Therefore, the double-track precharge logic is combined with the circuit operation result, and the correlation between the circuit operation result and the power consumption can be further eliminated by utilizing the path selection function of the bridge mask structure, so that the difficulty of an attacker in analyzing the circuit operation result is increased, and the power consumption attack resistance of the circuit is improved.
Disclosure of Invention
In order to make up for the defects of the prior art, the invention provides a power consumption constancy gate circuit unit based on a double-mask technology.
The power consumption constancy gate circuit unit based on the double-mask technology consists of two single-rail double-mask precharge gate circuit units, and is characterized in that the single-rail double-mask precharge gate circuit units are as follows: a single-track positive logic double-mask or gate logic unit or a single-track negative logic double-mask or gate logic unit; the composition mode is as follows: the single-track positive logic double-mask OR gate logic unit consists of a single-track positive logic double-mask OR gate logic unit and a single-track negative logic double-mask OR gate logic unit.
Further, the single-track positive logic double-mask OR gate logic unit consists of PMOS transistors P1, P2, P3, P4 and P5 and NMOS transistors N1, N2, N3, N4, N5, N6 and N7, and the signals provided with the input ends are x, y and mask signals m 1 、m 2 、/>The clock signal CLK and the signal at the output are f; the drain electrode of the NMOS tube N1 is connected with input signals x and y, and is connected with the grid electrodes of N1 and N2, and the source electrode of N1 is connected with the source electrode of N2 and the drain electrode of P5 and is grounded; the drain electrode of the NMOS tube N2 is connected with the drain electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P4; the drain electrode of the NMOS tube N3 is connected with the drain electrode of the PMOS tube P4, the grid electrode of the N3 is connected with a clock signal CLKA, and the source electrode of the N3 is connected with the source electrode of the PMOS tube P5 and the drain electrodes of the NMOS tubes N4 and N5; grid electrode of NMOS tube N4 and mask signal m 1 The source electrode of the N4 is connected with the drain electrode of the N6; gate of NMOS transistor N5 and mask signal +.>The source electrode of N5 is connected with the drain electrode of N7; grid electrode of NMOS tube N6 and mask signal m 2 The source electrode of the N6 is connected with the source electrode of the N7 and is connected with an output signal f; gate of NMOS transistor N7 and mask signal +.>Are connected; the drain electrode of the PMOS tube P1 is connected with the grid electrode of the PMOS tube P1 and the grid electrode of the PMOS tube P2 and is connected with a reference current signal I 0 The source electrode of P1 is connected with the source electrodes of P2 and P3 and is connected to a power supply VDD; the grid electrode of the PMOS tube P2 is connected with the grid electrode of the P3, and the width-to-length ratio of the PMOS tube P2 is 0.5 times of that of the P1; the drain electrode of the PMOS tube P3 is connected with the source electrode of the P4, and the width-to-length ratio of the PMOS tube P3 is the same as that of the P1; the gate of the PMOS transistor P5 is connected to the clock signal CLKA.
Further, one clock cycle of the single-track positive logic double-mask OR gate logic unit is divided into two stages of precharge and evaluation, when the precharge stage is entered, all input signals are set to be low level 0, and the output of the circuit is also a precharge 0 signal; when the circuit enters the evaluation phase, since the bridge structure has the effect of path selection, when (m 1 ,m 2 ) When the value of (0, 0) or (1, 1), the circuit is turned on, and the circuit outputs positive logic.
Further, the single-track negative logic double-mask OR gate logic unit consists of PMOS transistors P1', P2', P3', P4', P5 'and NMOS transistors N1', N2', N3', N4', N5', N6', N7', wherein signals provided with input ends are x, y and mask signals m 1 、m 2 、/>The clock signal CLK and the signal at the output are +.>The drain electrode of the NMOS tube N1 'is connected with the input signals a and b, and is connected with the grid electrodes of the N1' and the N2', and the source electrode of the N1' is connected with the source electrode of the N2 'and the drain electrode of the P5' and grounded; the drain electrode of the NMOS tube N2' is connected with the drain electrode of the PMOS tube P2' and the grid electrode of the PMOS tube P4 '; the drain electrode of the NMOS tube N3 'is connected with the drain electrode of the PMOS tube P4', the grid electrode of the N3 'is connected with the clock signal CLKA, the source electrode of the N3' and the source electrode of the PMOS tube P5', the NMOS tube N4' andthe drain electrode of N5' is connected; grid electrode of NMOS tube N4' and mask signal m 1 The source electrode of the N4 'is connected with the drain electrode of the N6'; gate of NMOS transistor N5' and mask signal +.>The source electrode of the N5 'is connected with the drain electrode of the N7'; gate of NMOS transistor N6' and mask signal +.>The source of N6 'is connected to the source of N7' and to the output signal +.>Grid electrode of NMOS tube N7' and mask signal m 2 Are connected; the drain electrode of the PMOS tube P1' is connected with the grid electrode of the PMOS tube P1' and the grid electrode of the PMOS tube P2' and is connected with a reference current signal I 0 The source of P1' is connected with the sources of P2', P3' and connected to the power supply VDD; the grid electrode of the PMOS tube P2 'is connected with the grid electrode of the P3', and the width-to-length ratio of the PMOS tube P2 'is 0.5 times of that of the P1'; the drain electrode of the PMOS tube P3' is connected with the source electrode of the P4', and the width-to-length ratio of the PMOS tube P3' is the same as that of the P1; the gate of the PMOS transistor P5' is connected to the clock signal CLKA.
Further, one clock cycle of the single-track negative logic double-mask OR gate logic unit is divided into a precharge phase and an evaluation phase, when the precharge phase is entered, all input signals are set to be low level 0, and the output of the circuit is also a precharge 0 signal; when the circuit enters the evaluation phase, since the bridge structure has the effect of path selection, when (m 1 ,m 2 ) When the value of (0, 1) or (1, 0), the circuit is turned on, and the circuit outputs negative logic.
Further, the single-track positive logic double-mask OR gate logic unit and the single-track negative logic double-mask OR gate logic unit form a double-track double-mask OR gate logic unit, and the double-track double-mask OR gate logic unit has an input signal x, y, a, b, m 1 、m 2 、CLKA and output signal f, ++>F, performing the process; the clock cycle of the double-track double-mask OR gate logic unit is divided into two stages of precharging and evaluating, and the corresponding relation between the values of signals (x, y) and (a, b) at two groups of input ends is as follows:
| (x,y) | (0,0) | (0,1) | (1,0) | (1,1) |
| (a,b) | (1,1) | (0,0) | (0,0) | (0,0) |
when the clock signal CLKA is low, two outputs f andthe signals of the circuit (a) all output a precharge 0 signal, namely F is also 0, and the circuit enters a precharge stage; and when the clock signal CLKA is high, the output terminal +.>Signals complementary to F, F being different according to the value of the maskAnd outputting a signal and entering an evaluation stage.
Compared with the prior art, the invention has the following advantages:
the invention can better make the power consumption of the power supply end of the logic gate unit constant, and can also make the output signal randomly overturned after introducing the double-mask technology, thereby improving the difficulty of an attacker in guessing the output signal of the circuit, and further weakening the correlation between the operation result of the circuit and the power consumption and improving the capability of resisting the analysis attack of the power consumption.
Drawings
FIG. 1 is a circuit diagram of a single-rail or gate current type logic cell;
FIG. 2 is a circuit diagram of a single-rail NOR gate current type logic cell;
fig. 3 is a circuit diagram of a dual rail or gate current type logic cell.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail with reference to the accompanying drawings.
The utility model provides a power consumption constancy gate circuit unit design based on double mask technique, comprises two monorail double mask precharge gate circuit units, monorail double mask precharge gate circuit unit is: a single-track positive logical double-mask or gate logic unit or a single-track negative logical double-mask or gate logic unit.
The mode of the two monorail precharge double-mask gate circuit units is as follows: the double-track double-mask OR gate logic unit is composed of a single-track positive logic double-mask OR gate logic unit and a single-track negative logic double-mask OR gate logic unit.
As shown in FIG. 1, the single-rail positive logic double-mask OR gate logic unit of the invention consists of PMOS transistors P1, P2, P3, P4 and P5 and NMOS transistors N1, N2, N3, N4, N5, N6 and N7. The signals provided with the input ends are x, y and mask signals m 1 、m 2 、A clock signal CLK. The signal of the output end is f; the drain electrode of the NMOS tube N1 is connected with input signals x and y, and is connected with the grid electrodes of N1 and N2, and the source electrode of N1 is connected with the source electrode of N2 and the drain electrode of P5 and is grounded; the drain electrode of the NMOS tube N2 is connected with the drain electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P4; the drain electrode of the NMOS tube N3 is connected with the drain electrode of the PMOS tube P4, the grid electrode of the N3 is connected with a clock signal CLKA, and the source electrode of the N3 is connected with the source electrode of the PMOS tube P5 and the drain electrodes of the NMOS tubes N4 and N5; grid electrode of NMOS tube N4 and mask signal m 1 The source electrode of the N4 is connected with the drain electrode of the N6; gate of NMOS transistor N5 and mask signal +.>The source electrode of N5 is connected with the drain electrode of N7; grid electrode of NMOS tube N6 and mask signal m 2 The source of N6 is connected to the source of N7 and to the output signal f. Gate of NMOS transistor N7 and mask signal +.>Are connected. The drain electrode of the PMOS tube P1 is connected with the grid electrode of the PMOS tube P1 and the grid electrode of the PMOS tube P2 and is connected with a reference current signal I 0 The source electrode of P1 is connected with the source electrodes of P2 and P3 and is connected to a power supply VDD; the grid electrode of the PMOS tube P2 is connected with the grid electrode of the P3, and the width-to-length ratio of the PMOS tube P2 is 0.5 times of that of the P1; the drain electrode of the PMOS tube P3 is connected with the source electrode of the P4, and the width-to-length ratio of the PMOS tube P3 is the same as that of the P1; the gate of the PMOS transistor P5 is connected to the clock signal CLKA.
The single-track positive logic double-mask OR gate logic unit is divided into a precharge phase and an evaluation phase in one clock cycle, when the precharge phase is entered, all input signals are set to be low-level 0, and the output of the circuit is also a precharge 0 signal. When the circuit goes into the evaluation phase, the bridge structure has a path selection effect, when (m 1 ,m 2 ) When the value of (0, 0) or (1, 1), the circuit is turned on, and the circuit outputs positive logic.
As shown in FIG. 2, the single-rail negative logic double-mask OR gate logic unit of the present invention comprises PMOS transistors P1', P2', P3', P4', P5' and NMOS transistors N1', N2', N3', N4', N5', N6', N7 '. The signals provided with the input ends are x, y and mask signals m 1 、m 2 、/>A clock signal CLK. The output signal is +.>The drain electrode of the NMOS tube N1 'is connected with the input signals a and b, and is connected with the grid electrodes of the N1' and the N2', and the source electrode of the N1' is connected with the source electrode of the N2 'and the drain electrode of the P5' and grounded; the drain electrode of the NMOS tube N2' is connected with the drain electrode of the PMOS tube P2' and the grid electrode of the PMOS tube P4 '; the drain electrode of the NMOS tube N3' is connected with the drain electrode of the PMOS tube P4', the grid electrode of the N3' is connected with a clock signal CLKA, and the source electrode of the N3' is connected with the source electrode of the PMOS tube P5' and the drain electrodes of the NMOS tubes N4' and N5 '; grid electrode of NMOS tube N4' and mask signal m 1 The source electrode of the N4 'is connected with the drain electrode of the N6'; gate of NMOS transistor N5' and mask signal +.>The source electrode of the N5 'is connected with the drain electrode of the N7'; gate of NMOS transistor N6' and mask signal +.>The source of N6 'is connected to the source of N7' and to the output signal +.>Grid electrode of NMOS tube N7' and mask signal m 2 Are connected. The drain electrode of the PMOS tube P1' is connected with the grid electrode of the PMOS tube P1' and the grid electrode of the PMOS tube P2' and is connected with a reference current signal I 0 The source of P1' is connected with the sources of P2', P3' and connected to the power supply VDD; the grid electrode of the PMOS tube P2 'is connected with the grid electrode of the P3', and the width-to-length ratio of the PMOS tube P2 'is 0.5 times of that of the P1'; the drain electrode of the PMOS tube P3' is connected with the source electrode of the P4', and the width-to-length ratio of the PMOS tube P3' is the same as that of the P1The method comprises the steps of carrying out a first treatment on the surface of the The gate of the PMOS transistor P5' is connected to the clock signal CLKA.
Further, one clock cycle of the single-rail negative logic double-mask OR gate logic unit is divided into a precharge phase and an evaluation phase, when the precharge phase is entered, all input signals are set to be low level 0, and the output of the circuit is also a precharge 0 signal. When the circuit goes into the evaluation phase, the bridge structure has a path selection effect, when (m 1 ,m 2 ) When the value of (0, 1) or (1, 0), the circuit is turned on, and the circuit outputs negative logic.
The dual-rail dual-mask or gate logic unit of the present invention is shown in fig. 3, and is formed by combining the logic units shown in fig. 1 and 2. It has an input signal x, y, a, b, m 1 、m 2 、CLKA and output signal f, ++>F, performing the process; one clock cycle of the dual track mask or gate logic unit is divided into two phases, precharge and evaluate. The corresponding relation between the values of the signals (x, y) and the signals (a, b) of the two groups of input ends is as follows:
| (x,y) | (0,0) | (0,1) | (1,0) | (1,1) |
| (a,b) | (1,1) | (0,0) | (0,0) | (0,0) |
during the precharge phase, two outputs f andthe signals of (a) all output a precharge 0 signal, then F is also 0; in the evaluation phase, two outputs f and +.>Outputting complementary signals, using a bridge structure of double mask, the value of F being F or +.>The actual output value of the circuit cannot be accurately determined when the mask value cannot be obtained by an attacker. When the clock signal CLKA is low, two outputs f and +.>The signals of the circuit (a) all output a precharge 0 signal, namely F is also 0, and the circuit enters a precharge stage; and when the clock signal CLKA is high, the output terminal +.>And F is a signal complementary with F, and F selects different output signals according to different values of the mask, and enters an evaluation stage.
The purpose of the invention is to enable a circuit to output signals f and f during a precharge phaseAre all precharged low level 0 signals; when the circuit enters the evaluation phase, two output signals f and +.>Always and only one occurs, which satisfies a constant signal slew rate, so that the power consumption of the circuit at different input signals is constant. The double-mask technology with the bridge structure is introduced to ensure that the output of the circuit has randomness, and when the mask value cannot be accurately obtained, an attacker cannot obtain the accurate circuit output value, so that the power consumption analysis attack resistance of the circuit is further improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (2)
1. The utility model provides a power consumption constancy gate circuit unit based on double mask technique, comprises two monorail double mask precharge gate circuit units, its characterized in that, monorail double mask precharge gate circuit unit is: a single-track positive logic double-mask or gate logic unit or a single-track negative logic double-mask or gate logic unit; the composition mode is as follows: the single-track positive logic double-mask OR gate logic unit and the single-track negative logic double-mask OR gate logic unit are formed;
the single-track positive logic double-mask OR gate logic unit consists of PMOS (P-channel metal oxide semiconductor) transistors P1, P2, P3, P4 and P5 and NMOS transistors N1, N2, N3, N4, N5, N6 and N7, wherein signals provided with input ends are x, y, mask signals m1,m2、/>The clock signal CLK and the signal at the output are f; the drain electrode of the NMOS tube N1 is connected with the input signals x and y and connected with the grid electrodes of N1 and N2, and the source electrode of N1 is connected with the source electrode of N2 and P5The drain electrode is connected with the ground; the drain electrode of the NMOS tube N2 is connected with the drain electrode of the PMOS tube P2 and the grid electrode of the PMOS tube P4; the drain electrode of the NMOS tube N3 is connected with the drain electrode of the PMOS tube P4, the grid electrode of the N3 is connected with a clock signal CLKA, and the source electrode of the N3 is connected with the source electrode of the PMOS tube P5 and the drain electrodes of the NMOS tubes N4 and N5; the grid electrode of the NMOS tube N4 is connected with a mask signal m1, and the source electrode of the NMOS tube N4 is connected with the drain electrode of the NMOS tube N6; gate of NMOS transistor N5 and mask signal +.>The source electrode of N5 is connected with the drain electrode of N7; the grid electrode of the NMOS tube N6 is connected with the mask signal m2, the source electrode of the NMOS tube N6 is connected with the source electrode of the NMOS tube N7, and the NMOS tube N6 is connected with the output signal f; gate of NMOS transistor N7 and mask signal +.>Are connected; the drain electrode of the PMOS tube P1 is connected with the grid electrode of the PMOS tube P1 and the grid electrode of the PMOS tube P2 and is connected with a reference current signal I0, and the source electrode of the PMOS tube P1 is connected with the source electrodes of the PMOS tube P2 and the PMOS tube P3 and is connected to a power supply VDD; the grid electrode of the PMOS tube P2 is connected with the grid electrode of the P3, and the width-to-length ratio of the PMOS tube P2 is 0.5 times of that of the P1; the drain electrode of the PMOS tube P3 is connected with the source electrode of the P4, and the width-to-length ratio of the PMOS tube P3 is the same as that of the P1; the grid electrode of the PMOS tube P5 is connected with a clock signal CLKA;
the single-track positive logic double-mask OR gate logic unit has one clock period divided into two stages of precharging and evaluating, when the precharge stage is entered, all input signals are set to be low level 0, and the output of the circuit is also a precharge 0 signal; when the circuit enters an evaluation stage, the bridge structure has a path selection function, and when the value of (m 1, m 2) is (0, 0) or (1, 1), the circuit is conducted, and positive logic is output by the circuit;
the single-track negative logic double-mask OR gate logic unit consists of PMOS (P-channel metal oxide semiconductor) transistors P1', P2', P3', P4', P5 'and NMOS transistors N1', N2', N3', N4', N5', N6', N7', wherein signals provided with input ends are x, y, mask signals m1,m2、/>The clock signal CLK and the signal at the output are +.>The drain electrode of the NMOS tube N1 'is connected with the input signals a and b, and is connected with the grid electrodes of the N1' and the N2', and the source electrode of the N1' is connected with the source electrode of the N2 'and the drain electrode of the P5' and grounded; the drain electrode of the NMOS tube N2' is connected with the drain electrode of the PMOS tube P2' and the grid electrode of the PMOS tube P4 '; the drain electrode of the NMOS tube N3' is connected with the drain electrode of the PMOS tube P4', the grid electrode of the N3' is connected with a clock signal CLKA, and the source electrode of the N3' is connected with the source electrode of the PMOS tube P5' and the drain electrodes of the NMOS tubes N4' and N5 '; the grid electrode of the NMOS tube N4' is connected with a mask signal m1, and the source electrode of the NMOS tube N4' is connected with the drain electrode of the NMOS tube N6 '; gate of NMOS transistor N5' and mask signal +.>The source electrode of the N5 'is connected with the drain electrode of the N7'; gate of NMOS transistor N6' and mask signal +.>The source of N6 'is connected to the source of N7' and to the output signal +.>The grid electrode of the NMOS tube N7' is connected with a mask signal m 2; the drain electrode of the PMOS tube P1 'is connected with the grid electrode of the PMOS tube P1' and the grid electrode of the PMOS tube P2 'and is connected with a reference current signal I0, and the source electrode of the PMOS tube P1' is connected with the source electrodes of the PMOS tubes P2 'and P3' and is connected to a power supply VDD; the grid electrode of the PMOS tube P2 'is connected with the grid electrode of the P3', and the width-to-length ratio of the PMOS tube P2 'is 0.5 times of that of the P1'; the drain electrode of the PMOS tube P3' is connected with the source electrode of the P4', and the width-to-length ratio of the PMOS tube P3' is the same as that of the P1; the grid electrode of the PMOS tube P5' is connected with a clock signal CLKA;
the single-track negative logic double-mask OR gate logic unit is divided into a precharge phase and an evaluation phase in one clock cycle, when the single-track negative logic double-mask OR gate logic unit enters the precharge phase, all input signals are set to be low level 0, and the output of the circuit is also a precharge 0 signal; when the circuit enters the evaluation stage, the bridge structure has the function of path selection, and when the value of (m 1, m 2) is (0, 1) or (1, 0), the circuit is conducted, and negative logic is output by the circuit.
2. The power consumption constancy gate unit based on the double-mask technology of claim 1, wherein the single-track positive logic double-mask or gate logic unit and the single-track negative logic double-mask or gate logic unit form a double-track double-mask or gate logic unit, the double-track double-mask or gate logic unit has input signals x, y, a, b, m1, m2,CLKA and output signal f, ++>F, performing the process; the clock cycle of the double-track double-mask OR gate logic unit is divided into two stages of precharging and evaluating, and the corresponding relation between the values of signals (x, y) and (a, b) at two groups of input ends is as follows:
(x,y)(0,0)(0,1)(1,0)(1,1)
(a,b)(1,1)(0,0)(0,0)(0,0)
when the clock signal CLKA is low, two outputs f andthe signals of the circuit (a) all output a precharge 0 signal, namely F is also 0, and the circuit enters a precharge stage; and when the clock signal CLKA is high, the output terminal +.>And F is a signal complementary with F, and F selects different output signals according to different values of the mask, and enters an evaluation stage.
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| CN112491410A (en) * | 2020-11-18 | 2021-03-12 | 杭州师范大学 | Power consumption constancy gate circuit unit based on precharge logic and mask technology |
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| CN109327206A (en) * | 2018-09-30 | 2019-02-12 | 天津大学 | Power consumption planarizes standard integrated circuit |
| CN112104357A (en) * | 2020-09-07 | 2020-12-18 | 杭州师范大学 | Power consumption balance type current type CMOS gate circuit unit based on double-track precharge logic |
| CN112491410A (en) * | 2020-11-18 | 2021-03-12 | 杭州师范大学 | Power consumption constancy gate circuit unit based on precharge logic and mask technology |
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