CN102035530A - Optimal maintaining pipe domino circuit used for high-performance VLSI (Very Large Scale Integrated Circuit) - Google Patents
Optimal maintaining pipe domino circuit used for high-performance VLSI (Very Large Scale Integrated Circuit) Download PDFInfo
- Publication number
- CN102035530A CN102035530A CN 201010515484 CN201010515484A CN102035530A CN 102035530 A CN102035530 A CN 102035530A CN 201010515484 CN201010515484 CN 201010515484 CN 201010515484 A CN201010515484 A CN 201010515484A CN 102035530 A CN102035530 A CN 102035530A
- Authority
- CN
- China
- Prior art keywords
- circuit
- holding tube
- domino
- voltage
- domino circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention relates to an optimal maintaining pipe domino circuit used for a high-performance VLSI (Very Large Scale Integrated Circuit), i.e. in the domino circuit, the balance of a plurality of important parameters of dynamic power consumption, leakage current, noise margin, circuit delay, process fluctuation resisting coefficients and the like is realized by applying an optimal maintaining pipe technology through regulating the substrate voltage and the power supply voltage of the maintaining pipe, therefore, the domino circuit reaches optimal comprehensive property, wherein the power supply voltage and the substrate voltage of the maintaining pipe are respectively VddL and Vb, the power supply voltages and the substrate voltages of left PMOS (P-channel Metal Oxide Semiconductor) pipes except the maintaining pipe are Vdd, the substrate voltages of all NOMS (N-channel Metal Oxide Semiconductor) pipes in the circuit are ground voltages Gnd, and the relation of the voltages is: Gnd<Vb<VddL<Vdd.
Description
Technical field
The present invention relates to a kind of low consumption circuit, is a kind of low-power consumption domino circuit of using optimum holding tube technology specifically, belongs to the integrated circuit application.
Background technology
The good characteristic that domino circuit is fast with its speed, area is little is widely used in the critical path part and memory of processor, is the dynamic logic circuit of the main flow of high-performance processor and memory.The domino circuit of standard is an important branch of cmos circuit, and it is that a static inverter constitutes on the dynamic logic piece string that is made of one group of NMOS pipe, as shown in Figure 1.The operation principle of circuit is as follows: when clock signal CLK=0, be the preliminary filling stage of circuit, this moment, preliminary filling PMOS pipe P1 was in conducting state, dynamic node by preliminary filling to high level V
Dd, the static inverter that is connected in series with it is output as low level; When CLK=1, evaluate phase for circuit, at this moment P1 ends, the input signal that dynamic node is looked NMOS pulldown network (PDN) discharges conditionally: if there is the DC channel from the dynamic node to ground in NMOS pipe logical block, dynamic node is discharged to low level over the ground so, and output rises to high level; Otherwise dynamic node keeps high value V
Dd, up to following one-period.
In traditional domino circuit, the substrate of all PMOS pipes connects supply voltage, the substrate earthed voltage of all NMOS pipes.
In domino circuit, holding tube keeps correct logic level state to play crucial effects to the circuit dynamic node.In the preliminary filling stage of circuit, as shown in Figure 2, the holding tube conducting, produce pull-up current, thereby improved antinoise (comprising the leakage current in the pulldown network) ability of dynamic node, make dynamic node remain on high level, obviously, the size of holding tube is big more, and pull-up current is big more, and the noise margin of circuit is big more; Evaluate phase at circuit, as shown in Figure 3, if there be the path of dynamic node to ground voltage, dynamic node will by drop-down be low level, this moment, the evaluation electric current in the pulldown network was competed with the pull-up current of holding tube, therefore, the pull-up current of holding tube is also referred to as the competition electric current, and obviously, the size of holding tube is big more, the competition electric current is big more, and the evaluation speed of circuit is slow more.And holding tube is big more, and the power consumption of circuitry consumes is big more.Therefore, the holding tube of large-size effectively raises the noise resisting ability of domino circuit, but has increased the power consumption of circuit simultaneously, and has reduced the speed of circuit.In addition, along with integrated circuit technology develops into deep-submicron, the unsteady parameter of technology is increasing to the influence of circuit.Therefore, realizing the equilibrium of a plurality of important parameters such as the unsteady coefficient of dynamic power consumption, leakage current, noise margin, circuit delay and anti-technology, is the domino circuit key in application thereby make domino circuit reach optimized combination property.
Summary of the invention
The objective of the invention is to use optimum holding tube technology, thereby effectively reduce the power consumption of domino circuit, improve the performance of circuit.
Be used for the optimum holding tube domino circuit of high-performance VLSI, comprise the input signal end, output signal end, clock signal terminal, preliminary filling pipe, holding tube, the clock pipe is exported static inverter and pulldown network (PDN), and wherein the supply voltage of holding tube and underlayer voltage are respectively V
DdLAnd V
b, the supply voltage of all the other PMOS pipes and underlayer voltage all are V except that holding tube
Dd, the underlayer voltage of all NOMS pipes is ground voltage Gnd in the circuit, the magnitude relationship of voltage is: Gnd＜V
b＜V
DdL＜V
Dd
The above-mentioned optimum holding tube domino circuit that is used for high-performance VLSI, the supply voltage of holding tube and underlayer voltage V
DdLAnd V
bCan regulate, with better balanced power consumption, circuit parameters such as time of delay and noise margin, definition coefficient OP is as the index of weighing the domino circuit combination property.
Wherein, Power is the power consumption of circuit, and Delay is the delay of circuit, and Noise_immunity is the noise margin of circuit, and PDP is the power consumption lagged product of circuit.When OP hour, the combination property optimum of circuit.
Drop-down (PDN) network of the above-mentioned optimum holding tube domino circuit that is used for high-performance VLSI can be any gate, as: or door, with door, same or door or XOR gate.
The above-mentioned optimum holding tube domino circuit that is used for high-performance VLSI can be economized and remove the clock pipe, i.e. the direct ground connection of pulldown network (PDN).
For multistage domino circuit, optimum holding tube technology can be applied to each grade domino circuit.
Compare with traditional domino circuit, the present invention can obtain following beneficial effect:
In domino circuit, holding tube keeps correct logic level state to play crucial effects to the circuit dynamic node.The holding tube of large-size effectively raises the noise resisting ability of domino circuit, but has increased the power consumption of circuit simultaneously, and has reduced the speed of circuit.In addition, the unsteady parameter of technology is increasing to the influence of domino circuit.Therefore, adopt optimum holding tube technology, realized the optimum of comprehensive parameters such as the unsteady coefficient of dynamic power consumption, leakage current, noise margin, circuit delay and anti-technology.
Description of drawings:
The domino circuit schematic diagram of Fig. 1 standard;
Fig. 2 preliminary filling stage domino circuit schematic diagram;
Fig. 3 evaluate phase domino circuit schematic diagram;
Optimum holding tube domino of Fig. 4 or door schematic diagram;
The OP value distribution map of Fig. 5 domino or door;
Fig. 6 removes the optimum holding tube domino circuit schematic diagram that is used for high-performance VLSI of clock pipe.
Embodiment
Be further described for the present invention below in conjunction with drawings and Examples.
Present embodiment is applied to domino or door with optimum holding tube technology.
Be illustrated in figure 4 as optimum holding tube domino or door, it is made up of several parts:
The input signal end, output signal end, clock signal terminal, the preliminary filling pipe, holding tube, the clock pipe is exported static inverter and pulldown network (PDN), and wherein the supply voltage of holding tube and underlayer voltage are respectively V
DdLAnd V
b, the supply voltage of all the other PMOS pipes and underlayer voltage all are V except that holding tube
Dd, the underlayer voltage of all NOMS pipes is ground voltage Gnd in the circuit, the magnitude relationship of voltage is: Gnd＜V
b＜V
DdL＜V
Dd
The low supply voltage holding tube has two important function: the first, and low supply voltage can effectively reduce the dynamic power consumption of holding tube and leak power consumption; The second, in the evaluate phase of many promises circuit, because holding tube is a low supply voltage, the competition electric current will reduce accordingly, thereby improve the drop-down speed of dynamic node, reduce the delay of circuit.
But the supply voltage that reduces holding tube also will bring serious problem: in the evaluate phase of domino circuit, if there is no dynamic node is to the path of ground voltage, and dynamic node still needs to keep high level by holding tube.But the competition electric current of holding tube reduces along with the reduction of supply voltage, thereby weakened the maintenance effect, cause dynamic node and output to produce unnecessary voltage and float, cause discharging and recharging of electric capacity, thereby part has been offseted the reduction effect of low supply voltage technology to power consumption.
Substrate biasing holding tube technology has and low supply voltage holding tube technology reverse effect.In the evaluate phase of many promises circuit, if there be the path of dynamic node to ground voltage, dynamic node is drop-down when being ground level, because the substrate biasing technique, the competition electric current of holding tube increases accordingly, has increased the delay of circuit; If there is no dynamic node is to the path of ground voltage, when dynamic node still keeps high level, the electric current of holding tube because of threshold voltage reduce increase, strengthened the maintenance effect, increased the noise margin of circuit.But because the use of substrate biasing technique, sub-threshold current leakage also increases thereupon, thereby has increased the leakage power consumption of holding tube.
By above analysis as can be seen, the low supply voltage holding tube has reduced the power consumption of circuit, has improved the speed of circuit, but has reduced the noise resisting ability of circuit; Substrate biasing holding tube has improved the noise resisting ability of circuit, but has increased the power consumption and the delay of circuit.Therefore,, and regulate the size of holding tube, can obtain the domino circuit of combination property optimum, optimum holding tube technology that Here it is if two technology of integrated application design low supply voltage substrate biasing holding tube domino circuit.In addition, the substrate biasing technique can also the compensate for process parameter be floated to the influence of holding tube.
Fig. 5 is the OP value distribution map of domino or door, when OP hour, circuit has optimum properties.As shown in the figure, V
DdlExcursion be 0.7V to 0.8V, V
bExcursion be that 0.1V is to 0.8V.As can be seen from the figure, work as V
Ddl=0.74V, V
bDuring=0.6V, the value minimum of OP,
This shows that optimum holding tube technology effectively raises the combination property of domino circuit.
In addition, drop-down (PDN) network of the above-mentioned optimum holding tube domino circuit that is used for high-performance VLSI can be any gate, as: or door, with door, same or door or XOR gate.
The above-mentioned optimum holding tube domino circuit that is used for high-performance VLSI can be economized and remove the clock pipe, i.e. the direct ground connection of pulldown network (PDN) is so as Fig. 6.
For multistage domino circuit, optimum holding tube technology can be applied to each grade domino circuit.
Claims (5)
1. be used for the optimum holding tube domino circuit of high-performance VLSI, comprise the input signal end, output signal end, clock signal terminal, preliminary filling pipe, holding tube, the clock pipe is exported static inverter and pulldown network (PDN), and wherein the supply voltage of holding tube and underlayer voltage are respectively V
DdLAnd V
b, the supply voltage of all the other PMOS pipes and underlayer voltage all are V except that holding tube
Dd, the underlayer voltage of all NOMS pipes is ground voltage Gnd in the circuit, the magnitude relationship of voltage is: Gnd＜V
b＜V
DdL＜V
Dd
2. the optimum holding tube domino circuit that is used for high-performance VLSI according to claim 1 is characterized in that: the supply voltage of holding tube and underlayer voltage V
DdLAnd V
bCan regulate, with better balanced power consumption, circuit parameters such as time of delay and noise margin, definition coefficient OP is as the index of weighing the domino circuit combination property.
Wherein, Power is the power consumption of circuit, and Delay is the delay of circuit, and Noise_immunity is the noise margin of circuit, and PDP is the power consumption lagged product of circuit.When OP hour, the combination property optimum of circuit.
3. the optimum holding tube domino circuit that is used for high-performance VLSI according to claim 1 is characterized in that: drop-down (PDN) network can be any gate, as: or door, with door, same or door or XOR gate.
4. the optimum holding tube domino circuit that is used for high-performance VLSI according to claim 1 is characterized in that: can economize and remove the clock pipe, be i.e. the direct ground connection of pulldown network (PDN).
5. the optimum holding tube domino circuit that is used for high-performance VLSI according to claim 1 is characterized in that: for multistage domino circuit, optimum holding tube technology can be applied to each grade domino circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010515484 CN102035530A (en) | 2010-10-15 | 2010-10-15 | Optimal maintaining pipe domino circuit used for high-performance VLSI (Very Large Scale Integrated Circuit) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010515484 CN102035530A (en) | 2010-10-15 | 2010-10-15 | Optimal maintaining pipe domino circuit used for high-performance VLSI (Very Large Scale Integrated Circuit) |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102035530A true CN102035530A (en) | 2011-04-27 |
Family
ID=43887950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010515484 Pending CN102035530A (en) | 2010-10-15 | 2010-10-15 | Optimal maintaining pipe domino circuit used for high-performance VLSI (Very Large Scale Integrated Circuit) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102035530A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873043A (en) * | 2014-03-14 | 2014-06-18 | 北京工业大学 | High-performance domino circuit design based on clock extraction bias voltage technology |
| CN106531056A (en) * | 2017-01-18 | 2017-03-22 | 京东方科技集团股份有限公司 | CMOS logic unit and logic circuit, gate drive circuit and display device |
| CN109637565A (en) * | 2017-10-05 | 2019-04-16 | 印芯科技股份有限公司 | Memory cell |
| CN112951176A (en) * | 2021-04-20 | 2021-06-11 | 合肥京东方显示技术有限公司 | Data sampler, drive circuit, display panel and display device |
-
2010
- 2010-10-15 CN CN 201010515484 patent/CN102035530A/en active Pending
Non-Patent Citations (1)
| Title |
|---|
| 《半导体学报》 20081231 汪金辉，宫娜，耿淑琴，侯立刚，吴武臣，董利民 45nm工艺pn混合下拉网络多米诺异或门设计 2443-2448 1-5 第29卷, 第12期 * |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103873043A (en) * | 2014-03-14 | 2014-06-18 | 北京工业大学 | High-performance domino circuit design based on clock extraction bias voltage technology |
| CN103873043B (en) * | 2014-03-14 | 2017-07-14 | 北京工业大学 | The high-performance domino circuit design of bias techniques is extracted based on clock |
| CN106531056A (en) * | 2017-01-18 | 2017-03-22 | 京东方科技集团股份有限公司 | CMOS logic unit and logic circuit, gate drive circuit and display device |
| CN106531056B (en) * | 2017-01-18 | 2019-06-07 | 京东方科技集团股份有限公司 | CMOS logic unit, logic circuit, gate driving circuit and display device |
| CN109637565A (en) * | 2017-10-05 | 2019-04-16 | 印芯科技股份有限公司 | Memory cell |
| CN112951176A (en) * | 2021-04-20 | 2021-06-11 | 合肥京东方显示技术有限公司 | Data sampler, drive circuit, display panel and display device |
| CN112951176B (en) * | 2021-04-20 | 2022-09-06 | 合肥京东方显示技术有限公司 | Data sampler, drive circuit, display panel and display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW423218B (en) | Charge-redistribution low-swing differential logic circuit | |
| CN102437836B (en) | Low-power-consumption pulse type D trigger | |
| CN104158516B (en) | voltage comparator | |
| CN108233896A (en) | A kind of low-power consumption sense amplifier type d type flip flop | |
| CN102035530A (en) | Optimal maintaining pipe domino circuit used for high-performance VLSI (Very Large Scale Integrated Circuit) | |
| KR101341734B1 (en) | A cmos differential logic circuit using voltage boosting technique | |
| Kim et al. | A 6.9-μm 2 3.26-ns 31.25-fj robust level shifter with wide voltage and frequency ranges | |
| Rjoub et al. | Low-power/low-swing domino CMOS logic | |
| CN102386908B (en) | Heat insulation domino circuit and heat insulation domino ternary AND gate circuit | |
| CN109697306B (en) | Encoder based on TDPL logic | |
| Rastogi et al. | Implementing low-power dynamic adders in MTCMOS technology | |
| Kim et al. | Low-voltage bootstrapped CMOS drivers with efficient conditional bootstrapping | |
| CN104410404A (en) | Adiabatic logic circuit and single bit full adder | |
| Lee et al. | Split-level precharge differential logic: A new type of high-speed charge-recycling differential logic | |
| Vo et al. | Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes | |
| Upadhyay et al. | Power and stability analysis of a proposed 12T MTCMOS SRAM cell for low power devices | |
| Ho et al. | A 0.1–0.3 V 40–123 fJ/bit/ch on-chip data link with ISI-suppressed bootstrapped repeaters | |
| Zhang et al. | Leakage Reduction of Power-Gating Sequential Circuits Based on Complementary Pass-Transistor Adiabatic Logic Circuits | |
| CN201918976U (en) | Dormant tube domino circuit used for low power consumption VLSI (very-large-scale integration) | |
| Chavan et al. | High performance and low power ONOFIC approach for VLSI CMOS circuits design | |
| Choe et al. | Dynamic half rail differential logic for low power | |
| Upadhyay et al. | Low power with high stability 12T MTCMOS based SRAM cell for write operation | |
| CN106710614A (en) | High-performance sense amplifier technology for memory | |
| Bansal et al. | A novel low power keeper technique for pseudo domino logic | |
| Majumder et al. | Power and energy efficient logic design using stacking effect of transistors |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20110427 |