CN104022758A - Power consumption equalization trigger with clearing setting port - Google Patents

Abstract

Disclosed is a power consumption equalization trigger with a clearing setting port. The trigger comprises a pre-stage latch module, an intermediate circuit and a rear-stage latch module which are connected in series. The pre-stage latch module and the rear-stage latch module each employ a dynamic difference circuit controlled by a single clock; the intermediate circuit comprises an intermediate independent setting module, a data isolation module and a data storage module; the intermediate independent setting module performs initial state arrangement on the trigger through an independent setting signal; the data isolation module comprises two clock-controlled transfer gates to isolate an evaluating signal and a setting signal; the data storage module comprises a pair of intersected coupling inverters for data storage; in a clock first half period, the pre-stage latch module performs evaluation, and the rear-stage module performs a precharging state; and in a clock later half period, the pre-stage latch module performs the precharging state, and the rear-stage latch module performs the evaluation for outputting. The power consumption equalization trigger has the advantages of good power consumption proportionality, small area cost, quite high performance, simple sequential control and the like.

Description

The balanced trigger of a kind of power consumption with zero clearing set port

Technical field

The present invention relates to integrated circuit (IC) design field, be specifically related to a kind of balanced trigger of power consumption of the zero clearing set port for anti-power consumption attack.

Background technology

Along with computer network, microelectronics and related science technology develop rapidly, impel the level of informatization to improve constantly, information security becomes the topic that all trades and professions are paid close attention to most.Therefore important information is encrypted and becomes the most direct method of protection information safety; be accompanied by recent years the development of integrated circuit, crypto chip is good with its closure, crack difficulty large, crack the feature that difficulty is high and be used for realizing information encryption by numerous industries.But the fast development along with microelectronic industry, crypto chip bypass attack technology (Side-Channel Leakage) becomes the threat of crypto chip maximum, Fig. 1 is that bypass attack is implemented schematic diagram, according to the known crypto chip of diagram, when being encrypted computing, can produce a large amount of bypass information (power consumption, electromagnetic radiation and the running time etc. of revealing when encrypted), therefore assailant can and carry out mass data statistical analysis by sample bypass information, can effectively implement cipher key attacks.In numerous crypto chip bypass attacks, power consumption attack is high with its attack efficiency, attack cost is low, implement difficulty relatively easily slowly becomes the most frequently used attack means of attack crypto chip.As shown in Fig. 2 a, Fig. 2 b, take the generation source of inverter power consumption in example explanation circuit, because the mobility of hole and electronics has difference, so inverter PMOS pipe is different with the width of NMOS pipe, drain capacitance is also different, and formula (1) is counting circuit dynamic power consumption equation; Formula (2) is load capacitance C _lthe energy producing within the unit interval.

P _dyn＝C _LVDD ²f _0→1 (1)

$E_{\mathrm{VDD}}={\∫}_0^{\∞}{i}_{\mathrm{vdd}}{\left(t\right)}^{*}{\mathrm{VDDd}}_t=C_t*\mathrm{VDD}{\∫}_0^{\mathrm{vdd}}{d}_{\mathrm{vout}}=C_L{\mathrm{VDD}}^2---\left(2\right)$

Known as load capacitance C according to formula (2) _lby PMOS, manage when charging, output voltage rises to VDD from 0, now from power supply, draws certain energy.A part for this energy consumes in PMOS pipe with heat energy form, and all the other just leave in load capacitance.When there is the saltus step of 0-1 in input signal, load capacitance C _lon electric charge will be let go, wherein another part is also consumed with the form of heat energy.The angle moving from electric charge, no matter at charging stage or discharge regime, it is C that each switch periods (by height on earth or from low to high) needs the energy of a fixed qty _lvDD ², and in real work, must consider the switching frequency f of device _{0 → 1}(representing catabiotic toggle frequency).By (1) formula, can find out that affect the factor of dynamic power consumption also has the toggle frequency of input signal except node capacitor, supply voltage.The switch activity of a circuit is relevant with essence and the statistical property of input signal, if input signal remains unchanged, any switch can not occur, so dynamic power consumption is zero, otherwise the signal of velocity variations can cause multiple switching and power consumption.Therefore guarantee that any different input all produces the core concept that identical power consumption becomes the design of power consumption logic of Equilibrium under changing.

At present, in the logical design of the balanced trigger of power consumption, adopt dynamic double track precharge structure to be embodied as the juche idea in order to design, the balanced trigger of power consumption that present stage proposes mainly comprises SDDL FF, MSDDL FF, TDPL, as shown in Figure 3.SDDL FF (Single Dynamic Different Logic flip-flop) consists of two common d type flip flops and two NOR gate, wherein the input of two d type flip flops is difference input, NOR gate input is control signal and d type flip flop output, and NOR gate mainly completes the generation work of combinational circuit precharging signal.When control signal each cycle is carried out saltus step, NOR gate all can present the variation that is pre-charged to evaluation, and the input of NOR gate, output be all differential signal, so the power consumption of NOR gate each cycle consumption is all the same.But d type flip flop can not show power consumption equalization characteristic, because can not making trigger each cycle, control signal is all pre-charged to the variation of evaluation, so the power consumption that (hold mode) consumes when d type flip flop input is the variation of 0 to 1 variation (transitional states) and 0 to 0 is different.As shown in Figure 4, for the electric current matching waveform of SDDL under four kinds of inputs change, by analyzing, can find out that current waveform has notable difference, so SDDL FF can not realize power consumption equilibrium.MSDDL FF (Master-Slave Dynamic Different Logic flip-flop) adopts by 4 common d type flip flop cascades between two, form pipeline organization, the design of precharge control logic is at the input of MSDDL, precharging signal and evaluation signal can alternately be propagated in two pairs of triggers like this, make each trigger can periodically complete precharge and evaluate operation, so MSDDL FF can arrive good power consumption harmony.So but due to 4 d type flip flops between two cascade input signal to could export through two all after dates, so control signal will be carried out the operating state that frequency division could meet MSDDL, this has caused greater loss to aspect of performance, and MSDDL has larger area overhead simultaneously.TDPL (three-phase dual-rail pre-charge logic) realizes and has adopted three stage structure as shown in Figure 6, prime, late-class circuit adopt identical dynamic difference circuit structure, but the forward and backward level of TDPL dynamic difference structure need to realize circuit function by three control signals, as shown in Figure 5.Thereby this makes inclusion relation between control signal signal inclusion relation more complicated and this complexity in dynamic logic design can produce larger short circuit current to cause serious power consumption to reveal.The data holding circuit of TDPL adopts NAND gate S-R latch, described in Fig. 2, because static NAND gate circuit structure there are differences itself, the power consumption that therefore output all Bu Tong produces at the transistor size that produces logical one and the institute's conducting of " 0 " time also has larger difference, so TDPL cannot realize good power consumption harmony.Table 1 is the comparison of the balanced trigger of existing power consumption aspect area, performance, power consumption.

In sum, although having advantage aspect area, SDDL FF cannot accomplish that power consumption is balanced, although it is harmonious that MSDDL FF can reach good power consumption, need to be with 4 connected in series realizations of standard static trigger, performance is lower, area overhead is too large, does not have advantage in Project Realization, although TDPL adopts syllogic to realize the parallel work-flow of precharge and evaluation, but the prime of TDPL, rear class dynamic difference circuit sequence controls complexity and intermediate data storage circuit adopts NAND gate S-R latch structure, according to known because static NAND gate circuit structure there are differences itself described in Fig. 2, so output has larger difference in generation logical one and the power consumption that " 0 " produces, the power consumption difference being produced by this body structure when carrying out multiply periodic cryptographic calculation will be exaggerated this crypto chip is had to fatal threat, and because existing the natural defect of structure, NAND gate itself cannot realize better power consumption equilibrium, more complicated this of sequencing control of TDPL also has larger difficulty to global design.

Summary of the invention

The technical problem to be solved in the present invention is just, the technical problem existing for prior art the invention provides that a kind of power consumption harmony is good, area overhead is little, performance is higher, sequencing control is simply with the balanced trigger of power consumption of zero clearing set port.

The balanced trigger of power consumption with zero clearing set port, comprises by prime latch module connected in series, intermediate circuit and rear class latch module, and three modules are all usingd differential signal as input, the output of generation difference; Described prime latch module and rear class latch module all adopt the dynamic difference circuit of single clock control; Independent set module, data isolation module and data memory module in the middle of described intermediate circuit comprises, the independent set module in described centre is carried out initial state setting by independent asserts signal to trigger, described data isolation module comprises that two groups of clock transmission gates isolate evaluation signal and asserts signal, and described data memory module comprises that pair of cross coupled inverters carries out data storage; Half period before clock, described prime latch module is carried out evaluation, rear class latch module is carried out pre-charge state; In the later half cycle of clock, described prime latch module is carried out pre-charge state, rear class latch module is carried out evaluation output, realizes the parallel work-flow of three modules in one-period.

As a further improvement on the present invention: described prime latch module and rear class latch module all adopt SABL dynamic difference structure and have data latch function.

As a further improvement on the present invention: the inverter with single-ended control signal that the independent set module in described centre comprises realizing a PMOS of set function and a NMOS and is used for realizing data inverter functionality.

Compared with prior art, the invention has the advantages that:

1, the present invention can realize and clock cycle same frequency work, improves flip-flop operation performance.

2, the balanced trigger of power consumption of the present invention has distinctive set function.

3, in the present invention, prime latchs, rear class latchs, intermediate circuit all adopts symmetric difference circuit structure, and all modules are all difference input, difference output, so the power consumption of this trigger is harmonious better.

4, trigger of the present invention has that power consumption is harmonious better, area overhead is less, performance is higher, trigger is controlled better simply advantage.

Accompanying drawing explanation

Fig. 1 is the principle schematic that in prior art, bypass attack is implemented.

Fig. 2 is the principle schematic that in prior art, inverter power consumption produces; Schematic diagram when wherein, Fig. 2 (a) changes for 0-1 occurs output; Schematic diagram when Fig. 2 (b) changes for 1-0 occurs output.

Fig. 3 is the electrical block diagram of SDDL FF and MSDDL FF in prior art.

Fig. 4 is the electric current matching schematic diagram of SDDL FF trigger under four kinds of inputs change in prior art.

Fig. 5 is the schematic diagram of the forward and backward level of TDPL circuit structure in prior art.

Fig. 6 is the structural representation of TDPL circuit in prior art.

Fig. 7 is the structural representation of prime in the present invention, late-class circuit.

Fig. 8 is the working state schematic representation of prime in the present invention, late-class circuit.

Fig. 9 is forward and backward level latch module electric current matching waveform schematic diagram under two kinds of inputs change in the present invention.

Figure 10 is the electrical block diagram of independent set module in the present invention.

Figure 11 is independent set module asserts signal and clock signal restriction relation schematic diagram in the present invention.

Figure 12 is structural representation of the present invention.

Figure 13 is internal node operation principle schematic diagram in the present invention.

Figure 14 is the electric current matching waveform schematic diagram that the present invention produces under four kinds of different inputs change.

Embodiment

Below with reference to Figure of description and specific embodiment, the present invention is described in further details.

As shown in figure 12, the balanced trigger of a kind of power consumption with zero clearing set port of the present invention (being called for short: TSSDDL FF is Three-step Separate Set Dynamic Different Logic flip-flop), adopt three stage structure, comprise by prime latch module connected in series, intermediate circuit and rear class latch module, three modules are all usingd differential signal as input, the output of generation difference, so the total power consumption that each cycle trigger produces is the same; Prime latch module and rear class latch module all adopt same difference channel structure, independent set module, data isolation module and data memory module in the middle of intermediate circuit comprises, and three all adopts full symmetric circuit structure to realize.Middle independent set module is carried out initial state setting by independent asserts signal to trigger, data isolation module adopts two groups of clock transmission gates to isolate evaluation signal and asserts signal, and data memory module adopts the cross coupling inverter of a pair of minimum dimension to realize data storage.The balanced trigger of power consumption of the present invention is realized the parallel work-flow of precharge and evaluation a clock cycle, the half period before clock, prime latch module is carried out evaluation, rear class latch module is carried out precharge generation (0.0) state; In the later half cycle of clock, prime latch module is carried out precharge (0.0) state, rear class latch module is carried out evaluation output, thereby realizes the parallel work-flow of three modules in one-period.

In the present embodiment, prime latch module, rear class latch module all adopt SABL dynamic difference structure to realize power consumption equilibrium, and circuit has data latch function.

In the present embodiment, middle independent set module adopts a PMOS and a NMOS to realize set function, and data inverter functionality adopts with the inverter of single-ended control signal and realizes.

In other words, when concrete application, in order not reduce the operating frequency of encrypted circuit, the design of trigger of the present invention adopts three grades of circuit to realize.First order circuit and tertiary circuit (prime latch module and rear class latch module) are all by a dynamic latch module composition, and difference is that first order inverter is to be controlled by the original signal of clock, and the third level is controlled by the inverted signal of clock.Intermediate circuit comprises the set module of two special circuits formations, transmission gate and a cross-linked feedback loop of two trailing edge conductings, and wherein RESET_MOD1 realizes the function of NOR; RESET_MOD2 realizes the function of NAND.When asserts signal is effective, middle independent set module is carried out initialization operation to trigger and is made output and D and Dn irrelevant, it is that the data that high level keeps are propagated in the past at trailing edge at CP that two transmission gates of opening at clock trailing edge are used for clock, and by the feedback loop of a low level conducting, data is stored.The operating state of this trigger is mainly by clock CLK and two signal controlling of asserts signal reset.

As shown in Figure 7, in the present embodiment, prime latch module, rear class latch module all can adopt SABL (Sense Amplifier Based Logic) dynamic difference circuit structure to realize.Input signal X and Xn are differential input signal, and Q, Qn are differential output signal, and this circuit has following three features:

(1) gate adopts dynamic operation mode, in each cycle, circuit is carried out to precharge and evaluate operation.In circuit structure, between net1 and net2, connect a NMOS pipe, whole like this circuit is in precharge and evaluation can be accomplished to charge completely and electric discharge completely.

(2) due to the existence of n6 pipe, in evaluate phase, circuit output after rising edge clock samples data to enter high level can not be subject to any variation of input and change, thereby reaches data latch function.

(3) in circuit, cross-linked inverter is used for producing one group of difference output between high period.

Circuit working state is divided into two stages: precharge (Pre_charge) and evaluation (evalue), at pre-charging stage CLK, it is low level, by P3, P0, capacitor C 1 and C2 are charged to VDD, making output Q, Qn is all low level, thereby meets the working method of double track precharge logical.In evaluate phase, according to the value of input signal X, Xn, decide output signal.Transistor n6 realizes two capacitor C 1 and C2 discharge and reach the total power consumption equilibrium of circuit in evaluate phase.The pair of cross coupled inverters being comprised of n0, n1, p1, p2 is used for output data to keep.

As shown in Figure 8, circuit working schematic diagram for prime latch module, rear class latch module in the present embodiment, the node relationships of inside when Xn=1, when CLK is low level, net3, net4 are pre-charged to VDD and make to export Q and Qn for (0.0), owing to being that grid and the drain electrode of n0 and n1 between low period is all VDD at CLK, in order to meet transistor, be operated in the condition V of saturation region _dS> V _gS-V _thso the node level of net1 and net2 can not reach the full amplitude of oscillation.When CLK be between high period circuit in evaluation discharge regime, while supposing dual-rail output signal X=0, Xn=1, capacitor C 2 is discharged and is made Q end be output as 1, because the capacitor C 1 of existing of n6 pipe can be discharged to GND through n0, n6, n3 and n4, so be that between high period, net1 and net2 can be in 0 current potentials at CLK.When net1 and net2 are 0 current potential, the variation of input can not impact output, therefore the jump in potential to 0 that makes net3 jump to 1 current potential by cross-linked inverter when C2 is 0 and Qn is held, at this moment any variation of input can not affect the result of output, thereby at CLK, be to keep data stabilization between high period, from sequential chart, can be clearly seen that the anti-phase relation of input and output and between high period, there are data to keep function.Because output between clock high period has data, keep function, as long as make to input data, meet certain settling time, single dynamic latch module also has the function that data latch.

As shown in Figure 9, by in the present embodiment the electric current matching waveform that produces under two kinds of different inputs of employing dynamic latch module, by waveform, can find out that in same time section, two kinds of current waveforms almost overlap completely, therefore illustrate that the power consumption that in two kinds of situations, dynamic latch module produces is identical.

As shown in Figure 10 and Figure 11, in the present embodiment, the independent set logic of middle independent set module adopts independent reset to control and brings in realization, and in Figure 10, RESET_MOD1 realizes NOR function, RESET_MOD2 realizes NAND function, and set logic is realized by a NMOS and a PMOS pipe.When asserts signal reset is while being high, module is in SM set mode, and clock inverter can be isolated prime input with output, therefore export Q and Qn and keep difference output always.When reset is while being low, asserts signal turn-off and clock inverter turning circuit in normal evaluation state.When meanwhile, reset changes to evaluation state from set and clock signal there is certain constraints.Description according to Fig. 8 to prime latch module, rear class latch module operation principle, input signal must be before rising edge clock effectively, and evaluation state as long as guarantee asserts signal before preparing to carry out the rising edge clock of evaluation in disarmed state.Provided as shown in figure 10 the setup time-constrain that reset signal and clock signal should be satisfied, the truth table that table 2 is independent set logic.

A	An	reset	reset_n	Q	Qn
						x	x	1	0	0	1
0	1	0	1	1	0
						1	0	0	1	0	1

By analyzing, can find out that RESET_MOD1, two modules of RESET_MOD2 adopt single MOS to realize except set logic, all the other structure full symmetrics.Due to trigger SM set mode in true cryptographic algorithm just trigger is carried out to initial state and also setting time relatively short, the NMOS pipe therefore producing in SM set mode and the power consumption difference of PMOS pipe can't cause serious power consumption leakage.When the independent set module circuit structure that RESET_MOD1, RESET_MOD2 are full symmetric during in evaluation scheme, so the total power consumption that two modules of evaluate phase produce in each cycle is the same substantially.

As shown in figure 13, be the operation principle schematic diagram of TSSDDL FF of the present invention, a complete operating state of TSSDDL FF can be divided into two stages, and the first stage is pre-charging stage; Second stage is evaluate phase.At pre-charging stage CP1=1, CPn=0, prime latch module enters evaluate phase and rear class latch module is pre-charging stage, therefore at pre-charging stage output, can produce full 0 signal.At this moment the result that prime latch module can sample input is transferred to net_c and net_d (pre-charging stage); As shown in Figure 7, known to the description of prime latch module, rear class latch module, data have the function that data latch after carrying out evaluation, and therefore at CP1=1, during CPn=0, prime latch module keeps the stage in data.

Trigger can be by the data of prime latch module by clock trailing edge (CP1=1 in entering evaluate phase process; CPn=0) transmission gate of opening propagates into net_c and net_d, then by feedback loop (CP1=0; CPn=1) data are latched.At this moment prime latch module enters again pre-charging stage and transmission gate and turn-offs and make any variation of input D and Dn can not refresh the data that feedback latchs, the rear class latch module that simultaneously CPn controls enters evaluate phase (CP1=0, CPn=1) and the signal of sampling is net_c and 2 signals that keep of net_d.

Trigger set function is judged according to reset signal, works as reset1=1, reset_n=0; Set module can continue output (1.0) signal, works as reset1=0, and during reset_n=1, set module enters evaluation scheme.

Known according to above-mentioned analysis, front half clock cycle of trigger of the present invention within a clock cycle, rear class is carried out precharge prime is sampled in order to produce full 0 signal and data are latched; In rear half period, prime carry out again that precharge is used for discharging and recharging next time and rear class in evaluate phase, the current potential that the output signal of rear class latch module is ordered according to net_c and net_d changes.Therefore, trigger of the present invention can be within a clock cycle by precharge and two stage parallel work-flows of evaluation and do not need to carry out frequency multiplication.

As shown in figure 13, F in figure (Front) represents prime latch module, and B (Back) represents rear class latch module.By upper figure, can show that the result of trigger output when asserts signal is effective and input are incoherent, the fixing output of output (0.1).After asserts signal is invalid, prime latch module sample and rear class latch module in precharge, so output Q and Qn keep (0.0) pre-charge state within the cycle of F_eval, B_prec.At clock trailing edge constantly, data dissemination prime being kept by transfer tube is to the input of rear class latch module, so the sampled result that in Figure 12, the data of larger dotted line frame are prime.Within the cycle of F_prec, B_eval, prime latch module is that pre-charge state is output as (0.0), so the node voltage of net_a is 0; The node voltage of net_b is 1.Pass through foregoing description, the balanced trigger of power consumption of the present embodiment design has been realized precharge and two operating process of evaluation within a complete clock cycle, and input signal is in transitional states or the inside level of hold mode trigger is all differential state, thereby reach the balanced object of power consumption.

In the present embodiment, experimental situation adopts Hspice to simulate, and the clock cycle is 1ns, and CMOS technique is 65nm, and temperature is 125 degree, and supply voltage is 1.2v; And all spice_modle simulate in SS situation.Data are by 100 ns of simulation and according to feature simulation 0-1 saltus step, 1-0 saltus step, 0-0 saltus step and these four kinds of situations of 1-1 saltus step of trigger input, as shown in figure 14, for TLSSDDL of the present invention carries out the current waveform of precharge and evaluate operation in same period.

In sum, the present invention has utilized three stage structure to realize the parallel work-flow of precharge and evaluation, but in the present invention, prime, rear class latch module only need single clock to control, so circuit structure is simpler with respect to prime, the rear class module of TDPL.Meanwhile, in the present invention, trigger has been added to set function, and intermediate circuit adopts symmetrical structure to realize completely, trigger can not cause the leakage of any power consumption difference in evaluate phase like this.Referring to electric current matching waveform under the given four kinds of different input conditions of Figure 14, can find out in precharge and the almost matching completely of four kinds of waveforms of evaluate phase.

Below be only the preferred embodiment of the present invention, protection scope of the present invention is also not only confined to above-described embodiment, and all technical schemes belonging under thinking of the present invention all belong to protection scope of the present invention.It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principles of the present invention, should be considered as protection scope of the present invention.

Claims (3)

1. with the balanced trigger of power consumption of zero clearing set port, it is characterized in that, comprise by prime latch module connected in series, intermediate circuit and rear class latch module, three modules are all usingd differential signal as input, the output of generation difference; Described prime latch module and rear class latch module all adopt the dynamic difference circuit of single clock control; Independent set module, data isolation module and data memory module in the middle of described intermediate circuit comprises, the independent set module in described centre is carried out initial state setting by independent asserts signal to trigger, described data isolation module comprises that two groups of clock transmission gates isolate evaluation signal and asserts signal, and described data memory module comprises that pair of cross coupled inverters carries out data storage; Half period before clock, described prime latch module is carried out evaluation, rear class latch module is carried out pre-charge state; In the later half cycle of clock, described prime latch module is carried out pre-charge state, rear class latch module is carried out evaluation output, realizes the parallel work-flow of three modules in one-period.

2. the balanced trigger of the power consumption with zero clearing set port according to claim 1, is characterized in that, described prime latch module and rear class latch module all adopt SABL dynamic difference structure and have data latch function.

3. the balanced trigger of the power consumption with zero clearing set port according to claim 1, it is characterized in that the inverter with single-ended control signal that the independent set module in described centre comprises realizing a PMOS of set function and a NMOS and is used for realizing data inverter functionality.