KR101788712B1 - Extendable BCD-excess 3 code converter using quantum-dot cellular automata - Google Patents

Abstract

The present invention relates to a QCA BCD-3 code converter. The QCA BCD-3 code converter according to the present invention is connected to first to fourth wirings and second to fourth wirings to which the first to fourth input signals are respectively inputted, A second combinational logic cell connected to the output cell of the first combinational logic cell and performing a logical sum gate function to output a first output signal, and a third combinational logic cell connected to the third and fourth wirings, A third combinational logic cell performing a gate function, a fourth combinational logic cell coupled to an output cell of the second and third combinational logic cells for performing an exclusive OR gate function to output a second output signal, A fifth combinational logic cell connected to the fourth wiring and performing an exclusive OR gate function and a sixth combinational logic circuit connected to an output cell of the fifth combinational logic cell to perform a logic negation function to output a third output signal, Cell, and the fourth wire. And performs the logical negation function, including a seventh gate combination logic cell that outputs a fourth output signal. According to the present invention, it is possible to provide a BCD-3 code converter having an expandable structure using a quantum dot cellular automata.

Description

Extensive BCD-excess 3 code converter using quantum-dot cellular automata

The present invention relates to a QCA BCD-3 code converter, and more particularly to a QCA BCD-3 code converter with an expandable structure using a quantum point cellular automata.

Scaling CMOS devices has sought aggressive development, such as reducing transistor size and reducing power consumption, but has caused problems such as current leakage and increased power density. Quantum-dot cellular automata (QCA), a new technology that can replace this problem, is a molecular or atomic nano-sized device that consumes extremely low power and is emerging in the next generation of electronic circuit design.

Since the basic operations of the QCA cell were implemented in hardware in the late 1980s, various circuits ranging from simple logic circuits such as adders to large scale integrated circuits such as microprocessors have been proposed.

Tougaw and Lent first designed a QCA-type single-bit adder with two inputs A, B, and Carry Cin as input, and the result Sum is M [M (A ', B, Cin) ', Cin), and M (A, B, Cin').

Here, A ', B', and Cin 'are complement of A, B, and Cin, respectively, which are implemented by an inverter, and M () represents a majority voting gate. Similarly, the carry value Cout is output as M (A, B, Cin), including five majority gate and three inverters, and a total of 192 cells are required.

Wang et al. Designed a pre-QCA adder with 145 cells by generating Sum as M (Cout ', Cin, M (A, B, Cin')). Fijany et al. Proposed a bit serial adder that modified the previous adder to include a feedback connection between Cout and Cin. A carry look ahead adder and a microprocessor have been proposed that connect the carry output to the carry input of the next stage adder in advance.

A subtracter can represent a negative number using 2's complement or 1's complement, and uses an adder and a subtracter together. In adder and subtracter, it is necessary to change to decimal method after binary operation. There are many kinds of code converters used at this time, and among them, BCD (binary coded decimal) codes are used most frequently. The BCD code is convenient to convert decimal numbers to binary numbers, but it does not perform a conservative conversion for subtraction operations and requires efficient management of data.

The improved BCD-3 over code is a type of BCD code, in which 3 is added to the corresponding number, which is represented by a 4-bit binary number. Each code value 1 is 0, 0 is 1, and if it is complemented, it becomes 9's complement on the decimal number, and it is called self complement code. The BCD-3 over code can compensate for the shortcomings of BCD using the complement conversion, and the data conversion is fast.

However, since the BCD-3 code converter designed on the existing QCA does not consider the scalability, it is not suitable for large-scale circuit design.

Therefore, it is necessary to consider a BCD-3 code converter with a scalable structure that can be used for large-scale circuit design.

Accordingly, it is an object of the present invention to provide a QCA BCD-3 code converter with an expandable structure using a quantum point cellular automata.

In order to achieve the above object, a QCA BCD-3 code converter according to the present invention comprises first to fourth wirings, each of which is composed of rotated cells and to which first to fourth input signals are input, A second combinational logic cell coupled to the output cells of the first combinational logic cell and the first combinational logic cell to perform a logical sum gate function to output a first output signal, A third combinational logic cell connected to the third and fourth wirings for performing a function of an OR gate and an output cell of the second combinational logic cell and performing an exclusive OR gate function A fifth combinational logic cell coupled to the third and fourth wirings for performing an exclusive OR gate function, a fourth combinational logic cell coupled to the output cells of the fifth combinational logic cell, , A logic unit Connected to claim 6 in combination with the logic cell, and the fourth wiring and outputting a third output signal by performing a gate function, by performing logical negation gate features a seventh combinational logic cell and outputting a fourth output signal.

Wherein the first to fourth wirings are made of rotated cells, the second wirings are arranged substantially parallel to the first wirings, and the third wirings are arranged substantially parallel to the first and second wirings , And the fourth wiring may be arranged substantially parallel to the first, second, and third wirings.

In addition, the first to seventh combinational logic cells and the first to fourth wirings may be connected in an extended crossing manner through wiring composed of general cells.

In order to achieve the above object, the present invention can provide a quantum dot cellular automata device including the QCA BCD-3 code converter.

According to the present invention, it is possible to provide a BCD-3 code converter having an expandable structure using a quantum dot cellular automata. The BCD-3 code converter according to the present invention agrees with the directions of the input and output in consideration of the expandability of the circuit, and the clocks of the output values are synchronized with each other to provide high spatial efficiency. Therefore, the BCD-3 code converter according to the present invention can be efficiently utilized for various devices using the quantum dot cellular automata.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a drawing referred to for describing a quantum dot cellular automata,
2 is a diagram showing a wiring crossing method on the same plane,
Figure 3 shows an enlarged cross section,
Figure 4 shows the simulation results of the extended intersection of Figure 3,
5 is a diagram showing a configuration of a logic combination cell capable of performing a 5-input majority gate function;
FIG. 6 is a diagram showing a simulation result for the logic combination cell shown in FIG. 5,
7 is a logic diagram of a general BCD-3 over-code converter,
8 is a diagram illustrating a structure of a general BCD-3 excess converter designed on QCA,
9 is a logic diagram of a BCD-3 excess converter using URG (Universal Reversible Logic Gate) and FG (Feynman gate) gates,
10 is a logic diagram of a QCA BCD-3 over-code converter in accordance with an embodiment of the present invention.
11 is a diagram illustrating a structure of a QCA BCD-3 code converter according to an embodiment of the present invention, and FIG.
12 is a diagram showing a simulation result of the QCA BCD-3 code converter shown in FIG.

Hereinafter, the present invention will be described in detail with reference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a diagram referred to illustrate a quantum point cellular automata.

As shown in Fig. 1 (a), a quantum cell is composed of four quantum dots, and has two transient electrons that can be tunneled between quantum dots. Due to the Coulomb repulsion, these transitional electrons are always located in the opposite quantum dots in the diagonal direction. A quantum cell has two types of polarization with equivalent energy, which can be represented by +1 (1) and -1 (0).

Fig. 1 (a) shows a basic cell structure, and Fig. 1 (b) shows a cell rotated by 45 degrees. In the following description, a cell having a basic cell structure is referred to as a 'general cell', and a cell rotated by 45 ° is referred to as a 'rotated cell'.

1 (c) shows a wiring in which cells are arranged.

In the case of a wiring made up of general cells, when a signal is input, it propagates in the same polarized state due to the Coulomb repulsion of electrons between adjacent cells. However, in the case of a wiring composed of rotated cells, a signal having a polarization opposite to that of an adjacent cell is propagated.

2 shows a wiring crossing method on the same plane.

Referring to FIG. 2, there is an intersection of a normal cell and a rotated cell on the same plane, and two wires using a normal cell and a rotated cell can correctly propagate a signal without affecting each other.

Figure 3 shows the extended intersection, and Figure 4 shows the simulation result of the extended intersection.

Referring to FIG. 3, the extended intersection structure allows a signal to pass vertically through a wiring using general cells to two different quantum dot directions, that is, wiring using a rotated cell, It is a design structure. Such an extended intersection structure can be applied to a circuit design in which an input signal is sent in various directions to receive one or more input signals for each output.

In the extended intersection structure, if the same clock is assigned to the cell wirings arranged horizontally and the cell wirings arranged vertically, it is necessary to design the clocks at different clock stages because the signal flow is disturbed.

Referring to FIG. 4, the simulation results of the extended intersection show that inputs A and B are output as outputs A 'and B'. That is, the input signal A is output as the output signal A 'through the horizontal wiring line, and the input signal B is also output as the output signal B'.

FIG. 5 shows a configuration of a logic combination cell capable of performing a 5-input majority-gate function, and FIG. 6 shows a simulation result of the logic combination cell shown in FIG.

Referring to FIG. 5, the values a, b and c derived by the majority function ab + ac + bc are output to F through d, e and a majority function. Inputs a to e are the same clock, and output F changes to the next clock phase.

Therefore, a total of two clock steps are required until the five variables are output through the majority function, which is the same as the clock phase consumed by the three-input majority gate.

Basically, the majority gate has three input cells and one output cell F, and the polarization of the cell in the center is determined according to the polarization of the input cells, and the polarization is influenced by the output cell to propagate the signal .

Referring to FIG. 6, the simulation result shows a value outputted as F by the majority function of the inputs a, b, c, d, and e.

In the QCA BCD-3 code converter according to the present invention, the above-mentioned extended intersection method and the 5-input majority gate are used to efficiently design the BCD-3 code conversion device on the QCA.

On the other hand, the BCD-3 excess code represents a result obtained by adding 3 to the BCD-code as a 4-bit binary number. In the 4-bit code combination used in the BCD code, the result obtained by adding 3 is used only to 10 (0011 ~ 1100) which does not exceed the usage range of the BCD, and the rest is invalidated. The BCD code and the BCD-3 excess code are shown in [Table 1].

Decimal

BCD
Excess-3
0

0000
0011
One

0001
0100
2

0010
0101
3

0011
0110
4
0100

0111
5
0101

1000
6
0110

1001
7
0111

1010
8
1000

1011
9
1001

1100

Figure 7 is a logic diagram of a general BCD-3 over-code converter.

Referring to FIG. 7, four AND gates, four OR gates, and three NOT gates are used. It is required to pass through at most three gates until the input signal is outputted, so that the structure is relatively complicated.

8 is a diagram showing the structure of a general BCD-3 excess converter designed on QCA.

The structure shown in FIG. 8 does not consider the scalability because the input and output values are in different directions and the input value starts from the inside. Also, since four output values are different in clock phase, the four output values are not output in the same clock phase.

9 is a logic diagram of a BCD-3 excess converter using URG (Universal Reversible Logic Gate) and FG (Feynman gate) gates.

The BCD-3 code converter shown in FIG. 9 is designed as a reversible circuit, but since it is not implemented in the current QCA designer, it is hardly reversible. One digital logic circuit is used for one URG gate, and one digital logic circuit is used for one FG gate. If this logic diagram is implemented in QCA, a minimum of 8 majority gate is used per URG gate. Also, there are 12 unused outputs in the output value, which is not efficient.

10 is a logic diagram of a QCA BCD-3 over-code converter in accordance with an embodiment of the present invention.

Referring to FIG. 10, the number of logic gates required is smaller than that of the conventional converter by using an XOR logic gate and a 5-input majority gate, unlike the logic of a general BCD-3 excess circuit.

Compared with the general logic shown in FIG. 7, a total of seven gates are used, that is, two OR gates, two XOR gates, two inverters, and one five-input majority gate, The number is four. In addition, the 5-input majority gate can simplify the existing 3-level circuit into a 2-level circuit, and since each input value is directly connected to the output value through the 5-input majority gate, .

11 is a diagram illustrating the structure of a QCA BCD-3 code converter according to an exemplary embodiment of the present invention.

11, the QCA BCD-3 code converter 100 includes first to fourth wirings 111, 113, 115 and 117, a fifth wiring 123, and first to sixth combinational logic cells 120, 130, 140, 150, 160, 170).

When the first to fourth wirings 111, 113, 115, and 117 are made of rotated cells, input signals A, B, C, and D are input, respectively. The first to fourth wirings 111, 113, 115, and 117 are arranged in parallel with each other.

The first combinational logic cell 120 is connected to the second wiring 113, the third wiring 115 and the fourth wiring 117 in an extended intersection manner to perform a majority gate function.

The fixed values -1 and 1 for the input of the 5-input majority gate are used to perform the AND and OR operations, respectively. The inputs a, b, and c are output first through the majority function, To a fixed polarized value cell and perform an AND operation and an OR operation. In the same way, one of the inputs d and e can be changed into a fixed polarized value cell, and two logical operations can be performed with one 5-input majority gate.

The second combinational logic cell 130 is connected to the output cell of the first combinational logic cell 120 and the first combinational logic cell 120 and performs a logical sum gate function to output a W output signal. The second combinational logic cell 130 is connected to the first interconnect 111 in an extended cross-over manner.

The third combinational logic cell 140 is connected to the third wiring 115 and the fourth wiring 117 in an extended intersection manner to perform an OR gate function.

The fourth combinational logic cell 150 is connected to the second wirings 113 in an extended intersection manner and is connected to the output cells of the third combinational logic cell 140 to perform an exclusive OR gate function, And outputs a signal.

The fifth combinational logic cell 160 is connected to the third wiring 115 and the fourth wiring 117 in an extended intersection manner to perform an exclusive OR gate function.

The sixth combinational logic cell 170 is coupled to the output cells of the fifth combinational logic cell 160 to perform a logic negation gate function and output a Y output signal. The sixth combinational logic cell 170 can perform an inverter function in which the polarity of the input signal and the output signal is opposite to each other and the signal propagates.

The fifth wiring 123 is connected to the fourth wiring 117 through the connection cell 122, inverts the input signal D, and outputs a Z output signal. The fifth wiring 123 is made of a general cell and arranged at a right angle to the third wiring 115. [

In such a configuration, the output signal can be expressed by the algebraic expression as follows.

In the case of the output signal W, the 5-input majority gate function of the first combinational logic cell 120 can be used to perform an OR operation on C and D, and the result is ANDed with B. In the case of a 5-input majority gate, the clock stages of the nine internal cells are divided to distinguish the operation sequence. That is, one clock phase of the operation of C and D is given, and the next clock phase of the clock phase of C and D is given in the operation of the next B, so that the order of the two operations is sequentially progressed.

The other output signal is implemented using an XOR logic gate. Because the input variable is used twice in an operation expression such as XOR, it is inefficient to represent it by a 5-input majority gate.

The output signals X and Y can be output in two cycles using an efficient XOR gate. The output signal X can output the result by XORing B with the result of the OR operation of C and D. The output signal Y performs an XOR operation on C and D and then performs an inverter on the value to output a value. The output signal Z performs an inverter on the value of the input signal D and outputs a result value.

The extended intersection using the rotated cell wiring is designed by giving the next clock step to each output so that the intensity of the signal is influenced by the wiring length, so that it does not interfere with the flow. Since the maximum number of wiring cells is 28 signals for normal cells and 27 for rotating cell wires, signals are normally propagated. It is necessary to design it not to exceed this limit.

With such a configuration, the QCA BCD-3 code converter 100 designs the input and output directions constantly using the extended intersection structure in consideration of expandability, and changes the output values to appear on the same clock . In addition, all outputs are performed within 8 clocks, and the length of the output wiring is designed to match. In the case of the general structure, the positions of the input / output values are sometimes located inside the circuit, and the flow of the input and output is not constant. The output signal W is designed using one 5-input majority gate and one 3-input majority gate. Since the number of input variables is large and the variable for one input is used once in each operation expression, Can be used to reduce the number of logic gates and clock stages.

12 shows a simulation result of the QCA BCD-3 code converter shown in FIG.

Referring to FIG. 12, when the upper ABCD value is input, the lower value WXYZ is output, and the output value for the first input is output after 2 cycles. Therefore, the output starts from the underlined value in the output portion to the right.

The following Tables 2 and 3 illustrate the BCD-3 over-code converter based on the converter and URG gate according to the present invention and the BCD-3 over-code converter (YW You and JC Jeon, "Efficient design of BCD-excess 3 code converter using quantum-dot cellular automata," Journal of Korea Navigation Institute , Vol. 17, No. 6, pp. 700-704, 2013).

The BCD-3 excess converter < RTI ID = 0.0 >

URG BCD-3 excess converter
Number of Gates

11
43
Number of garbage values

0
12
Percentage of free space

67%
74%

The BCD-3 excess converter < RTI ID = 0.0 >
YW You et al. Proposed a BCD-3 code converter

Output Clock Phase Count

8
8
Number of clock steps required for inter-circuit connections
One
7

In Table 2, even when the number of gates in the URG gate is minimized, there are many differences from the BCD-3 code converter according to the present invention. The circuit designed with the URG gate has a large circuit size due to the large number of inputs and outputs of the URG gate itself, but the efficiency is very low because more than half of the output value is the waste output.

In Table 3, although the BCD-3 code converter according to the present invention has more cells and majority gates than the BCD-3 code converter proposed by YW You et al., But the clocks of the four output values are all the same and the space efficiency Higher. Space efficiency is a measure of the percentage of cells used in the overall size of a circuit and is important in the design of the circuit. The number of output clocks is a comparison of the clocks between the output values. If the clocks of the output values are not the same, values exceeding 3 in the input are not output at the same time.

In the BCD-3 code converter according to the present invention, all four outputs are equal to 8 clocks. However, the BCD-3 code converter proposed by YW You et al. Has a maximum output value of 8 clocks, Since the positions of input and output values are irregular, additional clock and wiring are required to consider the scalability. In other words, Y. W. You et al. Proposed a code converter over BCD-3 that has a clock difference of 7 between the maximum output value and the minimum output value, and requires an additional 7 clocks to synchronize the output value clock.

In the present invention, the BCD-3 code converter structure coincides with the directions of the input and output in consideration of the expandability of the circuit, the output clocks are synchronized equally, and compatibility and efficiency are higher. Therefore, the BCD-3 code converter according to the present invention can be efficiently utilized for various devices using the quantum dot cellular automata.

Meanwhile, the QCA BCD-3 code converter according to the present invention is not limited to the configuration and method of the embodiments described above, but the embodiments can be applied to all of the embodiments Or some of them may be selectively combined.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present invention.

Claims (6)

First to fourth wirings into which the first to fourth input signals are input, respectively;
A first combinational logic cell coupled to the second to fourth wirings to perform a majority gate function;
A second combinational logic cell coupled to the output cell of the first combinational logic cell and the first combinational logic cell to perform a logical sum gate function to output a first output signal;
A third combinational logic cell coupled to the third and fourth wirings to perform an OR gate function;
A fourth combinational logic cell coupled to the output of the second combinational logic cell and the output of the third combinational logic cell to perform an exclusive OR gate function to output a second output signal;
A fifth combinational logic cell coupled to the third and fourth wirings to perform an exclusive OR gate function;
A sixth combinational logic cell coupled to an output cell of the fifth combinatorial logic cell to perform a logic negated gate function to output a third output signal; And
And a fifth wire connected to the fourth wire so as to transmit a signal obtained by inverting the fourth input signal, and outputting a fourth output signal. The method according to claim 1,
The first to fourth wires are made of rotated cells,
The second wiring is arranged in parallel with the first wiring,
The third wiring is arranged in parallel with the first and second wirings,
And the fourth wiring is arranged in parallel with the first to third wirings. 3. The method of claim 2,
Wherein the first to sixth combinational logic cells and the first to fourth wirings are connected in an extended crossing manner through wiring made up of general cells. The method according to claim 1,
Wherein the first combinational logic cell is a 5-input majority-gate structure with two fixed inputs. The method according to claim 1,
Wherein the fifth wiring is made of a general cell and is arranged at right angles to the fourth wiring. A quantum-point cellular automata device comprising the QCA BCD-3 over-code transducer of any one of claims 1 to 5.

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