KR20220117990A - QCA multiplexer using majority function-based NAND for quantum computing - Google Patents

Abstract

The present invention relates to a QCA multiplexer using a NAND gate based on a majority voting function. The QCA multiplexer according to the present invention includes: a first combinational logic cell to which a signal obtained by a first input signal and a selection signal is input and performs an AND gate function; a second combinational logic cell receiving a second input signal and a selection signal and performing an AND gate function; a third combinational logic cell receiving a signal obtained by inverting the output signal of the first combinational logic cell and an inverted signal of the output signal of the second combinational logic cell, and performing an AND gate function; and a fourth combinational logic cell that performs an inverter function and outputs a signal obtained by inverting the output signal of the third combinational logic cell as a final output signal. According to the present invention, it is possible to provide a QCA multiplexer having a structure with reduced time and space complexity and high energy efficiency based on a NAND gate.

Description

QCA multiplexer using majority function-based NAND for quantum computing in a quantum computing environment

The present invention relates to a quantum dot cellular automata (QCA) multiplexer using a NAND gate based on a majority vote function in a quantum computing environment.

Quantum-dot Cellular Automata (QCA), replacing complementary metal oxide semiconductor (CMOS) technology, is being considered as the future nanotechnology for high-performance integrated circuits. QCA has the potential advantage of implementing nanoscale circuits with high-speed operation, making it more attractive due to its low-power consumption capabilities. The performance of a QCA device is determined not only by the magnitude of the current or the associated voltage, but also by the composition of the charge according to the arrangement of the constituent cells.

Various digital logic devices have been designed using QCA over the years, but the input to these logic elements has always been limited due to the device's energy source. This problem was solved by using a clock control system that minimizes energy consumption and can use a pipeline structure, and then various combinations and sequential circuits based on the clock control system have been developed.

On the other hand, a multiplexer (multiplexer) plays an important logic device in the design of a digital logic circuit. In addition, the NAND gate is a general-purpose gate that is the most essential component in any circuit design, and circuit design is possible using only NAND gates. If only NAND gates are used, the number of logic required can be increased, but circuit design and manufacturing can be simplified.

Therefore, it is necessary to consider a method of implementing a QCA multiplexer having a structure with high energy efficiency and reducing complexity in time and space based on a NAND gate. Also, it is necessary to consider a method of designing a QCA arithmetic logic device capable of performing various operations by utilizing such a QCA multiplexer.

Accordingly, an object of the present invention is to provide a QCA multiplexer having a structure that reduces time and space complexity and has a high energy efficiency based on a NAND gate, and a QCA arithmetic logic device using the QCA multiplexer.

In the QCA multiplexer according to the present invention for achieving the above object, a signal obtained by inverting a first input signal and a selection signal is input, a first combination logic cell performing an AND gate function, a second input signal and the selection signal is input, a second combinational logic cell performing a logical product gate function, a signal obtained by inverting the output signal of the first combinational logic cell, and a signal obtained by inverting the output signal of the second combinational logic cell are input; a third combinational logic cell performing a multiplication gate function, and a fourth combinational logic cell performing an inverter function to output a signal obtained by inverting the output signal of the third combinational logic cell as a final output signal.

The first to third combinational logic cells are combinational logic cells in which one of the inputs of the 3-input majority vote gate is fixed to a value corresponding to logic bit 0, and the fourth combinational logic cell is the third combinational logic cell. It may consist of two cells which are diagonally arranged adjacent to the output cell.

A QCA multiplexer according to the present invention for achieving the above object, a first QCA two-to-one multiplexer for outputting any one of the first and second input signals as a first output signal according to a first selection signal, the first A second QCA 2-to-1 multiplexer that outputs any one of the third and fourth input signals as a second output signal according to a selection signal, and any one of the first and second output signals according to a second selection signal and a third QCA 2 to 1 multiplexer that outputs

In order to achieve the above object, the present invention may provide a QCA arithmetic logic device for selecting an arithmetic operation to be performed using the QCA multiplexer.

And, in order to achieve the above object, in the present invention, it is possible to provide a quantum dot cellular automata device including the QCA multiplexer.

According to the present invention, it is possible to provide a QCA multiplexer having a structure with high energy efficiency and reducing complexity in time and space based on a NAND gate. In addition, it is possible to provide a QCA arithmetic logic device capable of performing various operations by utilizing this QCA multiplexer. In addition, the QCA multiplexer according to the present invention can be efficiently used in various devices using quantum dot cellular automata.

1 is a diagram referenced to describe a quantum dot cellular automata;
2 is a diagram referenced in the description of various combinational logic cells;
3 is a diagram illustrating a QCA clock having four clock steps;
4 is a block diagram of a typical 2-to-1 multiplexer;
5 is a block diagram of a QCA 2 to 1 multiplexer according to an embodiment of the present invention;
6 is a diagram showing the structure of a QCA 2 to 1 multiplexer according to an embodiment of the present invention;
7 is a diagram showing the structure of a QCA 4 to 1 multiplexer according to an embodiment of the present invention;
8 is a block diagram of a QCA arithmetic logic device according to an embodiment of the present invention;
9 is a diagram showing an example of a QCA full adder used in the present invention;
10 is a diagram showing the structure of a QCA arithmetic logic device according to an embodiment of the present invention;
11 is a view showing a simulation result of the QCA 2 to 1 multiplexer shown in FIG. 6;
12 is a table showing the results of comparing the QCA 2 to 1 multiplexer according to the present invention and another QCA 2 to 1 multiplexer;
13 is a table showing the results of comparing the QCA 4 to 1 multiplexer according to the present invention and another QCA 4 to 1 multiplexer;
14 is a view showing a simulation result of the QCA 4 to 1 multiplexer shown in FIG. 7;
15 is a diagram showing a power dissipation map of a QCA 2 to 1 multiplexer and another QCA multiplexer according to the present invention;
16 is a table showing power loss analysis of the QCA 2-to-1 multiplexer and another QCA multiplexer according to the present invention.

In this specification, when a component is referred to as being “connected” or “connected” to another component, the component may be directly connected or connected to another component, but another component in between. It should be understood that elements may exist. Also, other expressions describing the relationship between elements, such as "between" or "neighboring", etc., such as that one element "transmits" a signal to another element, should be interpreted similarly. do.

Hereinafter, the present invention will be described in more detail with reference to the drawings.

1 is a diagram referenced to describe a quantum dot cellular automata.

Quantum-dot Cellular Automata (QCA) is a next-generation technology that represents a logical state not as a voltage state but as a pair of electronic states in the cell. It has the advantage of high device density of about 1012 devices/cm2.

Referring to FIG. 1 , a QCA cell is usually composed of four quantum dots, and has two transient electrons capable of tunneling between the quantum dots. Because of the coulombic repulsion, these electrons tend to be located within the diagonally opposite quantum dots, and the high potential barrier between each pair of quantum dots causes the electrons to split into individual points.

Additional quantum dots can be added to the center of the cell, but generally a cell with four quantum dots is used to simplify the structure. Electrons are known to exert a driving force due to their kink energy, while other electrons pass through the tunneling barrier and relocate to the corresponding diagonal quantum dots.

The QCA cell has two types of polarizations having energy equivalent, and this can be expressed as P=-1 polarization corresponding to 0 of the logic bit or P=+1 polarization corresponding to 1 of the logic bit.

2 is a diagram referenced in the description of various QCA combinational logic cells.

Figure 2 (a) shows a basic QCA wire (QCA wire), it can be designed by continuously arranging cells. In such QCA wiring, binary information can be transmitted by neighboring cell interactions along QCA cell lines in the input-to-output direction.

2(b)(c) shows the configuration of a combinational logic cell performing an inverter function. When the QCA cells are arranged diagonally, the direction of the excess electrons is changed by the Coulomb repulsion force, and an inverted value can be output to the input value.

FIG. 2(b) shows a more powerful inverter that has a stronger logical structure and outputs a stable value than that shown in FIG. 2(c). In the case of (c) of FIG. 2 , an inverter that is weaker than the inverter shown in (b) of FIG. 2 but can be configured simply is shown.

2(d)(e) shows the configuration and block diagram of a combinational logic cell performing a majority vote gate (MG) function.

The majority vote gate provides a function of outputting 1 when the number of 1's is greater than 0 among input signals, and outputting 0 when the number of 0's is greater than 1 among input signals. The following [Equation 1] shows the logic of the majority gate.

The basic logic gates, AND gates and OR gates, can be constructed using three-input majority vote gates. That is, as shown in the following equation, an AND gate can be made by fixing one of three inputs to 0, and an OR gate can be made by fixing one of three inputs to 1.

3 shows a QCA clock having four clock steps.

The QCA circuit uses a clock system to synchronize and manage data transfers. In other words, since the electrons in a quantum dot require high potential energy to tunnel through the junction, clocking plays a very important role in the synchronization and flow of information along a specific direction. The main advantage of the QCA clock system is that the quantum cell does not require an external power supply, so it can power the circuit.

As shown in FIG. 3 , the clock is composed of four stages of a switch, a hold, a release, and a relax, and can be manipulated according to the activation of the former.

During the switch phase, the barrier corresponding to a dot in the inactive cell gradually increases, and in the hold phase, in a state where the barrier corresponding to the dot is increased, the corresponding values 0 and 1 are encoded to prevent tunneling of electrons. The release phase means a state in which the barrier is gradually lowered, and the relaxation phase means a state in which the barrier is lowered and electron tunneling is promoted.

4 is a block diagram of a typical 2-to-1 multiplexer.

A multiplexer is a combination circuit that selects and outputs one value from a series of input values, and is an important component in various parts such as signal control and memory input/output in a digital logic circuit.

As shown in Fig. 4, the 2 to 1 multiplexer can be composed of two AND gates and one OR gate, and the output value of the multiplexer is determined using the inputs A and B and the selection value S as shown in the following equation. .

The following [Table 1] shows the truth table of the 2-to-1 multiplexer.

S
A
B
F
0
0
0
0
0
0
One
0
0
One
0
One
0
One
One
One
One
0
0
0
One
0
One
One
One
One
0
0
One
One
One
One

5 is a block diagram of a two-to-one multiplexer according to an embodiment of the present invention.

The QCA 2-to-1 multiplexer according to the present invention can be configured based on a QCA NAND gate. NAND gates are general-purpose gates, and any circuit can be designed using only NAND gates. Using only NAND gates increases the number of logic required, but can simplify the design and manufacture of the circuit.

Using De Morgan's law, [Equation 4] can be expressed as follows.

When [Equation 5] is applied, as shown in FIG. 5, a 2-to-1 multiplexer can be configured using only NAND gates. If the selection value S is 0, the value of A is output, and the value of the selection value S is If it is 1, the value of B is output.

6 shows the structure of a QCA 2 to 1 multiplexer according to an embodiment of the present invention.

Referring to FIG. 6 , the QCA 2-to-1 multiplexer 100 includes first to third combinational logic cells 110 , 120 , and 130 performing an AND gate function. And, functionally, it has a structure in which three inverters are used, and as a result, it can be seen that it is composed of only NAND gates.

The cell to which the selection signal S is input is disposed diagonally adjacent to the input cell of the first combinational logic cell 110 and vertically adjacent to the input cell of the second combinational logic cell 120, so that the first combination A signal obtained by inverting the input signal A and the selection signal S is input to the logic cell 110 , and the input signal B and the selection signal S are input to the second combination logic cell 120 .

In addition, the output cell of the first combinational logic cell 110 is disposed adjacent to the diagonal direction of the first cell 133 vertically adjacent to the input cell of the third combinational logic cell 130, the second combination logic cell ( As the output cell of 120 is disposed diagonally adjacent to the input cell of the third combinational logic cell 130 , the third combinational logic cell 130 passes through the first cell 130 to the first combinational logic cell ( An inverted signal of the output signal of 110) is input, and a signal obtained by inverting the output signal of the second combinational logic cell 120 is also input.

The second and third cells 135 and 137 perform an inverter function, and the output signal of the third combinational logic cell 130 is inverted by the second and third cells 135 and 137 to obtain the final output signal F. print out

With this configuration, when the selection signal S is 0, the value of the input signal A is output as the final output signal, and when the selection signal S is 1, the value of the input signal B is output as the final output signal.

7 shows the structure of a QCA 4 to 1 multiplexer according to an embodiment of the present invention.

Referring to FIG. 7 , the QCA 4-to-1 multiplexer 200 uses three QCA 2-to-1 multiplexers 100a, 100b, and 100c.

Here, S1 and S0 represent the selection signal, and A, B, C, and D represent the input signal. Therefore, if the combination of S1 and S0 is 00, the value of the input signal A is output, and the combination of S1 and S0 is If it is 01, the value of the input signal B is output. Similarly, when the combination of S1 and S0 is 10, the value of the input signal C is output, and when the combination of S1 and S0 is 11, the value of the input signal D is output

Using the same method as this, a QCA n-to-one multiplexer for an arbitrary natural number n can be designed.

This QCA 4:1 multiplexer 200 uses 79 QCA cells and has a structure superior to the existing multiplexer in terms of space efficiency.

8 is a block diagram of a QCA arithmetic logic device according to an embodiment of the present invention.

As shown in FIG. 8 , an arithmetic logic unit (ALU) may include a multiplexer and a full adder.

Arithmetic logic devices are combinatorial logic devices capable of performing basic arithmetic and logical micro-operations. The arithmetic logic unit can use the selection lines decoded by the arithmetic logic unit to determine the type of operation to be performed, and can specify up to 2 ^k different operations based on the k selection lines. At each step the inputs to the multiplexer are denoted 0, B, B', 1 and the corresponding selection values S1 S0, 00, 01, 10 and 11.

The parallel adder consists of four full adder circuits, and the carry into the first stage is the carry input Cin. The remaining carry is connected internally between successive steps. The optional variables are S1, S0 and Cin, where S1 and S0 control all inputs Y to the adder according to their ratio. If Cin is 1, A + Y always increases by 1.

9 shows an example of a QCA full adder used in the present invention.

A full adder is widely used in the construction of arithmetic circuits. A 1-bit full adder has three inputs (A, B, C _in ) and two outputs (Sum, C _out ).

10 shows the structure of a QCA arithmetic logic device according to an embodiment of the present invention.

Referring to FIG. 10 , the QCA arithmetic logic device 300 may be configured based on the QCA multiplexer 100 shown in FIG. 6 .

That is, the QCA arithmetic logic device 300 may be configured using four QCA two-to-one multiplexers 100a, 100b, 100c, 100d and four QCA full adders 150a, 150b, 150c, 150d.

By configuring the cell to which the selection signals S0 and S1 are input as the rotated cell, the same value can be transmitted to the four QCA 2-to-1 multiplexers 100a, 100b, 100c, and 100d.

Eight arithmetic operations determined by S1, S0, and Cin are shown in Table 2 below.

S1
S0
Cin
Function
Operation
0
0
0
G=A
Transfer A
0
0
One
G=A+1
Increment A
0
One
0
G=A+B
Add
0
One
One
G=A+B+1
Add with carry
One
0
0
G=A+B'
Subtract with borrow
One
0
One
G=A+B`+1
Subtract
One
One
0
G=A-1
Decrement A
One
One
One
G=A
Transfer A

The operation G = A appears twice here, which is not a problem, but a by-product of implementing the instruction to increment and decrement by one using Cin as the control variable.

FIG. 11 is a diagram illustrating simulation results of the QCA 2-to-1 multiplexer shown in FIG. 6 .

11, the QCA 2 to 1 multiplexer 100 and the following simulations according to the present invention can be performed using the QCADesigner 2.0.3 tool.

The QCA 2-to-1 multiplexer 100 uses a total of 19 cells, and the surface area can be implemented as 15,786 nm2.

12 is a comparison of the QCA 2 to 1 multiplexer 100 according to the present invention and the QCA 2 to 1 multiplexer according to the previous design, and FIG. 13 is the QCA 4 to 1 multiplexer 200 according to the present invention and the previous design. This is a comparison and summary of QCA 4 to 1 multiplexers.

12 and 13, [19] is a QCA multiplexer proposed by Mardiris VA, et al. (Mardiris VA, Karafyllidis IG (2010) Design and simulation of modular 2 to 1 quantum-dot cellular automata (QCA) multiplexers. Int J Circuit Theory Appl 38:771-785), [20] is a QCA multiplexer proposed by Mukhopadhyay D et al. (Mukhopadhyay D, Dinda S, Dutta P (2011) Designing and implementation of quantum cellular automata 2:1 multiplexer circuit. Int J Comput Appl Technol 25: 21-24) and [21] are the QCA multiplexers proposed by Hashemi S et al. (Hashemi S, Navi K (2012) New robust QCA D flip flop and memory structures. Microelectron J43:929-940), and [22] are presented by Roohi A et al. (Roohi A, Khademolhosseini H, Sayedsalehi S, Navi K (2011) A novel architecture for quantumdot cellular automata multiplexer. Int J Comput Sci 8:55-60), [23] is a QCA multiplexer proposed by Sen B et al. (Sen B, Goswami M, Mazumdar S, Sikdar BK (2015) Towards modular design of reliable quantum-dot cellular automata logic circuit using multiplexers. Comput Electr Eng 45:42-54). And, [the present invention] shows the QCA multiplexers 100 and 200 according to the present invention.

12 and 13, the QCA multiplexers 100 and 200 according to the present invention are focused on reducing time complexity and hardware complexity, and are improved over previous designs in terms of the number of cells, total surface area, and clock phase. it can be seen that In addition, the QCA multiplexers 100 and 200 according to the present invention can transmit a strong signal based on a compact structure using an appropriate clock phase, and since only NAND gates are used to implement the multiplexer, it is advantageous in terms of design and manufacturing. .

FIG. 14 is a diagram illustrating simulation results of the QCA 4 to 1 multiplexer shown in FIG. 7 .

As can be seen from FIG. 14 , the QCA 4:1 multiplexer 200 uses 79 QCA cells, uses fewer clock cycles, and exhibits excellent performance in terms of calculation speed and the like.

15 shows a power dissipation map of a QCA 2-to-1 multiplexer according to the present invention and a QCA multiplexer according to a previous design.

In FIG. 15 (a) is a QCA multiplexer proposed by Mardiris VA, et al. (Mardiris VA, Karafyllidis IG (2010) Design and simulation of modular 2 to 1 quantum-dot cellular automata (QCA) multiplexers. Int J Circuit Theory Appl 38:771- 785), (b) is a QCA multiplexer proposed by Mukhopadhyay D et al. (Mukhopadhyay D, Dinda S, Dutta P (2011) Designing and implementation of quantum cellular automata 2:1 multiplexer circuit. Int J Comput Appl Technol 25:21-24) , (c) shows a QCA multiplexer (Hashemi S, Navi K (2012) New robust QCA D flip flop and memory structures. Microelectron J43:929-940) proposed by Hashemi S et al., (d) is a QCA according to the present invention A two-to-one multiplexer 100 is shown.

15 shows energy dissipation at 0.5 E _k , indicating that dark cells consume more energy than other cells.

Figure 16 shows the power loss analysis of the QCA 2 to 1 multiplexer according to the present invention and the QCA multiplexer according to the previous design, showing the total energy consumed by leakage and switching energy.

In FIG. 16, [17] is a QCA multiplexer proposed by Lee JS et al. (Lee JS, Jeon JC (2016) NAND gate based QCA 2-to-1 line multiplexer. Asia Pac Proc Appl SciEng Better Hum Life 6:45-48) , [18] is a QCA multiplexer proposed by Safoev N et al. (Safoev N, Jeon JC (2016) Low area complexity demultiplexer based on multilayer quantum-dot cellular automata. Int J Control Autom 9:165-178), [19] is Mardiris The QCA multiplexer proposed by VA et al. (Mardiris VA, Karafyllidis IG (2010) Design and simulation of modular 2 to 1 quantum-dot cellular automata (QCA) multiplexers. Int J Circuit Theory Appl 38:771-785), [20] is Mukhopadhyay The QCA multiplexer proposed by D et al. (Mukhopadhyay D, Dinda S, Dutta P (2011) Designing and implementation of quantum cellular automata 2:1 multiplexer circuit. Int J Comput Appl Technol 25:21-24), [21] is Hashemi S et al. This proposed QCA multiplexer (Hashemi S, Navi K (2012) New robust QCA D flip flop and memory structures. Microelectron J43:929-940) is presented. And, [the present invention] shows the QCA 2 to 1 multiplexer 100 according to the present invention.

As shown in FIG. 16 , it can be seen that the QCA 2 to 1 multiplexer 100 according to the present invention also reduces energy loss.

And, the energy lost can be measured based on the Hamiltonian matrix using the Hartree-Fock approximation for the Coulomb interaction between cells defined as follows.

로 표현된다. Ek는 두 셀(i 및 j)의 에너지 비용과 관련된 꼬임 에너지이며, 이 꼬임 에너지는 극성이 반대되는 두 셀의 에너지 비용과 관련이 있다. 그리고,

은 클럭에 의해 제어되는 셀 내부의 전자 터널링 에너지를 나타낸다.In the above equation, the polarization of the i-th parallel cell is expressed as Ci, and the geometric factor identifying the electrostatic interaction between cells i and j is due to the geometric distance

is expressed as Ek is the twist energy related to the energy cost of the two cells (i and j), and this twist energy is related to the energy cost of the two cells with opposite polarities. and,

represents the electron tunneling energy inside the cell controlled by the clock.

Meanwhile, in the QCA multiplexer and the QCA arithmetic logic device using the same according to the present invention, the configuration and method of the embodiments described above are not limitedly applicable, but the embodiments are each embodiment so that various modifications can be made. All or part of the examples may be selectively combined and configured.

In addition, although preferred embodiments of the present invention have been illustrated and described above, the present invention is not limited to the specific embodiments described above, and the technical field to which the present invention belongs without departing from the gist of the present invention as claimed in the claims In addition, various modifications may be made by those of ordinary skill in the art, and these modifications should not be individually understood from the technical spirit or perspective of the present invention.

Claims (6)

a first combinational logic cell to which a signal obtained by inverting the first input signal and the selection signal is input, and performing an AND gate function;
a second combinational logic cell to which a second input signal and the selection signal are input, and performing an AND gate function;
a third combinational logic cell to which a signal obtained by inverting the output signal of the first combinational logic cell and a signal obtained by inverting the output signal of the second combinational logic cell are input, and performing an AND gate function; and
A QCA multiplexer comprising a fourth combinational logic cell that performs an inverter function and outputs a signal obtained by inverting the output signal of the third combinational logic cell as a final output signal. According to claim 1,
The first to third combinational logic cells are QCA multiplexer, characterized in that one of the inputs of the 3-input majority vote gate is a combinational logic cell in which a value corresponding to logic bit 0 is fixed. According to claim 1,
The fourth combinational logic cell, QCA multiplexer, characterized in that consisting of two cells arranged diagonally adjacent to the output cell of the third combinational logic cell. a first QCA 2-to-1 multiplexer for outputting any one of the first and second input signals as a first output signal according to the first selection signal;
a second QCA 2-to-1 multiplexer for outputting any one of the third and fourth input signals as a second output signal according to the first selection signal; and
A QCA multiplexer comprising a third QCA 2-to-1 multiplexer for outputting any one of the first and second output signals according to a second selection signal. A QCA arithmetic logic device for selecting an arithmetic operation to be performed using the QCA multiplexer of any one of claims 1 to 3. A quantum dot cellular automata device comprising the multiplexer of any one of claims 1 to 3.

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