CN117610471A - Method, system, equipment and medium for eliminating simulation competition adventure of non-sequential netlist - Google Patents
Method, system, equipment and medium for eliminating simulation competition adventure of non-sequential netlist Download PDFInfo
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- CN117610471A CN117610471A CN202311624415.1A CN202311624415A CN117610471A CN 117610471 A CN117610471 A CN 117610471A CN 202311624415 A CN202311624415 A CN 202311624415A CN 117610471 A CN117610471 A CN 117610471A
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- 238000004088 simulation Methods 0.000 title claims abstract description 43
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Abstract
The invention relates to the technical field of verification of a back-end netlist of digital circuit simulation, and discloses a method, a system, equipment and a medium for eliminating simulation competition risk of a non-sequential netlist, which comprise the following steps: s1, adding an intermediate variable for storing input data in a time sequence related library unit; s2, collecting input data of the library units related to time sequence; s3, after delaying the first time, saving the value of the input data into an intermediate variable; s4, the intermediate variable after the step S3 is used as an input value to be sent to a corresponding library unit, and the library unit is guaranteed to accept an old value of original input data before a clock edge comes, so that competition of non-sequential netlist simulation is eliminated. The method of the invention can reduce the influence on the performance as much as possible in the process of eliminating the competing risks of netlist simulation.
Description
Technical Field
The invention relates to the technical field of verification of a back-end netlist of digital circuit simulation, in particular to a method, a system, equipment and a medium for eliminating simulation competition risk of a non-sequential netlist.
Background
The competition and adventure in the digital circuit occur in the combinational logic circuit, after the same signal is transmitted through different paths, the time for reaching a certain meeting point in the circuit is prior, the phenomenon is called logic competition, and the phenomenon of generating output interference pulse is called adventure. There are three general methods for eliminating the competing hazards in the back-end netlist of digital circuit simulation:
first kind: the traditional scheme is as follows: finding out the place of sampling error through error waveform, modifying netlist at the corresponding place, adding fine delay;
second kind: library element behavior modeling scheme: modifying a library file provided by a fourdry plant, and re-modeling units in the library file;
third kind: library element delay scheme: a fine delay is added in some gates of the library cells or the FLOP cells.
The three schemes all have certain problems:
the first solution has the disadvantage: the method is very time-consuming, and the problem can not be solved in other places when some places are modified, so that the place with the problem is usually right, and other problems are raised;
the second solution has the disadvantage: the workload is large, and the method is generally suitable for companies with large scale, sufficient verification personnel and a certain project accumulation;
the third solution has the disadvantage: this scheme, which has a small overall delay of data relative to the clock, usually has a significant impact on performance, and originally only has data changes on the rising and falling clock edges, then only the events need to be evaluated on the rising and falling clock edges, and all events are now shifted, so that the events need to be evaluated at the moment of data changes, except on the rising and falling clock edges, and in addition, the delay to which units is not certain, and repeated experiments are required, and the process is very time-consuming, as shown in fig. 2.
Therefore, a solution for simply and thoroughly eliminating the risk of simulation competition of the non-sequential netlist is needed.
Disclosure of Invention
The invention provides a method, a system, equipment and a medium for eliminating simulation competition risk of a non-sequential netlist, which are used for solving the problems.
The invention is realized by the following technical scheme:
a method of eliminating a non-sequential netlist simulation competition hazard, comprising:
s1, adding an intermediate variable for storing input data in a time sequence related library unit;
s2, collecting input data of the library units related to time sequence;
s3, after delaying the first time, saving the value of the input data into an intermediate variable;
s4, the intermediate variable after the step S3 is used as an input value to be sent to a corresponding library unit, and the library unit is guaranteed to accept an old value of original input data before a clock edge comes, so that competition of non-sequential netlist simulation is eliminated.
As optimization, the specific steps of S1 are:
s1.1, finding primitives of library units related to clock acquisition data in a related library file of a digital circuit to be simulated;
s1.2, correspondingly copying the primitives of each library unit into a file named by each library unit;
s1.3, renaming the initial names of the primitives of the library units in each file to obtain new names of the primitives of each library unit respectively;
s1.4, newly creating intermediate modules, wherein the number of the intermediate modules is the same as that of the library units, the names of each intermediate module respectively correspond to the initial name of a primitive of one library unit, the interfaces of the intermediate modules are the same as the primitive of the corresponding library unit, and the intermediate modules named by the initial names of the primitives of the library units are intermediate variables related to the primitives of the library unit.
As optimization, the specific steps of S2 are: the input data of the primitives of the library element are replicated.
As an optimization, the first time in S3 ranges from not more than half a clock cycle.
As optimization, the specific steps of S4 are: and sending the intermediate variable after S3 as an input value to a library unit after the primitive is renamed.
And S5, after receiving the corresponding input values, storing a list of all related library files into one file, and then generating all modified related library files in batches by using a rtlmod tool.
As an optimization, the library elements comprise flip-flops and/or latches.
The invention also discloses a system for eliminating the simulation competition adventure of the non-sequential netlist, which is used for implementing the method for eliminating the simulation competition adventure of the non-sequential netlist, and comprises the following steps:
an intermediate variable adding module for adding an intermediate variable for storing input data in a time-series related library unit;
the acquisition module acquires input data of the library units related to time sequence;
the delay input module is used for storing the value of the input data into an intermediate variable after delaying the first time;
and the sending module is used for sending the intermediate variable obtained after being processed by the delay input module to a corresponding library unit as an input value, so that the library unit is ensured to accept the old value of the original input data before the clock edge comes, and the competition of eliminating the sequential netlist simulation is realized.
The invention also discloses an electronic device, which comprises at least one processor and a memory in communication connection with the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method of eliminating a non-sequential netlist simulation competition hazard as described above.
The invention also discloses a storage medium storing a computer program which when executed by a processor realizes the method for eliminating the simulation competition risk of the non-sequential netlist.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the invention thoroughly solves the problem of post-imitation competition adventure without a sequential netlist;
the modification method is simple and regular, and the script can be modified in batches;
the method of the invention can reduce the influence on the performance as much as possible in the process of eliminating the competing risks of netlist simulation.
Drawings
In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the drawings that are needed in the examples will be briefly described below, it being understood that the following drawings only illustrate some examples of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained from these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a generalized flow chart of a method for eliminating a non-sequential netlist simulation competition hazard according to the present invention;
FIG. 2 is an exemplary diagram of a third scenario in the background art;
FIG. 3 is an exemplary diagram of clock acquisition data;
FIG. 4 is a schematic diagram of the structure of a D flip-flop;
FIG. 5 is a schematic diagram of a gated D latch;
FIG. 6 is an exemplary diagram of clock acquisition data obtained by the method of the present invention;
FIG. 7 is a schematic diagram of a D flip-flop or gated D latch obtained by the method of the present invention;
fig. 8 is a detailed flowchart in an embodiment.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
The reasons for the functional errors in the netlist simulation, when data is taken with clocks, unexpected values are taken. As shown in fig. 3, if a new value of 0x5fff0 (referred to as a new value) is taken at time 8, then this value is an unexpected value. If 0x0000 (called the old value) is taken, then it is the expected value.
In the netlist, the cells associated with the clock data are flip-flops and latches.
The Flip-Flop (Flip-Flop) is a clock edge trigger, can store 1-bit data, and is a basic constituent unit of a register (resignster). FIG. 4 is a typical D flip-flop configuration;
the Latch (Latch) is level triggered and fig. 5 is a typical gated D Latch structure.
There are many different types of flip-flops and latches, and in order to solve the problem of data mining errors, there is no concern about their particular type, it is important to be able to ensure that the output (Q) is the old value of the input (D) and not the new value.
To ensure that the output (Q) is the old value of the input (D), we can take the value of the input (D) down before feeding it to the flip-flop and latch. The SystemVerilog standard specifies that the input value is taken first and then sent to the flip-flop and latch to ensure that the output (Q) is the old value of the input (D).
The signal after output is still aligned with the clock (this is the characteristic of the D flip-flop, the output Q is aligned with the clock, which belongs to the basic circuit knowledge and will not be described here again), and no new evaluation time point will be added. The method has very fine modification and is very easy to write script batch operation. The waveform is basically consistent with the front imitation waveform.
If the input value is not taken first, the input is directly supplied to the D flip-flop, and the output signal is still aligned with the clock, but this cannot guarantee that the value of the output (Q) is the old value of D. As shown in FIG. 6, in normal netlist simulation, the D input is shown as data, and in 8ns, the Q output may be either 0x0000 or 0x5ff0. If the value of D is taken down (0 x 0000) first, then it is sent to the D flip-flop, the Q output must be 0x0000 (old value).
In particular operations, the lowest primitive (private) needs to be found instead of the gate unit. In a library file given by a manufacturing plant, there are very many gate units, and if the gate units are modified, the effort is very great. The gate units are composed of more basic gate units and primitives. We replace the primitives of the sequential logic.
Taking as an example library elements under certain process conditions of the central core international (SMIC), they all use the following three primitives (primitives).
Udp_tlat: latch device
Udp_dff: general register
Udp_sedfft: register with scanning function
The invention is slightly modified based on the original method, firstly, the input data is sampled, after slight delay (the maximum can not exceed half clock period (4 ns in the illustrated diagram) is generally used, the effect of the slight delay is the same because the delay is 0.1ns and 3ns, so that the effect is not small, the advantage is that the waveform of the netlist simulation is basically the same as the waveform of the RTL), the data is saved on an intermediate variable, then the intermediate variable is sent to the original primitive module, the final process is as shown in fig. 8, the structure of a corresponding D trigger or a gating D latch by the method of the invention is as shown in fig. 7, the left side is the prior means, the right side is the means after the implementation of the method of the invention, D_dly is the intermediate variable carrying the input data Q, and the data and the clock diagram after the execution by a library unit of the method of the invention are as shown in fig. 6. The specific procedure is as in example 1:
a method for eliminating contention risk of non-sequential netlist simulation in embodiment 1, as shown in fig. 1, includes:
s1, adding an intermediate variable for storing input data in a time sequence related library unit; as described above, the timing dependent bank unit includes flip-flops and/or latches.
The specific process of step S1 is as follows:
s1.1, finding primitives of library units related to clock acquisition data in a related library file of a digital circuit to be simulated;
s1.2, correspondingly copying the primitives of each library unit into a file named by each library unit;
in the library file given by the chip manufacturer, one file contains a plurality of primitive definitions, the definition of one primitive in the library file is copied out, a file named by the primitive is newly built, and the definition of the primitive is placed in the file.
S1.3, renaming the initial names of the primitives of the library units in each file to obtain new names of the primitives of each library unit respectively;
s1.4, newly creating intermediate modules, wherein the number of the intermediate modules is the same as that of the library units, the names of each intermediate module respectively correspond to the initial name of a primitive of one library unit, the interfaces of the intermediate modules are the same as the primitive of the corresponding library unit, and the intermediate modules named by the initial names of the primitives of the library units are intermediate variables related to the primitives of the library unit.
The module in the middle module is a unit in verilog language, and v is used as suffix name for verilog file.
The intermediate modules verilog module and private will both contain input, output, inout. Such as: moduledff (a, clk, b);
input a；
input clk；
output b；
< detailed description > implementation
endmodule
The above a, clk, b are interfaces, a, clk are inputs, and b is an output.
The same is true of pritive.
primitive ulat_dff(a,clk,b)；
input a；
input clk；
output b；
< detailed description > implementation
endprimitive
S2, collecting input data of the library units related to time sequence; the method comprises the following specific steps: the input data of the primitives of the library element are replicated.
S3, after delaying the first time, saving the value of the input data into an intermediate variable; as described above, the first time ranges from no more than half a clock cycle.
Without delay, then the value of the intermediate variable is the same as the original value and the simulation result does not change. The purpose of the delay is to ensure that the value of the intermediate variable is the old value (e.g., the variable sees a change on the rising edge of the clock, at this point in time the edge, the front of the edge is called the old value, and the back of the edge is called the new value).
S4, the intermediate variable after the step S3 is used as an input value to be sent to a corresponding library unit, and the library unit is guaranteed to accept an old value of original input data before a clock edge comes, so that competition of non-sequential netlist simulation is eliminated. Specifically, the intermediate variable after S3 is used as an input value to be sent to a library unit after the primitive is renamed.
And S5, after all the library units receive the corresponding input values, saving the list of all the related library files into one file, and then using the rtlmod tool to generate all the modified related library files in batches.
The rtlmod tool generates all the modified related library files in batches, namely the batch automation processing of the scripts is realized, and an open source tool of an author can be used: https:// gitsub.com/zhuzhzhzhzhz/rtlmod.
It can conveniently replace modules (modules) or primitives (primitives) in the netlist file. It is necessary to provide a start keyword and an end keyword, and then replace the content between the start keyword and the end keyword with the content in a file, which is not described in detail herein.
The method minimizes the modification cost by modifying the primitives such as the trigger, the latch and the like at the bottommost layer in the library, and can output the old value while aligning the output with the clock by sampling the input value and then sending the original primitive unit to process the output, thereby reducing the performance burden.
Embodiment 2 also discloses a system for eliminating the simulation competition adventure of the non-sequential netlist, which is used for implementing the method for eliminating the simulation competition adventure of the non-sequential netlist, and comprises the following steps:
an intermediate variable adding module for adding an intermediate variable for storing input data in a time-series related library unit;
the acquisition module acquires input data of the library units related to time sequence;
the delay input module is used for storing the value of the input data into an intermediate variable after delaying the first time;
and the sending module is used for sending the intermediate variable obtained after being processed by the delay input module to a corresponding library unit as an input value, so that the library unit is ensured to accept the old value of the original input data before the clock edge comes, and the competition of eliminating the sequential netlist simulation is realized.
Embodiment 3 also discloses an electronic device comprising at least one processor, and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method of eliminating a non-sequential netlist simulation competition hazard as described above.
Embodiment 4 also discloses a storage medium storing a computer program which, when executed by a processor, implements a method of eliminating a non-sequential netlist simulation competition hazard as described above.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (10)
1. The method for eliminating the simulation competition adventure of the non-sequential netlist is characterized by comprising the following steps:
s1, adding an intermediate variable for storing input data in a time sequence related library unit;
s2, collecting input data of the time sequence correlation library unit;
s3, after delaying the first time, saving the value of the input data into an intermediate variable;
s4, the intermediate variable after the step S3 is used as an input value to be sent to a corresponding library unit, and the library unit is guaranteed to accept an old value of original input data before a clock edge comes, so that competition of non-sequential netlist simulation is eliminated.
2. The method for eliminating simulation competition adventure of non-sequential netlist according to claim 1, wherein the specific steps of S1 are as follows:
s1.1, finding primitives of library units related to clock acquisition data in a related library file of a digital circuit to be simulated;
s1.2, correspondingly copying the primitives of each library unit into a file named by each library unit;
s1.3, renaming the initial names of the primitives of the library units in each file to obtain new names of the primitives of each library unit respectively;
s1.4, newly creating intermediate modules, wherein the number of the intermediate modules is the same as that of the library units, the names of each intermediate module respectively correspond to the initial name of a primitive of one library unit, the interfaces of the intermediate modules are the same as the primitive of the corresponding library unit, and the intermediate modules named by the initial names of the primitives of the library units are intermediate variables related to the primitives of the library unit.
3. The method for eliminating simulation competition adventure of non-sequential netlist according to claim 1, wherein the specific steps of S2 are as follows: the input data of the primitives of the library element are replicated.
4. The method of eliminating a non-sequential netlist simulation competition hazard according to claim 1, wherein the first time in S3 is in a range of not more than half a clock cycle.
5. The method for eliminating the simulation competition risk of the non-sequential netlist according to claim 2, wherein the specific steps of S4 are as follows: and sending the intermediate variable after S3 as an input value to a library unit after the primitive is renamed.
6. The method of claim 2, further comprising S5, after all the library units receive the corresponding input values, saving the list of all the related library files to a file, and then generating all the modified related library files in batch using rtlmod tool.
7. A method of eliminating a sequential netlist free simulation competition hazard according to any of claims 1-6, wherein the library elements comprise flip-flops and/or latches.
8. A system for eliminating a non-sequential netlist simulation competition adventure, for implementing a method for eliminating a non-sequential netlist simulation competition adventure as claimed in any of claims 1-7, comprising:
an intermediate variable adding module for adding an intermediate variable for storing input data in a time-series related library unit;
the acquisition module is used for acquiring the input data of the library units related to time sequence;
the delay input module is used for storing the value of the input data into an intermediate variable after delaying the first time;
and the sending module is used for sending the intermediate variable obtained after being processed by the delay input module to a corresponding library unit as an input value, so that the library unit is ensured to accept the old value of the original input data before the clock edge comes, and the competition of eliminating the sequential netlist simulation is realized.
9. An electronic device comprising at least one processor, and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a method of eliminating non-sequential netlist simulation competition hazards as recited in any one of claims 1 to 7.
10. A storage medium storing a computer program which when executed by a processor implements a method of eliminating a non-sequential netlist simulation competition hazard as claimed in any one of claims 1 to 7.
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