CN112865758B - Reversible single-edge T trigger capable of asynchronously setting number - Google Patents

Reversible single-edge T trigger capable of asynchronously setting number Download PDF

Info

Publication number
CN112865758B
CN112865758B CN202110055794.1A CN202110055794A CN112865758B CN 112865758 B CN112865758 B CN 112865758B CN 202110055794 A CN202110055794 A CN 202110055794A CN 112865758 B CN112865758 B CN 112865758B
Authority
CN
China
Prior art keywords
input
output
terminal
input terminal
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110055794.1A
Other languages
Chinese (zh)
Other versions
CN112865758A (en
Inventor
吴钰
王伦耀
夏银水
储著飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ningbo University
Original Assignee
Ningbo University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ningbo University filed Critical Ningbo University
Priority to CN202110055794.1A priority Critical patent/CN112865758B/en
Publication of CN112865758A publication Critical patent/CN112865758A/en
Application granted granted Critical
Publication of CN112865758B publication Critical patent/CN112865758B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits

Landscapes

  • Logic Circuits (AREA)

Abstract

The invention discloses a reversible single-edge T trigger capable of asynchronously setting numbers, which consists of 3 Feynman reversible logic gates and 4 Fredkin reversible logic gates, and is provided with an asynchronous setting number enable signal input end, a clock signal input end, a data input end, a preset number input end, a first logic low level input end, a second logic low level input end, a third logic low level input end, an asynchronous setting number enable signal output end, a trigger present signal output end, a first garbage position output end, a second garbage position output end, a third garbage position output end and 2 signal output ends for outputting clock signals or logic low level signals; the reversible sequential logic circuit has the advantages that the reversible sequential logic circuit has a single-edge T trigger function and an asynchronous number setting function, and is favorable for enabling the reversible sequential logic circuit to run from a determined initial state or return to a controllable determined state from an error state after asynchronous number setting.

Description

Reversible single-edge T trigger capable of asynchronously setting number
Technical Field
The invention relates to a reversible logic circuit, in particular to a reversible single-edge T trigger capable of asynchronously setting numbers, which is formed by utilizing a Feynman reversible logic gate and a Fredkin reversible logic gate.
Background
How to reduce the power consumption of the circuit is a key issue in the current integrated circuit design. In a conventional irreversible logic circuit, information bit data loss is a main cause of circuit power consumption, and therefore, a reversible logic circuit design capable of avoiding information bit data loss has become an approach to low power consumption design. Meanwhile, the reversible logic circuit is also an important component for quantum computation and quantum information technology research.
The reversible logic circuit includes a reversible combinational logic circuit and a reversible sequential logic circuit. In a reversible sequential logic circuit, the significance of the set-up signal is second only to the clock signal, and the most basic purpose of asynchronous set-up is to bring the circuit into a certain state that can operate stably. The reversible flip-flop is a basic device constituting the reversible sequential logic circuit, how to initialize the reversible sequential logic circuit is a link which must be faced in the design process of the reversible sequential logic circuit, and the initialization of the reversible sequential logic circuit can be generally realized by initializing the reversible flip-flop.
Reversible flip-flops can be implemented using Feynman reversible logic gates and Fredkin reversible logic gates. Fig. 1 is a schematic circuit diagram of a Feynman reversible logic gate. The Feynman reversible logic gate has 2 input ends, namely a control input end and a target input end which are correspondingly marked as It1And It2(ii) a The Feynman reversible logic gate has 2 output terminals, namely a control output terminal and a target output terminal, which are correspondingly marked as Ot1And Ot2. Assume input to control input It1Is A and is input to a target input terminal It2If the input value is B, the output terminal O is controlledt1The output value is A, and the target output end is Ot2Output an output value of
Figure BDA0002900559460000011
Wherein, the symbol
Figure BDA0002900559460000012
Is an exclusive or operation sign. Fig. 2 is a schematic diagram of a circuit structure of a Fredkin reversible logic gate. Fredkin reversible logic gate has 3 input ends, respectively control input end, first target input end and second target input end, and are marked as If1、If2And If3The Fredkin reversible logic gate has 3 output terminals, namely a control output terminal, a first target output terminal and a second target output terminal, which are correspondingly marked as Of1、Of2And Of3. Assume input to control input If1Is X, is input to a first target input terminal If2Is Y, is input to a second target input terminal If3Is Z, the output terminal O is controlledf1The output value of X, i.e. the control output Of1The output value of the output is equal to the input value of the control input terminal If1Input value of, first target output terminal Of2Output an output value of
Figure BDA0002900559460000021
Second target output terminal Of3Output an output value of
Figure BDA0002900559460000022
When input to the control input terminal If1When the input value of (1) is "0", the first target output terminal Of2The output value is Y, and the second target output end is Of3The output value is Z, i.e. the first target output terminal Of2The output value of the output is equal to the input value of the first target input end If2Input value of, second target output terminal Of3The output value of the output is equal to the input value of the second target input end If3An input value of (a); when input to the control input terminal If1When the input value of (1) is zero, the first target output terminal Of2Output value Z, second target output terminal Of3The output value is Y, i.e. the first target output terminal Of2The output value of the output is equal to the input value of the second target input end If3Input value of, second target output terminal Of3The output value of the output is equal to the input value of the first target input end If2An input value of (a); wherein the content of the first and second substances,
Figure BDA0002900559460000023
indicating that X is not logically operated on.
However, the existing reversible flip-flop has no asynchronous setting function, and therefore, the research on the reversible single-edge T flip-flop with the asynchronous setting function is beneficial to make the reversible sequential logic circuit run from a determined initial state or return from an error state to a controllable determined state after the asynchronous setting.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a reversible single-edge T flip-flop capable of asynchronously setting numbers, which has the function of the single-edge T flip-flop and the function of asynchronously setting numbers, and is beneficial to enabling a reversible sequential logic circuit to run from a determined initial state or return from an error state to a controllable determined state after the asynchronous setting numbers.
The technical scheme adopted by the invention for solving the technical problems is as follows: asynchronous deviceThe reversible single-edge T flip-flop is characterized by comprising 3 Feynman reversible logic gates and 4 Fredkin reversible logic gates, wherein the 3 Feynman reversible logic gates are respectively marked as T0、t1And t2Will t0、t1And t2Respective control input terminal as first input terminal, let t0、t1And t2Respective target input terminal as second input terminal, let t0、t1And t2Respective control output terminal as the first output terminal, and t0、t1And t2Respective target output terminal as second output terminal at t0、t1And t2The output value of the first output terminal is equal to the input value of the first input terminal, and the output value of the second output terminal is equal to the logical exclusive-or of the input value of the first input terminal and the input value of the second input terminal; the 4 Fredkin reversible logic gates are respectively recorded as f1、f2、f3And f4A 1 is to f1、f2、f3And f4Respective control input terminal as first input terminal, f1、f2、f3And f4Respective first target input terminal as second input terminal, and f1、f2、f3And f4Respective second target input terminal as third input terminal, and f1、f2、f3And f4Respective control output terminal as the first output terminal, and f1、f2、f3And f4Respective first target output terminal as second output terminal, and f1、f2、f3And f4Respective second target output terminal as third output terminal at f1、f2、f3And f4In each case, the output value of the first output terminal is equal to the input value of the first input terminal, the output value of the second output terminal is equal to the input value of the second input terminal and the output value of the third output terminal is equal to the input value of the third input terminal when the input value of the first input terminal is "0", and the output value of the second output terminal is equal to the input value of the third input terminal when the input value of the first input terminal is "1The input value of the input end and the output value of the third output end are equal to the input value of the second input end;
the reversible single-edge T flip-flop comprises an asynchronous digital enable signal input end M, a clock signal input end C, a data input end I, a digital preset input end P, and a first logic low level input end L1A second logic low level input terminal L2A third logic low level input terminal L3And an asynchronous setting enable signal output end M', a trigger present signal output end Q and a first garbage position output end g1And a second garbage position output end g2And a third garbage position output end g32 signal output terminals O for outputting clock signals or logic low level signals1And O2(ii) a In the reversible single-edge T flip-flop, a logic low level is represented by "0", a logic high level is represented by "1", and Q is setnIndicating a flip-flop substate;
in the reversible single-edge T flip-flop, T0First input terminal and t1Is connected to a second output terminal t0Is connected to the data input I, t0First output terminal and f2Is connected to the second input terminal of t0Second output terminal of and f3Is connected with the second input end of the trigger, and the trigger is in a secondary state QnAt t0And f is a second output terminal and3on the second input of (f)1First input terminal and f4Is connected to the first output terminal of f1And a first logic low level input terminal L1Connection of f1Is connected to the clock signal input C, f1Is connected with an asynchronous setting enable signal output M', f1And one of the signal output terminals O for outputting a clock signal or a logic low level signal1Connection of f1Third output terminal of (d) and f3Is connected to the first input terminal of f2First input terminal and f3Is connected to the first output terminal of f2Third input terminal of and t2Is connected to the first output terminal of f2And the other one is used for outputting a clock signal or a logic low signalSignal output terminal O of number2Connection of f2Second output terminal and first garbage level output terminal g1Connection of f2Third output terminal and t1Is connected to the first input terminal of f3Third input terminal of (d) and f4Is connected to the second output terminal of f3Second output terminal and second garbage level output terminal g2Connection of f3Third output terminal and t2Is connected to the first input terminal of f4Is connected to an asynchronous set-number enable signal input M, f4Second input terminal and t2Is connected to the second output terminal of f4Is connected to the preset number input P, f4Third output terminal and third garbage level output terminal g3Connection, t1And a second logic low level input terminal L2Connection, t1Is connected with the flip-flop present signal output Q, t2And a third logic low level input terminal L3And (4) connecting.
Inputting an asynchronous reset enable signal SR to an asynchronous reset enable signal input terminal M, inputting a clock signal clk to a clock signal input terminal C, and inputting flip-flop data TgInput to the data input terminal I, and input the preset number N to the preset number input terminal P to make the first logic low level input terminal L1A second logic low level input terminal L2A third logic low level input terminal L3Are all connected with logic '0', and the signal output by the current signal output end Q of the trigger is recorded as QCT；
When the asynchronous set enable signal SR is logic high level, i.e. logic' 14The output value of the second output terminal is a preset number N, f1Has an output value of logic "0", so that f2Input value sum f of the first input terminal of3Is all logic '0', thereby causing Q to be equalCTThe function of asynchronous number setting is realized;
when the asynchronous set enable signal SR is logic low level, i.e. logic' 02Input value sum f of the first input terminal of3First input ofThe input values of the terminals are equal to the clock signals clk, f4The input value of the first input terminal of (a) is logic "0"; if the clock signal clk is logic high, i.e. logic "1", then t is asserted2,f3,f4The latch circuit is in data receiving state, and the received data is t0Output value Q of the second output terminaln，
Figure BDA0002900559460000041
And is dependent on the flip-flop data TgIs continuously updated by t1,f2The latch circuit is in latch state to ensure QCTDon' T follow trigger data TgIs changed; if the clock signal clk changes from logic high to logic low, i.e. from logic "1" to logic "0", then t is the integer2,f3,f4The latch circuit is configured to transition from a data receiving state to a latching state, where the latched data is the time t at which the clock signal clk is going to transition from a logic high level to a logic low level0Output value Q of the second output terminalnFrom t to1,f2The latch circuit is configured to change from a latched state to a data receiving state, the received data being represented by t2,f3,f4The formed latch circuit latches data; if the clock signal clk changes from logic low to logic high, i.e. from logic "0" to logic "1", as time goes on, t is counted1,f2The latch circuit is configured to change from a data receiving state to a latching state, the latched data being QCTFrom t to2,f3,f4The latch circuit is in the data receiving state again, and the received data is t0Output value Q of the second output terminalnThe function of a single-edge T trigger is realized; wherein, the symbol
Figure BDA0002900559460000051
Is an exclusive or operation sign.
Compared with the prior art, the invention has the advantages that:
1) the reversible single-edge T trigger not only has the function of a single-edge T trigger, but also can register the preset number in the trigger and output the preset number when the asynchronous preset number enabling signal is effective, and can respectively realize the asynchronous zero clearing or 1 setting of the trigger by changing the value of the preset number, thereby being beneficial to leading the reversible sequential logic circuit to run from a determined initial state or return from an error state to a controllable determined state after the asynchronous preset number.
2) When the reversible single-edge T trigger is used for forming the reversible sequential logic circuit, the initialization of the reversible sequential logic circuit can be conveniently realized by using an asynchronous number setting enabling signal and a preset number.
Drawings
FIG. 1 is a schematic diagram of a circuit configuration of a Feynman reversible logic gate;
FIG. 2 is a schematic diagram of a Fredkin reversible logic gate circuit;
FIG. 3 is a schematic diagram of a reversible single-edge T flip-flop capable of asynchronous setting according to the present invention;
FIG. 4 is a schematic diagram of the circuit configuration of FIG. 3 with the addition of input and output signals;
fig. 5 is a schematic diagram of a simulation result of the functional simulation performed on fig. 4.
Detailed Description
The invention is described in further detail below with reference to the accompanying examples.
The reversible single-edge T trigger capable of asynchronously setting numbers is composed of 3 Feynman reversible logic gates and 4 Fredkin reversible logic gates, and the 3 Feynman reversible logic gates are respectively recorded as T0、t1And t2Will t0、t1And t2Respective control input terminal as first input terminal, let t0、t1And t2Respective target input terminal as second input terminal, let t0、t1And t2Respective control output terminal as the first output terminal, and t0、t1And t2Respective target output terminal as second output terminal at t0、t1And t2Output of the respective first output terminalA value equal to the input value of the first input, an output value of the second output equal to the logical xor of the input value of the first input and the input value of the second input; the 4 Fredkin reversible logic gates are respectively recorded as f1、f2、f3And f4A 1 is to f1、f2、f3And f4Respective control input terminal as first input terminal, f1、f2、f3And f4Respective first target input terminal as second input terminal, and f1、f2、f3And f4Respective second target input terminal as third input terminal, and f1、f2、f3And f4Respective control output terminal as the first output terminal, and f1、f2、f3And f4Respective first target output terminal as second output terminal, and f1、f2、f3And f4Respective second target output terminal as third output terminal at f1、f2、f3And f4In each case, the output value of the first output terminal is equal to the input value of the first input terminal, the output value of the second output terminal is equal to the input value of the second input terminal and the output value of the third output terminal is equal to the input value of the third input terminal when the input value of the first input terminal is "0", the output value of the second output terminal is equal to the input value of the third input terminal and the output value of the third output terminal is equal to the input value of the second input terminal when the input value of the first input terminal is "1". The reversible single-edge T flip-flop comprises an asynchronous digital enable signal input end M, a clock signal input end C, a data input end I, a digital preset input end P, and a first logic low level input end L1A second logic low level input terminal L2A third logic low level input terminal L3And an asynchronous setting enable signal output end M', a trigger present signal output end Q and a first garbage position output end g1And a second garbage position output end g2And a third garbage position output end g32 signal output terminals O for outputting clock signals or logic low level signals1And O2(ii) a In the reversible single-edge T flip-flop, settingLogic low is represented by "0", logic high by "1", and QnIndicating a flip-flop substate. In the reversible single-edge T flip-flop, T0First input terminal and t1Is connected to a second output terminal t0Is connected to the data input I, t0First output terminal and f2Is connected to the second input terminal of t0Second output terminal of and f3Is connected with the second input end of the trigger, and the trigger is in a secondary state QnAt t0And f is a second output terminal and3on the second input of (f)1First input terminal and f4Is connected to the first output terminal of f1And a first logic low level input terminal L1Connection of f1Is connected to the clock signal input C, f1Is connected with an asynchronous setting enable signal output M', f1And one of the signal output terminals O for outputting a clock signal or a logic low level signal1Connection of f1Third output terminal of (d) and f3Is connected to the first input terminal of f2First input terminal and f3Is connected to the first output terminal of f2Third input terminal of and t2Is connected to the first output terminal of f2And another signal output terminal O for outputting a clock signal or a logic low level signal2Connection of f2Second output terminal and first garbage level output terminal g1Connection of f2Third output terminal and t1Is connected to the first input terminal of f3Third input terminal of (d) and f4Is connected to the second output terminal of f3Second output terminal and second garbage level output terminal g2Connection of f3Third output terminal and t2Is connected to the first input terminal of f4Is connected to an asynchronous set-number enable signal input M, f4Second input terminal and t2Is connected to the second output terminal of f4Is connected to the preset number input P, f4Third output terminal and third garbage level output terminal g3Connection, t1And a second input terminal and a second logic low levelInput terminal L2Connection, t1Is connected with the flip-flop present signal output Q, t2And a third logic low level input terminal L3And (4) connecting.
FIG. 4 is a schematic diagram of the circuit structure shown in FIG. 3 with the addition of an input signal and an output signal, where an asynchronous reset enable signal SR is input to an asynchronous reset enable signal input terminal M, a clock signal clk is input to a clock signal input terminal C, and flip-flop data T is outputgInput to the data input terminal I, and input the preset number N to the preset number input terminal P to make the first logic low level input terminal L1A second logic low level input terminal L2A third logic low level input terminal L3Are all connected with logic '0', and the signal output by the current signal output end Q of the trigger is recorded as QCT. When the asynchronous set enable signal SR is logic high level, i.e. logic' 14The output value of the second output terminal is a preset number N, f1Has an output value of logic "0", so that f2Input value sum f of the first input terminal of3Is all logic '0', thereby causing Q to be equalCTQ, regardless of whether the clock signal clk makes a transition or notCTThe preset number N is kept unchanged, so that the function of asynchronous number setting is realized. When the asynchronous set enable signal SR is logic low level, i.e. logic' 02Input value sum f of the first input terminal of3Is equal to the clock signal clk, f4The input value of the first input terminal of (a) is logic "0"; if the clock signal clk is logic high, i.e. logic "1", then t is asserted2,f3,f4The latch circuit is in data receiving state, and the received data is t0Output value Q of the second output terminaln，
Figure BDA0002900559460000071
And is dependent on the flip-flop data TgIs continuously updated by t1,f2The latch circuit is in latch state to ensure QCTDon' T follow trigger data TgIs changed by(ii) a If the clock signal clk changes from logic high to logic low, i.e. from logic "1" to logic "0", then t is the integer2,f3,f4The latch circuit is configured to transition from a data receiving state to a latching state, where the latched data is the time t at which the clock signal clk is going to transition from a logic high level to a logic low level0Output value Q of the second output terminalnFrom t to1,f2The latch circuit is configured to change from a latched state to a data receiving state, the received data being represented by t2,f3,f4The formed latch circuit latches data; if the clock signal clk changes from logic low to logic high, i.e. from logic "0" to logic "1", as time goes on, t is counted1,f2The latch circuit is configured to change from a data receiving state to a latching state, the latched data being QCTFrom t to2,f3,f4The latch circuit is in the data receiving state again, and the received data is t0Output value Q of the second output terminalnThe function of a single-edge T trigger is realized; wherein, the symbol
Figure BDA0002900559460000081
Is an exclusive or operation sign.
The reversible single-edge T trigger capable of asynchronously setting the number is subjected to a function simulation experiment.
After modeling the circuit behavior of the Feynman and Fredkin reversible logic gates in verilog hdl language, the circuit shown in fig. 4 was functionally simulated, the functional simulation results are shown in fig. 5, and it can be seen from fig. 5 that Q isCTWith asynchronous set enable signal SR, preset number N, clock signal clk, flip-flop data TgThe logic function between them is in accordance with the logic function of the reversible single-edge T trigger of asynchronous register. Since the signal name with subscript is not supported by the emulation software, the signal QCT in FIG. 5 corresponds to Q in FIG. 4CTTg in FIG. 5 corresponds to T in FIG. 4g。

Claims (2)

1. A reversible single-edge T flip-flop capable of asynchronously setting number,the reversible single-edge T flip-flop is characterized by comprising 3 Feynman reversible logic gates and 4 Fredkin reversible logic gates, wherein the 3 Feynman reversible logic gates are respectively recorded as T0、t1And t2Will t0、t1And t2Respective control input terminal as first input terminal, let t0、t1And t2Respective target input terminal as second input terminal, let t0、t1And t2Respective control output terminal as the first output terminal, and t0、t1And t2Respective target output terminal as second output terminal at t0、t1And t2The output value of the first output terminal is equal to the input value of the first input terminal, and the output value of the second output terminal is equal to the logical exclusive-or of the input value of the first input terminal and the input value of the second input terminal; the 4 Fredkin reversible logic gates are respectively recorded as f1、f2、f3And f4A 1 is to f1、f2、f3And f4Respective control input terminal as first input terminal, f1、f2、f3And f4Respective first target input terminal as second input terminal, and f1、f2、f3And f4Respective second target input terminal as third input terminal, and f1、f2、f3And f4Respective control output terminal as the first output terminal, and f1、f2、f3And f4Respective first target output terminal as second output terminal, and f1、f2、f3And f4Respective second target output terminal as third output terminal at f1、f2、f3And f4In each case, the output value of the first output terminal is equal to the input value of the first input terminal, the output value of the second output terminal is equal to the input value of the second input terminal and the output value of the third output terminal is equal to the input value of the third input terminal when the input value of the first input terminal is "0", the output value of the second output terminal is equal to the input value of the third input terminal and the output value of the third output terminal is equal to the input value of the third input terminal when the input value of the first input terminal is "1The output value is equal to the input value of the second input end;
the reversible single-edge T flip-flop comprises an asynchronous digital enable signal input end M, a clock signal input end C, a data input end I, a digital preset input end P, and a first logic low level input end L1A second logic low level input terminal L2A third logic low level input terminal L3And an asynchronous setting enable signal output end M', a trigger present signal output end Q and a first garbage position output end g1And a second garbage position output end g2And a third garbage position output end g32 signal output terminals O for outputting clock signals or logic low level signals1And O2(ii) a In the reversible single-edge T flip-flop, a logic low level is represented by "0", a logic high level is represented by "1", and Q is setnIndicating a flip-flop substate;
in the reversible single-edge T flip-flop, T0First input terminal and t1Is connected to a second output terminal t0Is connected to the data input I, t0First output terminal and f2Is connected to the second input terminal of t0Second output terminal of and f3Is connected with the second input end of the trigger, and the trigger is in a secondary state QnAt t0And f is a second output terminal and3on the second input of (f)1First input terminal and f4Is connected to the first output terminal of f1And a first logic low level input terminal L1Connection of f1Is connected to the clock signal input C, f1Is connected with an asynchronous setting enable signal output M', f1And one of the signal output terminals O for outputting a clock signal or a logic low level signal1Connection of f1Third output terminal of (d) and f3Is connected to the first input terminal of f2First input terminal and f3Is connected to the first output terminal of f2Third input terminal of and t2Is connected to the first output terminal of f2And another signal output terminal O for outputting a clock signal or a logic low level signal2The connection is carried out by connecting the two parts,f2second output terminal and first garbage level output terminal g1Connection of f2Third output terminal and t1Is connected to the first input terminal of f3Third input terminal of (d) and f4Is connected to the second output terminal of f3Second output terminal and second garbage level output terminal g2Connection of f3Third output terminal and t2Is connected to the first input terminal of f4Is connected to an asynchronous set-number enable signal input M, f4Second input terminal and t2Is connected to the second output terminal of f4Is connected to the preset number input P, f4Third output terminal and third garbage level output terminal g3Connection, t1And a second logic low level input terminal L2Connection, t1Is connected with the flip-flop present signal output Q, t2And a third logic low level input terminal L3And (4) connecting.
2. The reversible single-edge T flip-flop capable of being asynchronously clocked according to claim 1, wherein the asynchronous clock enable signal SR is inputted to the asynchronous clock enable signal input terminal M, the clock signal clk is inputted to the clock signal input terminal C, and the flip-flop data T is inputtedgInput to the data input terminal I, and input the preset number N to the preset number input terminal P to make the first logic low level input terminal L1A second logic low level input terminal L2A third logic low level input terminal L3Are all connected with logic '0', and the signal output by the current signal output end Q of the trigger is recorded as QCT；
When the asynchronous set enable signal SR is logic high level, i.e. logic' 14The output value of the second output terminal is a preset number N, f1Has an output value of logic "0", so that f2Input value sum f of the first input terminal of3Is all logic '0', thereby causing Q to be equalCTThe function of asynchronous number setting is realized;
when the asynchronous set enable signal SR is logic lowAt a level, i.e. logic "0", f2Input value sum f of the first input terminal of3Is equal to the clock signal clk, f4The input value of the first input terminal of (a) is logic "0"; if the clock signal clk is logic high, i.e. logic "1", then t is asserted2,f3,f4The latch circuit is in data receiving state, and the received data is t0Output value Q of the second output terminaln，
Figure FDA0002900559450000031
And is dependent on the flip-flop data TgIs continuously updated by t1,f2The latch circuit is in latch state to ensure QCTDon' T follow trigger data TgIs changed; if the clock signal clk changes from logic high to logic low, i.e. from logic "1" to logic "0", then t is the integer2,f3,f4The latch circuit is configured to transition from a data receiving state to a latching state, where the latched data is the time t at which the clock signal clk is going to transition from a logic high level to a logic low level0Output value Q of the second output terminalnFrom t to1,f2The latch circuit is configured to change from a latched state to a data receiving state, the received data being represented by t2,f3,f4The formed latch circuit latches data; if the clock signal clk changes from logic low to logic high, i.e. from logic "0" to logic "1", as time goes on, t is counted1,f2The latch circuit is configured to change from a data receiving state to a latching state, the latched data being QCTFrom t to2,f3,f4The latch circuit is in the data receiving state again, and the received data is t0Output value Q of the second output terminalnThe function of a single-edge T trigger is realized; wherein, the symbol
Figure FDA0002900559450000032
Is an exclusive or operation sign.
CN202110055794.1A 2021-01-15 2021-01-15 Reversible single-edge T trigger capable of asynchronously setting number Active CN112865758B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110055794.1A CN112865758B (en) 2021-01-15 2021-01-15 Reversible single-edge T trigger capable of asynchronously setting number

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110055794.1A CN112865758B (en) 2021-01-15 2021-01-15 Reversible single-edge T trigger capable of asynchronously setting number

Publications (2)

Publication Number Publication Date
CN112865758A CN112865758A (en) 2021-05-28
CN112865758B true CN112865758B (en) 2022-03-29

Family

ID=76005789

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110055794.1A Active CN112865758B (en) 2021-01-15 2021-01-15 Reversible single-edge T trigger capable of asynchronously setting number

Country Status (1)

Country Link
CN (1) CN112865758B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7427876B1 (en) * 2007-03-19 2008-09-23 National Tsing Hua University Reversible sequential element and reversible sequential circuit thereof
CN102983841A (en) * 2012-12-20 2013-03-20 上海工程技术大学 Reversible master-slave RS flip-flop based on reversible logical gate
CN109687848A (en) * 2018-11-28 2019-04-26 宁波大学 A kind of reversible trigger and its configuration method that logic function is configurable

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432738B1 (en) * 2007-03-28 2008-10-07 National Tsing Hua University Reversible sequential apparatuses

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7427876B1 (en) * 2007-03-19 2008-09-23 National Tsing Hua University Reversible sequential element and reversible sequential circuit thereof
CN102983841A (en) * 2012-12-20 2013-03-20 上海工程技术大学 Reversible master-slave RS flip-flop based on reversible logical gate
CN109687848A (en) * 2018-11-28 2019-04-26 宁波大学 A kind of reversible trigger and its configuration method that logic function is configurable

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Design of fault tolearnt full Adder/Subtarctor using reversible gates;Parminder Kaur;《2012 International Conference on Computer Communication and Informatics》;20120301;1-5 *
可逆双边沿触发器的设计;张莹;《宁波大学学报(理工版)》;20181231;45-50 *

Also Published As

Publication number Publication date
CN112865758A (en) 2021-05-28

Similar Documents

Publication Publication Date Title
US8291358B2 (en) Synchronous to asynchronous logic conversion
CN109687848B (en) Reversible trigger with configurable logic function and configuration method thereof
US6720813B1 (en) Dual edge-triggered flip-flop design with asynchronous programmable reset
Arora The art of hardware architecture: Design methods and techniques for digital circuits
US7432738B1 (en) Reversible sequential apparatuses
US20030030474A1 (en) Master-slave flip-flop with non-skewed complementary outputs, and methods to operate and manufacture the same
CN112910441B (en) Reversible double-edge JK trigger capable of asynchronously setting number
Saha et al. Low‐power 6‐GHz wave‐pipelined 8b× 8b multiplier
CN112865757B (en) Logic function configurable reversible single edge trigger
CN112865758B (en) Reversible single-edge T trigger capable of asynchronously setting number
US7427876B1 (en) Reversible sequential element and reversible sequential circuit thereof
CN112910444B (en) Reversible single-edge D trigger capable of asynchronously setting number
CN112910440B (en) Reversible double-edge T trigger capable of asynchronously setting number
CN112865756B (en) Reversible double-edge D trigger capable of asynchronously setting number
CN112910454B (en) Reversible single-edge JK trigger capable of asynchronously setting number
CN112910442B (en) Reversible double-edge trigger with configurable logic function
Munratiwar et al. Design of high speed 8-bit magnitude comparator for security application
Ghose et al. Design of reversible shift registers minimizing number of gates, constant inputs and garbage outputs
Metku et al. Novel area-efficient null convention logic based on cmos and gate diffusion input (Gdi) hybrid
Hoyer et al. Locally clocked pipelines and dynamic logic
Jahangir et al. Design of quaternary sequential circuits using a newly proposed quaternary algebra
US20080215941A1 (en) Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications
CN104038184B (en) A kind of QETFF circuit unit based on CMOS technology
Jou et al. Low-power globally asynchronous locally synchronous design using self-timed circuit technology
Chiwande et al. VHDL Implementation of Low Power Sequential Circuits using Reversible Logic

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant