CN116050327A - Scan test register chain with checking function - Google Patents

Abstract

The invention discloses a scan test register chain with a verification function, which belongs to the field of testability design and comprises a plurality of registers which are connected in series and have the verification function; each register with the verification function comprises a PI port, an SI port, a CEN port, a SEN port, an S port, a CK port, a CKN port and a Y port, wherein the Y port of the former stage register is connected with the SI port of the latter stage register in series; the scan test register chain is used as a data readback circuit for testability design, the circuit to be tested generates response after being stimulated, the circuit response is read out through the scan test register chain, then the result is compared with a target result, and finally the comparison result is serially output to the chip port. The invention is used for grabbing the test result inside the test circuit and comparing the test result with the target result, and then outputting the verification result outside the chip, thereby improving the test efficiency of the circuit and reducing the hardware resource expenditure.

Description

Scan test register chain with checking function

Technical Field

The invention relates to the technical field of testability design, in particular to a scan test register chain with a verification function.

Background

The testability design technology is to reduce the test difficulty and test cost of the chip by effectively adding a test circuit on the basis of meeting the normal functions of the chip.

For large-scale integrated circuit design projects, the design for testability is increased in the stage of integrated circuit design, so that the time for test development can be shortened, the test cost can be reduced, and the test coverage can be evaluated in advance. Controllability and observability are the most fundamental two features in circuit design for testability. Controllability means that all states of the circuit are guaranteed to be controllable and the circuit is easily controlled by applying test patterns; observability means that the response of the circuit can be conveniently detected and verified.

Disclosure of Invention

The invention aims to provide a scan test register chain with a verification function, which is used for solving the problems in the background technology.

In order to solve the technical problems, the invention provides a scan test register chain with a verification function, which comprises a plurality of registers which are connected in series and have the verification function; each register with the verification function comprises a PI port, an SI port, a CEN port, a SEN port, an S port, a CK port, a CKN port and a Y port, wherein the Y port of the former stage register is connected with the SI port of the latter stage register in series;

the scan test register chain is used as a data readback circuit for testability design, the circuit to be tested generates response after being stimulated, the circuit response is read out through the scan test register chain, then the result is compared with a target result, and finally the comparison result is serially output to the chip port.

In one embodiment, when the sel signal of the S port in the register is '1' and the shift_en signal of the SEN port is '1', the scan test register chain is in a Serial transmission data state, at this time, the target result data is transmitted to the scan test register chain through the serial_in signal of the SI port by the control clock clk of the CK port, after all n bits of data are transmitted to the scan test register chain, the sel signal of the S port is switched to "0", and the target result data of the circuit to be tested is latched in each register in the scan test register chain;

the capture_en signal of the CEN port is set to '0', the scan test register chain is switched to the Parallel input mode, at this time, all test circuit response data is read into the scan test register chain through the parallel_d0 to parallel_dn signals of each PI port, the shift_en signal of the SEN port is set to '0', the scan test register chain is switched to the data verification mode, the response data of the test circuit is automatically compared with the target result data, and if the response is consistent with the target result, a '1' is output, and if the response is inconsistent with the target result, a '0' is output. The sel signal of the S port is set to be '1', the control clock clk reads the verification result into the next-stage register, the shift_EN signal of the SEN port is set to be '1', the scan test register chain is switched to the serial transmission data state again, and the control clock clk transmits all the verification results to the chip port.

In one embodiment, the register with the verification function comprises a parallel data reading circuit, a serial data transmission register and a data verification circuit; and the parallel data reading circuit and the serial data transmission register transmit data to the data verification circuit for verification and output.

In one embodiment, the parallel data read-in circuit includes a first not gate and a first nor gate, where an input end of the first not gate inputs parallel data PI, and an output end of the first not gate is connected to one input end of the first nor gate; the other input end of the first NOR gate is a CEN port, and the output end of the first NOR gate is connected to the data verification circuit;

when the signal of the CEN port is set to be 0', the parallel data reading circuit is effective, and the parallel data PI reading circuit is used for reading the parallel data; when the signal of the CEN port is '1', the parallel data read-in circuit is invalid.

In one embodiment, the serial data transfer register includes a selector MUX and a register; one input end of the selector MUX inputs serial data SI, and the other input end is connected with the output end of the register; the output end of the selector MUX is connected with the D end of the register; the output end of the register is connected with the data verification circuit;

when the signal of the S port of the selector MUX is set as '1', and the signal of the SN port is set as '0', the serial data transmission register is switched to a serial data transmission mode, the selector MUX gates a second path, and data is transmitted in series under the pushing of a shift clock CK; on the one hand, external data can be transmitted into the scan test register chain through the serial data transmission register, and on the other hand, the data in the scan test register chain can be output out of the data chain through the serial data transmission register;

when the signal of the S port of the selector MUX is set to '0' and the signal of the SN port is set to '1', the serial data transfer register is switched to the data latch mode, and the data Q is latched.

In one embodiment, the data verification circuit includes a second NOT gate, a second NOR gate, a transmission gate, a PMOS tube and an NMOS tube; one input end of the second NOR gate is connected with the output end of the parallel data reading circuit, the other end of the second NOR gate is an EN port, and a check control signal is input; the output end of the second NOR gate is connected with the input end of the transmission gate, the grid electrode of the PMOS tube and the grid electrode of the NMOS tube at the same time; one end of the control end of the transmission gate is connected with the output end of the serial data transmission register, the input end of the second NOT gate and the source electrode of the PMOS tube, and the other end of the control end is connected with the output end of the second NOT gate and the source electrode of the NMOS tube; the output end of the transmission gate is connected with the drain electrode of the PMOS tube and the drain electrode of the NMOS tube and is used as the output of the scan test register chain;

when the check control signal of the EN port is set to '1', the serial data transmission mode is set, i.e. z=a2; when the check control signal of the EN port is set to '0', the data check mode, A1 and A2 are exclusive-ored, i.e., z=a1+a2.

The scan test register chain with the verification function is used for capturing the test result inside the test circuit and comparing the test result with the target result, and then outputting the verification result to the outside of the chip, so that the test efficiency of the circuit can be improved, and the hardware resource expenditure can be reduced.

Drawings

FIG. 1 is a schematic diagram of a scan test register chain with a verification function.

Fig. 2 is a schematic diagram of the structure of a single register with a verification function.

Fig. 3 is a schematic diagram of a serial data transfer register.

Fig. 4 is a schematic diagram of a data verification circuit.

Detailed Description

The following describes a scan test register chain with verification function in further detail with reference to the drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

The invention provides a scan test register chain with a verification function, which comprises a plurality of registers which are connected in series and have the verification function, as shown in figure 1, each register with the verification function comprises a PI port, an SI port, a CEN port, a SEN port, an S port, a CK port, a CKN port and a Y port, wherein the Y port of a former stage register is connected in series with the SI port of a latter stage register. The testability designed data read-back circuit can adopt the scan test register chain; the circuit to be tested generates response after being excited, the circuit response can be read out through the scanning test register chain, then the circuit is compared with a target result, and finally the comparison result is serially output to the chip port.

In the scan test register chain with the verification function, when the sel signal of each register S port is '1' and the shift_en signal of the SEN port is '1', the scan test register chain is in a Serial transmission data state, at this time, the target result data can be transmitted to the scan test register chain through the serial_in signal of the SI port by the control clock clk of the CK port (clk_n is the inversion signal of clk), and after all n bits of data are transmitted to the scan test register chain, the sel signal of the S port is switched to "0", and the target result data of the circuit to be tested is latched in each register in the scan test register chain. The Capture _ EN signal of the CEN port is set to '0' and the scan test register chain is switched to parallel input mode. At this time, all test circuit response data is read into the scan test register chain by the parallel_d0 to parallel_dn signals of the PI ports. The shift_en signal of the SEN port is set to '0', the scan test register chain is switched to a data check mode, response data of the test circuit is automatically compared with target result data, if the response is consistent with the target result, a '1' is output, and if the response is inconsistent with the target result, a '0' is output. The sel signal of the S port is set to be '1', the control clock clk reads the verification result into the next stage register, the shift_EN signal of the SEN port is set to be '1', the scan test register chain is switched to the serial transmission data state again, and the control clock clk can transmit all the verification results to the chip port.

The single register with verification function in the scan test register chain is shown in fig. 2, and comprises a parallel data reading circuit, a serial data transmission register and a data verification circuit. When the signal of the CEN port is set to be 0', the parallel data reading circuit is effective, and the parallel data PI reading circuit is used for reading the parallel data PI; when the signal of the CEN port is '1', the parallel data read-in circuit is invalid.

As shown in fig. 3, when the signal of the S port of the selector MUX is set to '1' (the signal of the SN port is '0'), the serial data transmission register is switched to the serial data transmission mode, the selector MUX gates the second path, and the data is serially transmitted under the pushing of the shift clock CK; on the one hand, external data can be transmitted into the scan test register chain through the serial data transmission register, and on the other hand, the data in the scan test register chain can be output to the outside of the data chain through the serial data transmission register; when the signal of the S port of the selector MUX is set to '0' (the signal of the SN port is '1'), the serial data transfer register switches to the data latch mode, and the data Q latches.

As shown in fig. 4, when the check control signal of the EN port is set to '1', the data A2 transmission mode, i.e., z=a2; when the check control signal of the EN port is set to '0', the data check mode, A1 and A2 are exclusive-ored, i.e., z=a1+a2.

For example, the serial data transmission register of fig. 3 is switched to the serial data transmission mode, the target data is transmitted to the inside of the scan test register chain, then the serial data transmission register is switched to the data latch mode, and the target data is latched at the Q terminal; enabling the parallel data reading circuit to read in the sampling data from the PI port and send the sampling data to the A2 end of the data checking circuit in FIG. 4; the data verification circuit in fig. 4 is switched to the data verification mode, the target data Q in fig. 3 is sent to the A1 end of the data verification circuit in fig. 4, and the Z end outputs the same or operation result of the target data A1 and the sampling data A2 through operation, if a1=a2, z= '1', otherwise, z= '0'. The serial data transmission register in fig. 3 is switched to a serial data transmission mode, the calculation result of the data verification circuit in the previous stage (n-1) is transmitted to the serial data transmission register in the current stage, the serial data transmission register in fig. 3 is switched to a data latch mode, the calculation result of the previous stage is locked at the Q end, the data verification circuit in fig. 4 is switched to an A2 data transmission mode, the parallel data reading circuit is controlled to be invalid, the serial data transmission register in fig. 3 is switched to the serial data transmission mode, the shift clock CK is controlled, and the verification result is transmitted to the outside of a data chain, so that data verification and transmission are completed.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (6)

1. The scan test register chain with the verification function is characterized by comprising a plurality of registers which are connected in series and have the verification function; each register with the verification function comprises a PI port, an SI port, a CEN port, a SEN port, an S port, a CK port, a CKN port and a Y port, wherein the Y port of the former stage register is connected with the SI port of the latter stage register in series;

the scan test register chain is used as a data readback circuit for testability design, the circuit to be tested generates response after being stimulated, the circuit response is read out through the scan test register chain, then the result is compared with a target result, and finally the comparison result is serially output to the chip port.

2. The scan test register chain with a checking function according to claim 1, wherein when the sel signal of the S port in the register is '1' and the shift_en signal of the SEN port is '1', the scan test register chain is in a Serial transmission data state, at this time, the target result data is transmitted into the scan test register chain through the serial_in signal of the SI port by the control clock clk of the CK port, and after the n-bit data is all transmitted into the scan test register chain, the sel signal of the S port is switched to "0", and the target result data of the circuit to be tested is latched into each register in the scan test register chain;

the capture_en signal of the CEN port is set to '0', the scan test register chain is switched to the Parallel input mode, at this time, all test circuit response data is read into the scan test register chain through the parallel_d0 to parallel_dn signals of each PI port, the shift_en signal of the SEN port is set to '0', the scan test register chain is switched to the data verification mode, the response data of the test circuit is automatically compared with the target result data, and if the response is consistent with the target result, a '1' is output, and if the response is inconsistent with the target result, a '0' is output. The sel signal of the S port is set to be '1', the control clock clk reads the verification result into the next-stage register, the shift_EN signal of the SEN port is set to be '1', the scan test register chain is switched to the serial transmission data state again, and the control clock clk transmits all the verification results to the chip port.

3. The scan test register chain with a checking function according to claim 1, wherein the register with a checking function comprises a parallel data read-in circuit, a serial data transmission register, and a data checking circuit; and the parallel data reading circuit and the serial data transmission register transmit data to the data verification circuit for verification and output.

4. A scan test register chain with a checking function according to claim 3, wherein the parallel data read-in circuit comprises a first nor gate and a first nor gate, the input of the first nor gate inputs parallel data PI, and the output is connected to one input of the first nor gate; the other input end of the first NOR gate is a CEN port, and the output end of the first NOR gate is connected to the data verification circuit;

when the signal of the CEN port is set to be 0', the parallel data reading circuit is effective, and the parallel data PI reading circuit is used for reading the parallel data; when the signal of the CEN port is '1', the parallel data read-in circuit is invalid.

5. A scan test register chain with a verification function as claimed in claim 3, wherein said serial data transfer register comprises a selector MUX and a register; one input end of the selector MUX inputs serial data SI, and the other input end is connected with the output end of the register; the output end of the selector MUX is connected with the D end of the register; the output end of the register is connected with the data verification circuit;

when the signal of the S port of the selector MUX is set as '1', and the signal of the SN port is set as '0', the serial data transmission register is switched to a serial data transmission mode, the selector MUX gates a second path, and data is transmitted in series under the pushing of a shift clock CK; on the one hand, external data can be transmitted into the scan test register chain through the serial data transmission register, and on the other hand, the data in the scan test register chain can be output out of the data chain through the serial data transmission register;

when the signal of the S port of the selector MUX is set to '0' and the signal of the SN port is set to '1', the serial data transfer register is switched to the data latch mode, and the data Q is latched.

6. The scan test register chain with a checking function according to claim 3, wherein the data checking circuit comprises a second NOT gate, a second NOR gate, a transmission gate, a PMOS tube and an NMOS tube; one input end of the second NOR gate is connected with the output end of the parallel data reading circuit, the other end of the second NOR gate is an EN port, and a check control signal is input; the output end of the second NOR gate is connected with the input end of the transmission gate, the grid electrode of the PMOS tube and the grid electrode of the NMOS tube at the same time; one end of the control end of the transmission gate is connected with the output end of the serial data transmission register, the input end of the second NOT gate and the source electrode of the PMOS tube, and the other end of the control end is connected with the output end of the second NOT gate and the source electrode of the NMOS tube; the output end of the transmission gate is connected with the drain electrode of the PMOS tube and the drain electrode of the NMOS tube and is used as the output of the scan test register chain;

when the check control signal of the EN port is set to '1', the serial data transmission mode is set, i.e. z=a2; when the check control signal of the EN port is set to '0', the data check mode, A1 and A2 are exclusive-ored, i.e., z=a1+a2.

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