CN110007897A - Logic gate, logic circuit and calculation method based on resistance-variable storing device - Google Patents
Logic gate, logic circuit and calculation method based on resistance-variable storing device Download PDFInfo
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- CN110007897A CN110007897A CN201910205303.XA CN201910205303A CN110007897A CN 110007897 A CN110007897 A CN 110007897A CN 201910205303 A CN201910205303 A CN 201910205303A CN 110007897 A CN110007897 A CN 110007897A
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
- G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
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Abstract
The invention discloses logic gate, logic circuit and calculation methods based on resistance-variable storing device.The logic gate includes variable-resistance memory unit, divider resistance, one end of the variable-resistance memory unit and one end of the divider resistance are commonly connected to the voltage output end of circuit, for the other end of the variable-resistance memory unit for being grounded or for input signal, the other end of the divider resistance is voltage input end；The variable-resistance memory unit includes the resistance-variable storing device of one or more serial or parallel connections together, the low resistance state resistance value of the resistance-variable storing device is much smaller than the resistance value of the divider resistance, and the high-resistance resistors value of the resistance-variable storing device is much larger than the resistance value of the divider resistance.The logic circuit is based on the logic gate.The calculation method is based on the logic gate or the logic circuit.The present invention can maximally reduction circuit operation step number, while reducing the complexity of logical unit peripheral control unit.
Description
Technical field
The present invention relates to logical operation technical fields, in particular to logic gate, logic circuit based on resistance-variable storing device and
Calculation method.
Background technique
In the prior art, logical operation is carried out using resistance-variable storing device be mainly the following method:
1) IMPLY logic
Logic if then operation was proposed by Julien Borghetti of HP Lab et al. in 2010 at first, was please referred to
Document [1], this is that resistance-variable storing device is found to have the ability for realizing complete logical operation for the first time.Basic circuit as shown in Figure 1, P,
Q is resistance-variable storing device, RGFor resistance, RGIt is resistor satisfied: Rclose< < RG< < Ropen.The high resistant of circuit resistance-variable storing device
State indicates logical zero, and low resistive state indicates logic 1.When work, the upper end P, Q applies Vcond, Vset voltage respectively, due to P two
Voltage is held to be less than Vcond, so the state of P remains unchanged, when P is in high-impedance state (logical zero), resistance RGOn partial pressure it is close
It is approximately equal to Vset like for the voltage at the both ends 0, Q, resistance-variable storing device Q is unconditionally set to low resistive state (logic 1).When P is in low
(logic 1), R when resistance stateGOn partial pressure be approximately Vcond, the voltage at the both ends Q is approximately equal to Vset-Vcond, this voltage be less than make
The threshold voltage that resistance-variable storing device state changes, guarantees that the state of Q remains unchanged.The truth table of if then operation is as shown in Table 1:
One truth table of table
PIMPq is equivalent to realizationOperation, which is logically complete.More in-depth study shows
Using the if then operation of resistance-variable storing device, regardless of how many is a for input resistance-variable storing device, it is only necessary to 2+m work resistance-variable storing device
The function that can realize a m output circuit please refers to document [2], and realizes arbitrary basic Boolean logic and only need two
A work resistance-variable storing device, please refers to document [3], can greatly reduce the area of circuit using logic is contained.However, containing
It is to sacrifice the considerable time as cost that logic completes logical operation under extremely low hardware spending.Since if then operation is
0,1 two kind of logic is indicated with the resistance sizes of resistance-variable storing device, and resistance cannot facilitate in circuit as voltage and current
Ground conduction, causes the circuit based on if then operation to can be only done single stepping inside a clock, and since logic is to make
It is indicated with resistance sizes, so being difficult to carry out the transmission of signal between circuit, leads to the more difficult concurrent operation of circuit.Logic is accumulate
It is substantially the reduction for sacrificing arithmetic speed to exchange hardware for containing operation.
There are many being suggested based on the simple operation circuit for containing logic realization, such as adder please refers to document [4],
As most basic arithmetic operation unit, the add operation that the adder that resistance-variable storing device is built completes one one needs 19
Clock, this is cannot be received.For improving operational speed, a variety of logic synthesis methods, which are suggested to reduce, to be based on containing patrolling
The operation step number for collecting circuit please refers to document [5] and [6], but since resistance transmitting information is not as good as voltage and current transmitting information
Convenient, this is difficult to the status for changing the operation step number that if then operation needs to grow very much.
2) modified IMPLY logic
Kang Jinfeng et al. published an article on " Advanced Materials " in 2016 propose it is a kind of new based on resistance
The logical operation method of transition storage please refers to document [7], this logical operation may be implemented logical AND operation and with non-behaviour
Make, be logically it is complete, arbitrary logical function may be implemented.It is defeated shown in specific logic gate such as Fig. 2 (a) and Fig. 2 (b)
Enter for the size of input terminal resistance-variable storing device resistance value, output is stored in output end resistance-variable storing device with the resistance value of resistance-variable storing device
On, all resistance-variable storing devices are connect on same common end by WL, and resistance RC is load resistance (Rclose< < RC< < Ropen)。
As Fig. 2 (a) exports resistance-variable storing device Y and be set to high resistant first, VR is terminated under A, B resistance-variable storing device, is terminated under Y for NAND gate
Ground ground, load resistance RC right end meet VDD, if A, B are high-impedance state (logic 1), the voltage on the WL of common end is about etc.
Low resistive state (logical zero) will be set in VDD, Y.If A, B has one for low resistive state, the voltage on the WL of common end is approximately equal to
The undertension at the both ends VR, resistance-variable storing device Y is kept high-impedance state (logic 1) with changing its logic state.Such as Fig. 2 (b),
For with door, circuit structure is similar, but VDD is terminated under A, B, and load resistance right end meets VR, and resistance-variable storing device Y is first set to height
Resistance state, when A, B are high-impedance state, the voltage on the WL of common end is approximately equal to VR, the undertension at the both ends resistance-variable storing device Y
To change its state, keep high-impedance state (logic 1).When have in A, B at least one resistance-variable storing device be low resistive state (logic
0), the voltage on the WL of common end is approximately equal to VDD, and resistance-variable storing device Y will be set to low resistive state (logical zero).Using this logic wind
The one-bit full addres of lattice design need the operation of 10 steps, reduce considerable operation step number compared to IMPLY logic.The electricity simultaneously
Road can integrate in crossed array, but since this same input and output of logic implementation method are all using resistance-variable storing device
Resistance value indicate different logic states, cause the operation step number equally very long, the transmitting of signal is equally relatively more tired between circuit
It is difficult.
3) MAGIC logic
Shahar Kvatinsky et al. proposed a kind of novel logical operation side based on resistance-variable storing device in 2014
Method (Memristor-Aided Logic), please refers to document [8], Fig. 3 (a) and Fig. 3 (b) provide realize in this way or
Door and the circuit diagram with door, the high low resistance state of circuit input state resistance-variable storing device indicate, export with resistance-variable storing device
Resistance value size be stored in output end resistance-variable storing device.Output end resistance-variable storing device is set to high-impedance state (logical zero) first,
When the switch is closed, according to the resistance value of input terminal resistance-variable storing device, output end resistance-variable storing device can obtain different voltage, thus
The switching of realization state.Such as shown in Fig. 3 (a) or door, when two input resistance-variable storing device at least one resistives are deposited
When reservoir is in low resistive state (logic 1), partial pressure of the V0 on output end resistance-variable storing device can make it be transformed into low-resistance shape
State, otherwise, output end resistance-variable storing device state remain unchanged, thus realization or operation.Similarly may be implemented it is non-or non-, and it is non-
Equal operations, and input port can extend.
It is all to be indicated by the resistance value of resistance-variable storing device, and be limited to since this logic implementation method is output and input
The connection type of circuit, this circuit are difficult to be cascaded.While in order to protect input terminal resistance-variable storing device after the completion of operation
State is not changed, and the requirement to different logic gate input terminal voltage V0 is different, and this greatly limits the freedom of design
Degree, while the fluctuation of voltage is easy to cause the mistake of calculated result.
4) class MOS structure circuit
Vourkas et al. proposed a kind of method for constructing similar cmos circuit with resistance-variable storing device in 2012, please referred to
Document [9], the resistance-variable storing device of circuit forward bias replace NMOS transistor, with the resistance-variable storing device of reverse bias come table
Show that PMOS transistor, structure are as shown in Figure 4.Each resistance-variable storing device changes resistance value shape by input signal in circuit
Whether state, the resistance-variable storing device of top half anode upward access Vdd signal similar to PMOS transistor control output end, and lower end is negative
Whether the resistance-variable storing device of end upward is connected to ground similar to NMOS transistor control output end.Final output voltage swing passes through Vdd
In lower half portion, the partial pressure of resistance-variable storing device equivalent resistance is obtained.
This logic implementation method arithmetic speed is many fastly compared to the logics implementation method such as IMPLY, and circuit design
Method is similar with conventional CMOS circuit design method, can greatly reduce the complexity of circuit design, and circuit is passed with voltage
Delivery signal indicates that the method for logic is consistent with traditional circuit, and circuit is allow to carry out operation parallel.But due to resistance-variable storing device
Unit be all state conversion is carried out by positive back bias voltage, and output voltage range be between Vdd to 0, so circuit without
Method is cascaded, this needs increasingly complex peripheral circuit just to control the conversion of resistance-variable storing device state.Meanwhile for difference
Logic function, class PMOS module and class NMOS module equivalent resistance are all different, cause output voltage fluctuation it is larger.
Summary of the invention
The purpose of the invention is to make up above-mentioned at least one deficiency in the prior art, propose to be based on resistance-variable storing device
Logic gate, logic circuit and calculation method.
In order to solve the above technical problems, the invention adopts the following technical scheme:
Logic gate based on resistance-variable storing device, including variable-resistance memory unit, divider resistance, the one of the variable-resistance memory unit
End and one end of the divider resistance are commonly connected to the voltage output end of circuit, and the other end of the variable-resistance memory unit is used for
Ground connection is used for input signal, and the other end of the divider resistance is voltage input end；The variable-resistance memory unit includes one
The resistance-variable storing device of a or multiple serial or parallel connections together, the low resistance state resistance value of the resistance-variable storing device is much smaller than described point
The resistance value of piezoresistance, the high-resistance resistors value of the resistance-variable storing device are much larger than the resistance value of the divider resistance.
In some preferred embodiments, the quantity of the resistance-variable storing device being connected in parallel is less than or equal to 11,
The quantity of the resistance-variable storing device being cascaded is less than or equal to 6.
In some preferred embodiments, the anode of the variable-resistance memory unit and one end of the divider resistance are common
It is connected to the voltage output end of circuit, the negative terminal of the variable-resistance memory unit is for being grounded or for input signal；Alternatively, institute
One end of the negative terminal and the divider resistance of stating variable-resistance memory unit is commonly connected to the voltage output end of circuit, and the resistive is deposited
The anode of storage unit is for being grounded or for input signal.
On the other hand, the present invention provides the calculation method based on above-mentioned logic gate, comprising:
According to the logic of input signal, the resistance value state of the resistance-variable storing device is rewritten, so that at the resistance-variable storing device
In high-impedance state or low resistive state；
Make the input voltage V for being input to the voltage input endinMeet Vin< min (| Vopen|,Vclose), wherein Vopen
For the resistance-variable storing device from low resistive state jump be high-impedance state threshold voltage, VcloseIndicate the resistance-variable storing device from height
Hinder the threshold voltage that state transition is low resistive state；
The logical consequence of the logic gate output is determined according to the partial pressure on the equivalent resistance of the variable-resistance memory unit.
In some preferred embodiments, the resistance value state for rewriting the resistance-variable storing device specifically: make described
One end input voltage V of resistance-variable storing devicep, other end ground connection, wherein Vp> max (| Vopen|,Vclose)。
On the other hand, the present invention provides the logic circuit based on resistance-variable storing device, including multi-level pmultistage circuit array, the electricity
Road array includes multiple above-mentioned logic gates；In gate array described in the voltage output end and next stage of gate array described in upper level
Resistance-variable storing device connection, to rewrite the resistance value state of the resistance-variable storing device in gate array described in next stage.
In some preferred embodiments, the operation mode of the logic gate include with or it is non-.
In some preferred embodiments, the quantity of the gate array is two-stage or three-level or more.
On the other hand, the present invention also proposes a kind of calculation method based on above-mentioned logic circuit, comprising:
Initial value is set to the resistance-variable storing device of the gate array；
Make to be input to the input voltage V of the voltage input end of gate array described in the first orderinMeet Vin< min (| Vopen|,
Vclose), wherein VopenFor the resistance-variable storing device from low resistive state jump be high-impedance state threshold voltage, VcloseIndicate institute
Threshold voltage of the resistance-variable storing device from high-impedance state jump for low resistive state is stated, so that the logic in gate array described in the first order
Door carries out logical operation；
The resistive in gate array described in next stage is rewritten using the logic operation result of gate array described in upper level to deposit
The resistance value state of reservoir exports final operation result so that the logic gate in gate array described in next stage carries out logical operation.
On the other hand, it the present invention also provides a kind of computer readable storage medium, is stored with and calculates in conjunction with equipment
The computer program used, the computer program can be executed by processor to realize the above method.
Compared with prior art, the beneficial effects of the present invention are as follows:
Constitute potential-divider network based on resistance-variable storing device and complete complicated logical operation, wherein with or the logics such as non-transport
Calculation can synchronously complete operation, provide parallel logic door implementation a kind of that output is voltage and that logic function is complete, most
The operation step number of the earth reduction circuit, while reducing the complexity of logical unit peripheral control unit.It is realized in array big
While the digital circuit of scale, the delay of operation can be shortened.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of IMPLY logic circuit in the prior art；
Fig. 2 (a) is the structural schematic diagram of the NAND gate circuit of modified IMPLY logic in the prior art；
Fig. 2 (b) is the structural schematic diagram of the AND gate circuit of modified IMPLY logic in the prior art；
Fig. 3 (a) is the structural schematic diagram of the OR circuit of MAGIC logic in the prior art；
Fig. 3 (b) is the structural schematic diagram of the AND gate circuit of MAGIC logic in the prior art；
Fig. 4 is the structural schematic diagram of class MOS structure circuit in the prior art；
Fig. 5 is the structural schematic diagram of the not circuit of the embodiment of the present invention；
Fig. 6 is the simulation result of the not circuit of the embodiment of the present invention；
Fig. 7 is the structural schematic diagram of the OR-NOT circuit of the embodiment of the present invention；
Fig. 8 is the simulation result of the OR-NOT circuit of the embodiment of the present invention；
Fig. 9 is the structural schematic diagram of the NAND gate circuit of the embodiment of the present invention；
Figure 10 is the simulation result of the NAND gate circuit of the embodiment of the present invention；
Figure 11 is the structural schematic diagram of the AND gate circuit of the embodiment of the present invention；
Figure 12 is the simulation result of the AND gate circuit of the embodiment of the present invention；
Figure 13 is the structural schematic diagram of the OR circuit of the embodiment of the present invention；
Figure 14 is the simulation result of the OR circuit of the embodiment of the present invention；
Figure 15 is the structural schematic diagram of m high-impedance state resistance-variable storing device parallel circuit of the embodiment of the present invention；
Figure 16 is the structural schematic diagram of n low resistive state resistance-variable storing device series circuit of the embodiment of the present invention；
Figure 17 is the structural schematic diagram for the logic circuit that the embodiment of the present invention realizes full adder circuit inside array；
Figure 18 is that the embodiment of the present invention realizes that the structure of the logic circuit of benchmark Schaltkreis d53f2 is shown inside array
It is intended to.
Specific embodiment
With reference to Fig. 5 to Figure 18, elaborate below to embodiments of the present invention.It is emphasized that following the description
It is only exemplary, the range and its application being not intended to be limiting of the invention.
Logic gate of the embodiment of the present invention based on resistance-variable storing device is following logic gates or following logic gates
Circuit after circuit extension.
The logic gates of the embodiment of the present invention include not circuit, OR-NOT circuit, NAND gate circuit, AND gate circuit and
OR circuit.
Not circuit namely NOT logic gate circuit are that resistance-variable storing device is realized as potential-divider network.
NOT logic gate circuit is as shown in figure 5, variable-resistance memory unit is a resistance-variable storing device A, the divider resistance R of left upper end
Resistance value between the high-resistance resistors value Roff and low resistance state resistance value Ron of resistance-variable storing device A.Divider resistance R and resistive are deposited
The common end of reservoir A connection is output end, and the other end of divider resistance R is input terminal, the positive ending grounding of resistance-variable storing device A.Work
When making, first passes through input signal and unified rewriting is carried out to the resistance value state of resistance-variable storing device A, it is right when input signal is logic 1
The upper end of the resistance-variable storing device A of rewrites status should be wanted to be grounded, lower termination Vp, wherein Vp> max (| Vopen|,Vclose), make resistive
Memory A is set to low resistive state, wherein VopenFor resistance-variable storing device from low resistive state jump be high-impedance state threshold voltage,
VcloseIndicate threshold voltage of the resistance-variable storing device from high-impedance state jump for low resistive state；When input signal is logical zero, resistive
The upper end of memory A is grounded, lower termination-Vp, resistance-variable storing device A is made to be set to high-impedance state.When operation, the one of resistance-variable storing device A
Hold Port V1 namely its positive ending grounding, input termination Vin voltage, wherein Vin< min (| Vopen|,Vclose) to guarantee that resistive is deposited
The resistance value of reservoir A is not written over, and partial pressure of the Vin in arithmetic element namely variable-resistance memory unit equivalent resistance is exactly that output calculates
As a result.
For NOT gate, when input signal is logic 1, in initial assignment operation namely the resistance value of resistance-variable storing device A is rewritten
State, the resistance value of resistance-variable storing device A is set to low resistive state, and the low resistance state resistance value Ron of resistance-variable storing device A is much smaller than partial pressure
The resistance value of resistance R, partial pressure i.e. output voltage on resistance-variable storing device A are approximately equal to 0V, are logical zero；Conversely, working as input signal
When for logical zero, in initial assignment operation, the resistance value of resistance-variable storing device A is set to high-impedance state, due to the height of resistance-variable storing device A
Resistance state resistor value Roff is much larger than the resistance value of divider resistance R, and the partial pressure i.e. output voltage on resistance-variable storing device A are approximately equal to
Vin is logic 1.Thereby realize the operation of logic NOT.
Simulating, verifying function is carried out to above-mentioned not circuit, emulation is using the resistive proposed in document [15] and document [16]
The high-resistance resistors value of memory model, resistance-variable storing device A is about 2.8x106Ω, low resistance state resistance value are about 5x103Ω, partial pressure
The resistance value size of resistance R is about 7x104The Vopen of Ω, resistance-variable storing device A are about -1.1V, and Vclose is about 0.8V, Vin setting
1.4V is set as 0.5V, Vp.Simulation result is as shown in fig. 6, horizontal axis is the time in Fig. 6, and the longitudinal axis is output voltage size, when defeated
When entering signal A=0, NOT gate output voltage is high voltage, is approximately equal to 0.491V, is logic 1；As input signal A=1, NOT gate
Output voltage is low-voltage, is approximately equal to 0.052V, is logical zero.It can be seen that the function of above-mentioned not circuit is normal.
OR-NOT circuit namely or logic gate circuit are that resistance-variable storing device is realized as potential-divider network.
Or logic gate circuit is as shown in fig. 7, variable-resistance memory unit includes resistance-variable storing device A and resistance-variable storing device B, upper left
The divider resistance R resistance value at end is between the high-resistance resistors value Roff and low resistance state resistance value Ron of resistance-variable storing device.Resistance-change memory
Device A and resistance-variable storing device B are in parallel.The negative terminal and divider resistance R of two resistance-variable storing devices link together, two resistance-variable storing devices
Positive ending grounding, the common end of divider resistance R and the connection of two resistance-variable storing devices is output end, and the other end of divider resistance is defeated
Enter end.It when work, first passes through input signal and unified rewriting is carried out to the resistance value state of resistance-variable storing device, when input signal is logic
When 1, the upper end ground connection of the corresponding resistance-variable storing device for wanting rewrites status, lower termination Vp, wherein Vp> max (| Vopen|,Vclose), make
Resistance-variable storing device is set to low resistive state；When input signal is logical zero, the upper end ground connection of resistance-variable storing device, lower termination-Vp, make
Resistance-variable storing device is set to high-impedance state.When operation, one end Port V1 (namely its anode) and resistance-change memory of resistance-variable storing device A
One end Port V2 (namely its anode) of device B is grounded, input termination VinVoltage, wherein Vin< min (| Vopen|,Vclose), with
Guarantee that the resistance value of resistance-variable storing device is not written over, partial pressure of the Vin on two resistance-variable storing device parallel equivalent resistances is exactly to export
Calculated result.
For nor gate, when input signal is all logical zero, after the first step assignment operation resistance-variable storing device A, B all in
High-impedance state, the resistance value of resistance-variable storing device A, B parallel connection are Roff/2, since Roff is much larger than the resistance value of resistance R, divider resistance R
On partial pressure be approximately equal to 0V, the voltage Vout of output end is approximately equal to Vin namely logic 1.When input signal, at least one is to patrol
When volume 1, after the first step assignment operation resistance-variable storing device A, B at least one be in low resistive state, resistance-variable storing device A, B parallel connection
Resistance is less than low resistance state resistance value Ron, since low resistance state resistance value Ron is much smaller than the resistance value of divider resistance R, causes to divide
Partial pressure on resistance R is approximately equal to Vin, and output end voltage Vout is approximately equal to 0V namely logical zero, completes or non-operation.By hindering
The extension of or non-operation input terminal may be implemented in transition storage A, B both ends parallel connection resistance-variable storing device, and principle of operation is similar, per mostly simultaneously
An input terminal can be extended more by joining a resistance-variable storing device.
Simulating, verifying function is carried out to above-mentioned OR-NOT circuit, emulation is using the resistance proposed in document [15] and document [16]
The high-resistance resistors value of transition storage model, resistance-variable storing device is about 2.8x106Ω, low resistance state resistance value are about 5x103Ω, point
The resistance value size of piezoresistance R is about 7x104The Vopen of Ω, resistance-variable storing device are about -1.1V, and Vclose is about 0.8V, and Vin is set
It is set to 0.5V, Vp is set as 1.4V.For simulation result as shown in figure 8, horizontal axis is the time in Fig. 8, the longitudinal axis is output voltage size, defeated
Entering signal AB, there are four types of situations, respectively AB=00, AB=01, AB=10, AB=11, the only nor gate when inputting AB=00
Output voltage is high voltage, is approximately equal to 0.483V, is logic 1, and output voltage is approximately equal to 0.048V in the case of other, is logical zero.
As it can be seen that the function of above-mentioned OR-NOT circuit is normal.
NAND gate circuit namely NOT logic gate circuit are that resistance-variable storing device is realized as potential-divider network.
NAND Logic gate circuit is as shown in figure 9, variable-resistance memory unit includes resistance-variable storing device A and resistance-variable storing device B, upper left
The divider resistance R resistance value at end is between the high-resistance resistors value Roff and low resistance state resistance value Ron of resistance-variable storing device.Resistance-change memory
Device A and resistance-variable storing device B series connection.The negative terminal and divider resistance R of resistance-variable storing device A links together, the anode of resistance-variable storing device B
Ground connection, the common end that divider resistance R is connected with resistance-variable storing device are output end, and the other end of divider resistance is input terminal, resistive
There are an exits 100, and the initial assignment of resistance-variable storing device to be facilitated to operate namely rewrite resistance-variable storing device between memory A, B
Resistance value state.When work, first passes through input signal and unified rewriting is carried out to the resistance value state of resistance-variable storing device, work as input signal
When for logic 1, the upper end ground connection of the corresponding resistance-variable storing device for wanting rewrites status, lower termination Vp, wherein Vp> max (| Vopen|,
Vclose), so that resistance-variable storing device is set to low resistive state；When input signal is logical zero, the upper end ground connection of resistance-variable storing device, lower end
Meet-Vp, resistance-variable storing device is made to be set to high-impedance state.When operation, one end Port V2 of resistance-variable storing device B namely its positive ending grounding,
Input termination VinVoltage, wherein Vin< min (| Vopen|,Vclose), to guarantee that the resistance value of resistance-variable storing device is not written over, Vin exists
Partial pressure on resistance-variable storing device A, B series equivalent resistance is exactly to export calculated result.
For NAND gate, when input signal is all logic 1, during first step resistance-variable storing device assignment operation, resistance
Transition storage A, B are set in low resistive state, and the concatenated equivalent resistance resistance value of resistance-variable storing device A, B is 2Ron, due to resistance
The low resistance state resistance value of transition storage namely the resistance value much smaller than divider resistance R of closed resistance value Ron, on divider resistance R
Partial pressure is approximately equal to Vin, and output end voltage is approximately equal to 0V, is logical zero.When input signal, at least one is logical zero, first
During walking resistance-variable storing device assignment operation, at least one resistance-variable storing device is set in high resistant in resistance-variable storing device A, B
State, the concatenated equivalent resistance resistance value of resistance-variable storing device A, B be greater than Roff, due to resistance-variable storing device high-resistance resistors value namely
ON resistance value Roff is much larger than the resistance value of divider resistance R, and the partial pressure on divider resistance R is approximately equal to 0V, resistance-variable storing device A, B string
Partial pressure i.e. output end voltage after connection on equivalent resistance are approximately equal to Vin, are logic 1, complete NAND operation.By in resistive
The extension of NAND operation input terminal may be implemented in resistance-variable storing device of connecting in memory A, B.The participation NAND operation per more one
Operand needs more concatenated resistance-variable storing devices, and operation delay and step remain unchanged.
Simulating, verifying function is carried out to above-mentioned NAND gate circuit, emulation is using proposition in paper document [15] and document [16]
Resistance-variable storing device model, the high-resistance resistors value of resistance-variable storing device is about 2.8x106Ω, low resistance state resistance value are about 5x103
The resistance value size of Ω, divider resistance R are about 7x104The Vopen of Ω, resistance-variable storing device are about -1.1V, and Vclose is about 0.8V,
Vin is set as 0.5V, and Vp is set as 1.4V.Simulation result is as shown in Figure 10, and horizontal axis is the time in Figure 10, and the longitudinal axis is output voltage
Size, there are four types of situations, respectively AB=00, AB=01, AB=10, AB=11 by input signal AB, only in input AB=11
When nor gate output voltage be low-voltage, be equal to 0.0455V, be logical zero, output HIGH voltage is approximately equal in the case of other
0.485V is logic 1.As it can be seen that the function of above-mentioned NAND gate is normal.
AND gate circuit namely and logic gates, be that resistance-variable storing device is realized as potential-divider network.
As shown in figure 11 with logic gates, variable-resistance memory unit includes resistance-variable storing device A and resistance-variable storing device B, upper left
The resistance value of the divider resistance R at end is between the high-resistance resistors value Roff and low resistance state resistance value Ron of resistance-variable storing device.Resistive is deposited
Reservoir A and resistance-variable storing device B are in parallel.The common end that divider resistance R is connected with resistance-variable storing device is output end, divider resistance R's
The other end is input terminal.For with door, the connection method of resistance-variable storing device and logic gate above are different, resistance-variable storing device A,
The anode of B is connected on common end and links together with divider resistance R, the negativing ending grounding of resistance-variable storing device A, B.When work,
It first passes through input signal and unified rewriting is carried out to the resistance value state of resistance-variable storing device, when input signal is logic 1, correspondence will change
The upper end of the resistance-variable storing device of write state is grounded, lower termination Vp, wherein Vp> max (| Vopen|,Vclose), set resistance-variable storing device
For high-impedance state；When input signal is logical zero, the upper end ground connection of resistance-variable storing device, lower termination-Vp, set resistance-variable storing device
For low resistive state.Under identical input signal, resistance-variable storing device state jumps resistance-change memory in direction and above logic gate
Jumping for device state is contrary.
When operation, one end Port V2 of one end Port V1 (namely its negative terminal) and resistance-variable storing device B of resistance-variable storing device A
(namely its negative terminal) ground connection, input termination Vin voltage, Vin< min (| Vopen|,Vclose) to guarantee the resistance value of resistance-variable storing device not
It is written over, partial pressure of the Vin on resistance-variable storing device A, B equivalent resistance is exactly to export calculated result.
When it is logical zero that input signal, which has at least one, after resistance-variable storing device assignment, in resistance-variable storing device A, B at least
One is in low resistive state, and the equivalent resistance of resistance-variable storing device parallel network is less than low resistance state resistance value Ron, due to low resistance state electricity
Resistance value Ron is much smaller than the resistance value of divider resistance R, and the partial pressure on divider resistance R is approximately equal to Vin, and the voltage of output end is approximately equal to 0V.
When input signal is all logic 1, after assignment operation, the equivalent electricity of resistance-variable storing device A, B all in high-impedance state, after parallel connection
Resistance is Roff/2, the resistance value due to the high-resistance resistors value Roff of resistance-variable storing device much larger than divider resistance R, on divider resistance R
Partial pressure be approximately equal to 0V, output end voltage Vout is approximately equal to Vin, be logic 1, thus realize and logical operation, in resistance-change memory
The extension with door input port may be implemented in the more resistance-variable storing devices of parallel connection in device potential-divider network.
Simulating, verifying function is carried out to above-mentioned AND gate circuit, emulation is using the resistive proposed in document [15] and document [16]
The high-resistance resistors value of memory model, resistance-variable storing device is about 2.8x106Ω, low resistance state resistance value are about 5x103Ω, partial pressure
The resistance value size of resistance R is about 7x104Ω, the Vopen of resistance-variable storing device are about -1.1V, and Vclose is about 0.8V, Vin setting
1.4V is set as 0.5V, Vp.Simulation result is as shown in figure 12, and horizontal axis is the time in Figure 12, and the longitudinal axis is output voltage size, defeated
Enter signal AB there are four types of situation, respectively AB=00, AB=01, AB=10, AB=11, only in input signal AB=11 with
Door output voltage is high voltage, is equal to 0.481V, is logic 1, and output voltage is approximately equal to 0.04V in the case of other, is logical zero.
As it can be seen that above-mentioned normal with the function of door.
Can the OR circuit of concurrent operation even also logic gates be that resistance-variable storing device is realized as potential-divider network.
Or logic gates is as shown in figure 13, variable-resistance memory unit includes resistance-variable storing device A and resistance-variable storing device B, upper left
The divider resistance R resistance value at end is between the high-resistance resistors value Roff and low resistance state resistance value Ron of resistance-variable storing device, resistance-change memory
Device A and resistance-variable storing device B series connection.The common end that divider resistance R is connected with resistance-variable storing device is output end, and divider resistance R's is another
One end is input terminal.There are an exits 100, and the initial assignment of resistance-variable storing device to be facilitated to operate between resistance-variable storing device A, B
Rewrite the resistance value state of resistance-variable storing device.For or door, with as logic gate, resistive is deposited for the connection method of resistance-variable storing device
The anode of reservoir A, B connect upward, and the negative terminal of resistance-variable storing device A, B connect downward, the negativing ending grounding of resistance-variable storing device B.Work
When, it first passes through input signal and unified rewriting is carried out to the resistance value state of resistance-variable storing device, it is corresponding when input signal is logic 1
The upper end of the resistance-variable storing device of rewrites status is wanted to be grounded, lower termination Vp, wherein Vp> max (| Vopen|,Vclose), make resistance-change memory
Device is set to high-impedance state；When input signal is logical zero, the upper end ground connection of resistance-variable storing device, lower termination-Vp, make resistance-change memory
Device is set to low resistive state.When operation, one end Port V2 of resistance-variable storing device B namely its negativing ending grounding, input termination VinVoltage,
Wherein Vin< min (| Vopen|,Vclose), to guarantee that the resistance value of resistance-variable storing device is not re-written under identical input signal, resistance
Transition storage state jump direction and with it is non-or non-, in NOT logic door resistance-variable storing device state jump it is contrary.
When it is logic 1 that input signal, which has at least one, after first step resistance-variable storing device assignment operation, resistance-variable storing device A,
At least one in B is in high-impedance state, and the equivalent resistance of resistance-variable storing device parallel network is greater than Roff, due to resistance-variable storing device
High-resistance resistors value Roff be much larger than the resistance value of divider resistance R, the partial pressure on divider resistance R is approximately equal to 0V, the electricity of output end
Pressure is approximately equal to Vin.When input signal is all logical zero, after assignment operation, resistance-variable storing device A, B are in parallel all in low resistive state
Equivalent resistance later is 2Ron, since the remote Ron of low resistance state resistance value of resistance-variable storing device is much smaller than the resistance value of resistance R, partial pressure
Partial pressure on resistance R is approximately equal to Vin, and output end resistance Vout is approximately equal to 0V, thus realization or logical operation.In resistance-variable storing device
The extension of OR gate input port may be implemented in more resistance-variable storing devices of connecting in potential-divider network.
Simulating, verifying function is carried out to above-mentioned OR circuit, emulation is using the resistive proposed in document [15] and document [16]
The high-resistance resistors value of memory model, resistance-variable storing device is about 2.8x106Ω, low resistance state resistance value are about 5x103Ω, partial pressure
The resistance value size of resistance R is about 7x104Ω, the Vopen of resistance-variable storing device are about -1.1V, and Vclose is about 0.8V, Vin setting
1.4V is set as 0.5V, Vp.Simulation result is as shown in figure 14, and horizontal axis is the time in Figure 14, and the longitudinal axis is output voltage size, defeated
Enter signal AB there are four types of situation, respectively AB=00, AB=01, AB=10, AB=11, only in input signal AB=00 or
Door output voltage is low-voltage, is equal to 0.0467V, is logical zero, and output voltage is approximately equal to 0.47V in the case of other, is logic 1.
As it can be seen that above-mentioned or door function is normal.
Above-mentioned all logic gates can realize that the extension of multi input, addition need to deposit in corresponding resistive with item
It connects resistance-variable storing device in reservoir column, addition or item need in resistance-variable storing device network in a common end column resistance-change memory in parallel
Device, the circuit after extension can be used as logic gate.The potential-divider network that resistance-variable storing device is constituted can complete complicated logical operation,
In with or the logical operations such as non-can synchronously complete operation.
In fact, the scale of logic circuit is restricted, because last output voltage is by RRAM (Resistive
Random Access Memory, resistance-variable storing device) and divider resistance R between divided, it is assumed that output level is
The minimum value of high level is Voh, and output level is that low level maximum value is Vol, sets the low resistive state table of resistance-variable storing device
It is shown as logical one, high-impedance state is expressed as logical zero, sets high-resistance resistors value as Roff, low resistance state resistance value is Ron.
It is the worst situation of logical one for output result, with reference to Figure 15, it is assumed that m high-impedance state resistance-variable storing device is simultaneously
Connection, i.e. resistance-variable storing device RRAM_1 to resistance-variable storing device RRAM_m, when output level is logical one:
Requ=Roff1//Roff2//Roff3…//Roffm(2)
Roff1=Roff2...=Roffm=Roff(3)
It is available by expression formula (1), (2) and (3):
The worst situation that result is logical zero is exported, with reference to Figure 16, it is assumed that n low resistive state resistance-variable storing device series connection, i.e.,
Resistance-variable storing device RRAM_1 to resistance-variable storing device RRAM_n, when output level is logical zero:
Requ=nRon(5)
It is available by expression formula (4) and (5):
Wherein emulated using the resistance-variable storing device model proposed in document [15] and document [16].
It is provided with divider resistance R=7*104Ω, Roff=2.8*106Ω, Ron=5*103Ω, Vin=0.5V, Voh=
0.4V, Vol=0.15V.
Substitute into and calculate: m is less than or equal to 10, n and is less than or equal to 6.The data of final actual emulation: m is less than or equal to 11, n and is less than
Equal to 6.
It can be seen from the above, every a line at most allows 11 resistance-variable storing device parallel connections in logic gate, each column at most allow
6 resistance-variable storing device series connection, if it exceeds this scale, logical operation will will appear deviation.
It can be seen that from basic logic gate circuit above-mentioned real after the series-parallel rear and divider resistance R of resistance-variable storing device is divided
The existing NMOS Elementary Function for being functionally similar to cmos circuit, defers to the logic function of " string with and or, result is negated ", but
Charge and discharge are taken to carry out control output end voltage swing in cmos circuit, and the circuit based on resistance-variable storing device takes the plan of " partial pressure "
Slightly carry out control output end voltage swing.Using such basic logic gate circuit unit, circuit design method and class NMOS logic
Circuit is similar, and circuit can synchronously complete arbitrary logical operation, simultaneously for negated input, it is only necessary to by corresponding resistive
Memory is inverted, and completes reversed logical assignment, so that it may realize inversion operation.It is not deposited among circuit Different Logic operation simultaneously
It is interfering, arbitrary logical operation can completed with parallel synchronous.
The logic gate of class NMOS is to follow the logic function of " going here and there and and or, result is negated ", uses (6) and (7) two tables
Any one logical expression can be converted to the logical expression for deferring to " going here and there and and or, result is negated " this form up to formula
Formula.
Such as: the rd53f1 of benchmark circuit.
Export expression formula: F=ACDE+ABCD+ABDE+ABCE+BCDE.
By being obtained after (6) (7) abbreviation above:
By the expression formula of abbreviation above it is also seen that come the complete expression formula of abbreviation, which complies fully with, " goes here and there and and or, result
It is negated " logical form, and only need two steps that can complete to calculate it is also seen that carrying out expression above.
The nor gate mainly mentioned using above-mentioned class NMOS logic gate brief introduction is realized inside array.By taking full adder as an example:
The logical expression of carry signal C are as follows:
(6) (7) rule is used to convert each single item of expression above:
Can be seen that all operations from the expression formula after conversion and can only use nor gate can complete.In battle array
The logic circuit that column the inside is realized is as shown in figure 17.Logic circuit of the embodiment of the present invention based on resistance-variable storing device, including multistage
Gate array, wherein gate array includes multiple above-mentioned logic gates.Voltage output end and the next stage electricity of upper level gate array
Resistance-variable storing device connection in the array of road, to be rewritten in next stage circuit array using the output result of upper level gate array
The resistance value state of resistance-variable storing device, namely assignment is carried out to resistance-variable storing device, in this way, operation can be realized inside array.
Under unconfined condition, the calculation method realized inside array includes step S100 to S300.
Step S100, initial value is set to the resistance-variable storing device of gate array.According to the logic of input signal, resistance-change memory is rewritten
The resistance value state of device, so that resistance-variable storing device is in high-impedance state or low resistive state.
Step S200, make the input voltage V for being input to the voltage input end of first order gate arrayinMeet Vin< min (|
Vopen|,Vclose), wherein VopenFor resistance-variable storing device from low resistive state jump be high-impedance state threshold voltage, VcloseIt indicates
The threshold voltage that resistance-variable storing device is jumped from high-impedance state as low resistive state, so that the logic gate in gate array described in the first order
Carry out logical operation；Specifically, setting input voltage VinFor 0.5V, makes each single item while carrying out logical operation.
Step S300, the resistive in next stage circuit array is rewritten using the logic operation result of upper level gate array to deposit
The resistance value state of reservoir, so that the logic gate in next stage circuit array carries out logical operation, and so on, by afterbody electricity
Road array exports final operation result.
With reference to Figure 17, step S100 to S300 is illustrated by taking full adder circuit above-mentioned as an example.
The full adder circuit includes two-stage circuit array, respectively first order gate array Area A and second level circuit battle array
Arrange Area B.The voltage output end of first order gate array Area A passes through switch and the resistance in second level gate array Area B
Transition storage connection.Wherein, for port SUM for summing, port Carry is used for carry.
Initial value is set to the resistance-variable storing device inside gate array, wherein switch is closed.Port 1,2,3,4,5,6 and 7 meets 0V,
Port A, B and C meet V according to the logic of specific input signalpOr-Vp, resistance-change memory in the gate array Area B of the second level
Device needs all to be set to high resistant, so port x and Y meet Vp。
Disconnect port 1,2,3,4,5,6 and 7, port A, A ', B, B ', C, C ', X and Y meet 0V, set input voltage VinFor
0.5V, each single item carry out logical operation simultaneously, and partial pressure is completed in operation.
Port x and Y are met into-(Vp- 0.4), when dividing result is 0V, second level gate array Area B is not changed
In resistance-variable storing device resistance value, resistance-change memory when dividing result is 0.4V, in the gate array Area B of the second level
The resistance value of device is rewritten as low-resistance.
Switch is disconnected, port 1,2,3,4,5,6 and 7 is grounded, and the input voltage of port x and Y are 0.5V, carries out logic fortune
It calculates, exports final operation result.
In unconfined situation, array realizes that logic circuit need to only use nor gate that can realize various logic function
Can, but analyzed according to worst situation above-mentioned, every a line at most allows 11 resistance-variable storing device parallel connections, if it exceeds this is advised
Mode logic operation will will appear deviation.So needing to cut circuit if carrying out extensive Logic Circuit Design, cut
Circuit needs afterwards are used and door, are an anti-array with door just.Specific cutting method is as follows:
The logical form all completed using nor gate is converted to firstly the need of logic function expression formula；
Then " or item " quantity of the expression formula after conversion is calculated, if quantity is more than aforementioned constraint, is carried out according to formula (6)
Cutting, so that the circuit scale after cutting meets aforementioned constraint；
And then judge each " or item " by how many a resistance-variable storing device phases or, if quantity is more than constraint, according to formula (6)
It is cut, so that the circuit scale after cutting meets aforementioned constraint.
Above-mentioned extensive Logic Circuit Design is illustrated by taking benchmark Schaltkreis d53f2 as an example.
Benchmark Schaltkreis d53f2 converts the expression formula after abbreviation are as follows:
With reference to Figure 18, which includes three-level gate array, respectively first order gate array Area A2,
Second level gate array Area B2 and tertiary circuit array Area C2.The voltage output of first order gate array Area A2
End is connect by switch with the resistance-variable storing device in the gate array Area B2 of the second level, the electricity of second level gate array Area B2
Pressure output end is connect by switch with the resistance-variable storing device in tertiary circuit array Area C2.The workflow of the circuit is
It is as follows.
All switches disconnect, according to specific input signal to the resistance-change memory in first order gate array Area A2
Device sets initial value；Port x and Y in the gate array Area B2 of the second level connect 0V, port x 1 to port x 8, port Y1 to port Y8
All meet-Vp, all resistance-variable storing devices of the gate array are set to high-impedance state；In tertiary circuit array Area C2
Port Z meets 0V, port Z1 and Z2 and meets-Vp, the resistance-variable storing device of the gate array is set to high resistant；
Port A, A in first order gate array Area A2 ', B, B ', C, C ', D, D ', E and E ' ground connection, port Vin are defeated
Enter the input voltage of 0.5V；
For port x 1 in the gate array Area B2 of the second level to port x 8, port Y1 is all impractical to the port port Y8, should
The switch of gate array is all closed, and port x and Y meet-(Vp-0.4)V；
Port x 1 in the gate array Area B2 of the second level is to port x 8, and port Y1 to port Y8 is all grounded, the circuit
The switch of array is all off, the voltage of port x and Y input 0.5V；
Port Z1 and Z2 in tertiary circuit array Area C2 is all impractical, and the switch of the gate array is all closed,
Port x and Y meet (Vp+0.15)V；
Port Z1 and Z2 in tertiary circuit array Area C2 are all grounded, and the switch of the gate array is all off,
Port Z inputs the voltage of 0.5V, obtains final operation result.
Below in conjunction with simulation example, the present invention will be described.
The quantitative comparison of resistance-variable storing device needed for each logic circuit of table two
The clock quantitative comparison of each logic circuit of table three
By the data comparison of above-mentioned two table it is found that scheme proposed by the present invention: in terms of consuming resistance-variable storing device
About document [10], [13], 2 to 3 times of [14] are the growth of tens and hundreds of times in terms of speed.Due to
Benchmark circuit scale is less, and when circuit scale is larger, when inputting more, advantage of the invention is more obvious.
On the other hand, the embodiment of the present invention also provides a kind of computer readable storage medium, is stored with and sets with calculating
The standby computer program being used in combination, the computer program can be executed by processor to realize the above method.
The above content is combine it is specific/further detailed description of the invention for preferred embodiment, cannot recognize
Fixed specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs,
Without departing from the inventive concept of the premise, some replacements or modifications can also be made to the embodiment that these have been described,
And these substitutions or variant all shall be regarded as belonging to protection scope of the present invention.
The document quoted in this patent document is as follows:
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Claims (10)
1. the logic gate based on resistance-variable storing device, it is characterised in that: including variable-resistance memory unit, divider resistance, the resistive is deposited
One end of storage unit and one end of the divider resistance are commonly connected to the voltage output end of circuit, the variable-resistance memory unit
For the other end for being grounded or for input signal, the other end of the divider resistance is voltage input end；The resistance-change memory
Unit includes the resistance-variable storing device of one or more serial or parallel connections together, and the low resistance state resistance value of the resistance-variable storing device is remote
Less than the resistance value of the divider resistance, the high-resistance resistors value of the resistance-variable storing device is much larger than the resistance value of the divider resistance.
2. logic gate according to claim 1, it is characterised in that: the quantity of the resistance-variable storing device being connected in parallel is small
In or be equal to 11, the quantity of the resistance-variable storing device being cascaded is less than or equal to 6.
3. logic gate according to claim 1 or 2, it is characterised in that: the anode of the variable-resistance memory unit and described point
One end of piezoresistance is commonly connected to the voltage output end of circuit, and the negative terminal of the variable-resistance memory unit is for being grounded or being used for
Input signal；Alternatively, one end of the negative terminal of the variable-resistance memory unit and the divider resistance is commonly connected to the voltage of circuit
Output end, the anode of the variable-resistance memory unit is for being grounded or for input signal.
4. the calculation method based on logic gate according to any one of claims 1 to 3, characterized by comprising:
According to the logic of input signal, the resistance value state of the resistance-variable storing device is rewritten, so that the resistance-variable storing device is in height
Resistance state or low resistive state；
Make the input voltage V for being input to the voltage input endinMeet Vin< min (| Vopen|,Vclose), wherein VopenFor institute
State threshold voltage of the resistance-variable storing device from low resistive state jump for high-impedance state, VcloseIndicate the resistance-variable storing device from high resistant shape
State jump is the threshold voltage of low resistive state；
The logical consequence of the logic gate output is determined according to the partial pressure on the equivalent resistance of the variable-resistance memory unit.
5. calculation method according to claim 4, it is characterised in that the resistance value state for rewriting the resistance-variable storing device
Specifically: make one end input voltage V of the resistance-variable storing devicep, other end ground connection, wherein Vp> max (| Vopen|,Vclose)。
6. the logic circuit based on resistance-variable storing device, it is characterised in that: including multi-level pmultistage circuit array, the gate array includes more
A logic gate according to any one of the claim 1 to 3；Described in the voltage output end and next stage of gate array described in upper level
Resistance-variable storing device connection in gate array, to rewrite the resistance value state of the resistance-variable storing device in gate array described in next stage.
7. logic circuit according to claim 6, it is characterised in that: the operation mode of the logic gate include with or
It is non-.
8. logic circuit according to claim 6, it is characterised in that: the quantity of the gate array be two-stage or three-level with
On.
9. based on the calculation method according to the described in any item logic circuits of claim 6 to 8, characterized by comprising:
Initial value is set to the resistance-variable storing device of the gate array；
Make to be input to the input voltage V of the voltage input end of gate array described in the first orderinMeet Vin< min (| Vopen|,
Vclose), wherein VopenFor the resistance-variable storing device from low resistive state jump be high-impedance state threshold voltage, VcloseIndicate institute
Threshold voltage of the resistance-variable storing device from high-impedance state jump for low resistive state is stated, so that the logic in gate array described in the first order
Door carries out logical operation；
The resistance-variable storing device in gate array described in next stage is rewritten using the logic operation result of gate array described in upper level
Resistance value state export final operation result so that logic gate in gate array described in next stage carries out logical operation.
10. a kind of computer readable storage medium is stored with the computer program being used in combination with calculating equipment, the calculating
Machine program can be executed by processor to realize claim 4 or 5 or 9 the methods.
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