CN106158017A - The method and apparatus realizing logic and arithmetical operation based on resistance computing - Google Patents
The method and apparatus realizing logic and arithmetical operation based on resistance computing Download PDFInfo
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- CN106158017A CN106158017A CN201610443316.7A CN201610443316A CN106158017A CN 106158017 A CN106158017 A CN 106158017A CN 201610443316 A CN201610443316 A CN 201610443316A CN 106158017 A CN106158017 A CN 106158017A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The present invention proposes a kind of resistive computing storage device and operational approach thereof.Described resistive computing storage device includes: a plurality of wordline that first direction extends；The multiple bit lines that the second direction that edge and first direction intersect extends；Being respectively arranged at each bit line and the intersection of each wordline and the multiple resistive computing storing sub-units being connected with respective bit line and respective word, each resistive computing storing sub-units is changeable and therefore store corresponding data between high-impedance state and low resistance state；It is connected to the bit line reference cell of each bit lines, the one end being connected to each wordline is connected with wordline reference cell, and controller, the trigger voltage signal carrying out computing is connected with input module, the Resistance states different by resistance value height represents input variable, and control same a line or collaborative logic or the arithmetical operation of carrying out of described resistive computing storing sub-units with string, and control output module for the different resistance value of the height reading storage array to represent output variable.
Description
Technical field
Present disclose relates generally to semiconductor integrated circuit and manufacturing technology field thereof, permissible more particularly, to one
Realized the method and device of logic and arithmetical operation by resistance transmission in resistive device crossed array.
Background technology
The present computer technology is based on von Neumann architectural framework and Boolean algebra logic.At von Neumann architecture
Middle arithmetic section and storage part are to separate, and data are swapped between arithmetic section and storage part divide by bus.Number
According to swapping meeting consumed energy in bus and reducing computational efficiency, along with arithmetic section based on COMS technology and storage part
The development divided, data exchange velocity in bus has become as the bottleneck that restriction system computing efficiency improves, and data are led to simultaneously
The energy consumption crossing bus switch process causes the energy consumption of system to increase.In modern computer, Boolean algebra logical operations is dependent on level
Signal triggers and cascade, and in arithmetic section, the transmission of data signal has always a demand for keeping triggering level signal and input signal, makes
Become bigger quiescent dissipation.Additionally, the arithmetic section in modern computer is based primarily upon COMS circuit, its logic function is by COMS
Interconnection and the compound mode of unit determine, therefore cannot carry out function remodeling easily, and this can cause the idle of calculation resources, it is impossible to
Utilize calculation resources most effectively.
Under current big data and Internet of Things is fast-developing, mobile device is widely available historical background, traditional calculating
Equipment is the most gradually difficult to meet the demand of people at the aspect such as energy consumption, speed.In order to break through the restriction of existing counting system framework,
Propose the framework of the emulation neural computing system of human brain structure and calculating based on memristor/be stored as one.God
In metanetwork counting system, the most do not observe Boolean algebra logic, need again develop programming language and operate system accordingly
System.Counting system based on memristor still follows Boolean algebra logic, but there is new technology in this architecture
Challenge, it is impossible to realize the cascade of logical message.
Summary of the invention
For above-mentioned technical problem, the invention provides a kind of side carrying out Boolean algebra logical operations in resistive device
Method, and the integrated novel counting system structure of the computing/storage of logic based on this method cascade and operational approach thereof.
It is an object of the invention to provide one utilizes resistive device (to include resistance-variable storing device RRAM based on oxide, base
Resistance is relied on to become in metal ion redox resistance-variable storing device CBRAM, phase transition storage PCM, magnetoresistive memory MRAM etc.
Change the components and parts carrying out information storage) realize Boolean algebra logical operations, data storage and the method for transmission by resistance transmission
And corresponding architecture.The resistance value of resistive device can be cut by applied voltage between two different resistance values
Change, referred to as programming (program)/erasing (erase) (or SET/RESET).Program voltage and erasing voltage opposite polarity,
The high low resistance state of two resistance values of storage has significantly difference.In this architecture, the resistance that resistance value height is different
State is as the input of information, the variable that exports and calculate and store, and pulse voltage signal triggers computing, and pulse voltage letter
Number signal sequence form determine computing type.
According to an aspect of the present invention, it is proposed that a kind of resistive computing storage device, including:
The a plurality of wordline extended in a first direction；
The multiple bit lines that the second direction that edge and first direction intersect extends；
It is respectively arranged at each bit line and the intersection of each wordline and the multiple resistances being connected with respective bit line and respective word
Becoming computing storing sub-units, each resistive computing storing sub-units is changeable and therefore store between high-impedance state and low resistance state
Corresponding data；
Being connected to the bit line reference cell of each bit lines, the first end of bit line reference cell is connected to bit line, and bit line
The other end of reference cell gates different triggering level signals by the first input module, and the other end of every bit lines is led to
Cross resistive computing storing sub-units to be connected with each wordline, and the other end of every bit lines is switched by selection and exports
Module is connected,
The wordline reference cell being connected to each wordline is connected, and the first end of wordline reference cell is connected to wordline, and
The other end of wordline reference cell gates different triggering level signals by the second input module, other the one of every wordline
End be connected with each bit lines by resistive computing storing sub-units, and the other end of every wordline by select switch with
Output module is connected；And controller, the trigger voltage signal carrying out computing is connected with input module；High by resistance value
Low different Resistance states represents input variable, control the described resistive computing storing sub-units with a line or with string work in coordination with into
Row logical-arithmetical operation, controls output module and is used for carrying out data exchange with other equipment in calculating, and read storage array
The different resistance value of height carry out logical variable output.
Preferably, described resistive computing storing sub-units includes resistance-variable storing device RRAM based on oxide, based on metal
The resistance-variable storing device CBRAM of ionic redox, phase transition storage PCM, magnetoresistive memory MRAM at least one, described resistive
Computing storing sub-units depends on resistance variations and carries out information storage and computing.
Preferably, described resistive computing storing sub-units is single resistive device or resistive device and two-way choice
The structure of devices in series.
Preferably, the resistance of described reference cell is in the high-impedance state resistance of resistive computing storing sub-units and low resistance state resistance
Between value.
Preferably for be connected in the resistive computing storing sub-units of same bit line storage data " A " and " B ", when
Trigger voltage V applied on the port of the first input block being connected with reference cellCC, single at resistive computing input storage
Trigger voltage V is applied on the port of unit ACC/ 2, and execute on the port of the computing storage output subelement B of storage output variable
Add trigger voltage 0, then the logical value on the resistive computing storage output subelement after triggering level triggers achieves " containing "
Logical operations:When B=0 when, it is achieved the logical operations of " non-".
Preferably for the resistive computing storing sub-units and the auxiliary resistive computing storing sub-units that are connected to same bit line
The data " A " of middle storage and " B ", when the trigger voltage applied on the port at the first input block being connected with reference cell
VCC, the port of described resistive computing storage input subelement A applies trigger voltage 0, and in described auxiliary resistive computing
Trigger voltage VCC, then the auxiliary resistive computing storing sub-units after triggering level triggers is applied on the port of storing sub-units
On logical value achieve logical "or" computing: B'=A+B.When B=0 when, it is achieved that " transmission " logic.
Preferably for the resistive computing storing sub-units and the auxiliary resistive computing storing sub-units that are connected to same bit line
The data " A " of middle storage and " B ", when the trigger voltage applied on the port at the first input block being connected with reference cell
VCC, the port of described resistive computing storage input subelement A applies trigger voltage VCC/ 2, and in described resistive computing
Trigger voltage 0, the then resistance originally storing data " B " after triggering level triggers is applied on the port of storage output subelement B
Become the logical value in computing storing sub-units to achieve logic and " contain " computing:When B=0 when, it is achieved
The logic of " non-".
Preferably for be connected in the resistive computing storing sub-units of same bit line storage data " A " and " B ", when
Trigger voltage V applied on the port of the first input block being connected with reference cellCC/ 2, at resistive computing storage input
Trigger voltage V is applied on the port of unit ACC, and apply trigger voltage on the port of resistive computing storage output subelement B
0, then the logical value in resistive computing output storing sub-units B after triggering level triggers achieves logical "or" computing: B'
=A+B.When B=0 when, it is achieved that " transmission " logic.
Logic cascade or logical reconstruction can also be carried out to above-mentioned logic and arithmetical operation.
In this architecture, the resistance value the most different Resistance states of height as information input, export and calculate and deposit
The variable of storage, pulse voltage signal triggers computing, and the signal sequence form of pulse voltage signal determines the type of computing.Resistance
Becoming device is non-volatile-type memorizer, and therefore logic operation result need not triggering level maintenance, greatly reduces the merit of computing
Consumption.Different logic, arithmetical operation task can be completed by same group of resistive device of the control realization of triggering level, i.e. realize
Logic function reconstructs, and can be greatly enhanced the utilization ratio of hardware cell.
Accompanying drawing explanation
By description to disclosure embodiment referring to the drawings, above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows by two basic logic units that bit line resistive device is constituted altogether；
Fig. 2 shows the crossed array computing memory module schematic diagram being made up of resistive device；
Fig. 3 shows system schematic based on resistive device resistance computing；
Fig. 4 shows by two basic logic units that wordline resistive device is constituted altogether；
Fig. 5 shows the circuit diagram called when carrying out " AB+C " arithmetic logic；And
Fig. 6 shows the schematic diagram of logical reconstruction function and corresponding triggering level sequential chart.
Detailed description of the invention
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are the most exemplary
, and it is not intended to limit the scope of the present disclosure.Additionally, in the following description, eliminate the description to known features and technology, with
Avoid unnecessarily obscuring the concept of the disclosure.
Various structural representations according to disclosure embodiment shown in the drawings.These figures are not drawn to scale
, wherein in order to understand the purpose of expression, it is exaggerated some details, and some details may be eliminated.Shown in figure
The shape of various elements and the relative size between them, position relationship are only exemplary, are likely to be due to manufacture in reality
Tolerance or technical limitations and deviation, and those skilled in the art have not similar shape according to actually required can additionally design
Shape, size, the element of relative position.
In the context of the disclosure, when one layer/element is referred to as positioned at another layer/element " on " time, this layer/element can
To be located immediately on this another layer/element, or intermediate layer/element between them, can be there is.If it addition, one towards
In one layer/element be positioned at another layer/element " on ", then when turn towards time, this layer/element may be located at this another layer/unit
Part D score.
It is an object of the invention to provide one utilizes resistive device (to include resistance-variable storing device RRAM based on oxide, base
Resistance is relied on to become in metal ion redox resistance-variable storing device CBRAM, phase transition storage PCM, magnetoresistive memory MRAM etc.
Change the components and parts carrying out information storage) realize Boolean algebra logical operations, data storage and the method for transmission by resistance transmission
And corresponding architecture.The resistance value of resistive device can be cut by applied voltage between two different resistance values
Change, referred to as programming (program)/erasing (erase) (or set (SET)/reset) RESET) program voltage and erasing
Polarity of voltage is contrary, and the high low resistance state of two resistance values of storage has significantly difference.In this architecture, resistance value is high
Low different Resistance states as the input of information, the variable that exports and calculate and store, pulse voltage signal trigger computing with
And signal sequence form determines the type of computing.
The ALU being made up of two resistive devices shown in accompanying drawing 1, when applying to be suitable on port 0,1 and 2
Triggering level, on resistive device A, B with resistance form storage data message value can carry out logical operations, the knot after computing
Fruit is stored on resistive device A or B with the form of resistance value.Here, the resistance value on resistive device A and B can be as logic
Input variable participates in computing, and participates in the resistance logic as output logical variable after the resistance value of computing and computing
Value is all stored in the resistive device of participation computing, need not carry out carrying out information data between arithmetic element and memory element
Transmission, it is achieved that use same unit to realize data operation and storage.Resistive device is non-volatile-type memorizer, therefore logic fortune
Calculate result and need not triggering level maintenance, greatly reduce the power consumption of computing.Participate in resistance logic arithmetic element and do not limit to 2,
Computing can be participated in, the resistance logic value storage after computing by the resistance value that the control of triggering level makes multiple resistor-type store
On one of resistive device participating in logical operations, after storage computing, the unit of resistance value can be controlled by triggering level
Select.The memorizer of storage resistance operation result for the first time can be by execution cycle after the control participation of triggering level
Resistance logic computing thus realize the cascade of logical operations.Carry out the logic of computing, arithmetic types (with, or, non-, add, subtract)
Being selected by the type of triggering level, this shows that same resistor-type memory element can participate in different logics and arithmetic
Computing, can complete different logic, arithmetical operation task by same group of resistive device of the control realization of triggering level, the most in fact
Existing logic function reconstruct, so can greatly utilize hardware cell.
Based on resistance computing and the principle of transmission, resistive device can prepare crossed array as shown in Figure 2.Intersecting
The a plurality of wordline comprise a plurality of multiple bit lines parallel to each other in array, being parallel to each other and the resistance between wordline and bit line
Become computing storing sub-units；Resistive computing storing sub-units can be single resistive device can also be a resistive device and double
Structure to selector series connection.Wordline and bit line are mutually perpendicular to, and deposit in the crossed array resistive computing with a line with string
Storage subelement can directly constitute arithmetic element, and the subelement of different rows different lines can constitute arithmetic element indirectly.Every position
One end of line and the reference cell R with fixed resistanceCIt is connected, fixed resistance RCOther end gated not by input module
Same triggering level signal.RCValue between high value and the low resistance that resistive device stores, such as it is for both
Geometrical mean.The other end of every bit lines is connected with input/output module by selecting switch；One end of every wordline
With fixed resistance RCIt is connected, fixed resistance RCOther end gate different triggering level signals, every word by input module
The other end of line is connected with input/output module by selecting switch.Output module mainly reads the resistance value of storage array
It is transformed into voltage signal and facilitates other outputs in calculating system.
Resistive computing store interleaving array and input module, output module constitute the information data computing of a collection and storage one
The module of body, carries out data exchange by depositor between module and module.As shown in Figure 3；The input of module and output point
Not being connected with input/output bus, the data on address bus are connected with the input block in module.Operation control sends and carries out
The trigger voltage signal of computing is connected with the input module in module；Each of control signal that operation control sends and system
Module is connected and coordinates input and output and computing.
Specifically, as it is shown in figure 1, when trigger voltage 0V applied on port 0, apply trigger voltage V on port 1CC/
2, port 2 applies trigger voltage VCCIf before computing, resistive device A, B being storage low resistance state Ron, then electricity is being triggered
During pressure applies, the voltage being carried in resistive device A, B two ends is-Vcc/ 4 and VccAbout/4 (on port 3, voltage is big
Time be negative), it is impossible to change the resistance value in resistive device A, B；If storage for R in resistor-type A, B before computingonAnd height
Resistance state Roff, the voltage being carried in resistive device A, B two ends during triggering level applies is 0 and VccAbout/2, resistive device
Resistance value in A, B will not change；If the resistance being stored in before computing in A, unit B is RoffAnd Ron, in triggering level
Being carried in resistive device A during applying, the voltage at B two ends is-Vcc/ 2 and about 0, resistive device A, the resistance value in B will not
Change；If the resistance being stored in before computing in A, unit B is RoffAnd Roff, it is carried in during triggering level applies
A, the voltage at unit B two ends is Vcc/ 2 and VccLeft and right, the resistance value on resistor-type storage B can occur upset to be set to low resistance state.As
Really RoffIt is expressed as 0, RonIt is expressed as 1；Then after triggering level triggers, the logical value in unit B can describe with following formula:
B ' represents the logical value of storage in the B after computing, it is achieved that " containing " logical operations.
If the triggering level applied is that port 0 sets to 0, port 1 puts-Vcc/ 2, port 2 puts Vcc/2.If before computing, resistance
Becoming in device A, B is all storage low resistance state Ron, then, during trigger voltage applies, it is carried in the electricity at resistive device A, B two ends
Pressure is-Vcc/ 2 and VccAbout/2, it is impossible to change the resistance value in resistive device A, B；If in resistive device A, B before computing
Storage for RonWith high-impedance state Roff, the voltage being carried in resistive device A, B two ends during triggering level applies is 0 and Vcc
Left and right, in resistive device A, the resistance value of storage will not change, and the resistance value in B can be inserted low resistance state from high-impedance state；As
The resistance being really stored in A, unit B before computing is RoffAnd Ron, during triggering level applies, it is carried in resistive device A, B
The voltage at two ends is-VccWith about 0, the resistance value in resistive device A, B will not change；If being stored in A, B before computing
Resistance in unit is RoffAnd Roff, triggering level apply during be carried in A, the voltage at unit B two ends is-Vcc/ 2 Hes
VccAbout/2, resistive device A, the resistance value in B will not change.After triggering level triggers, the logical value in unit B can
To describe with following formula:
B'=A+B (2),
Achieve the logical operation of "or".
For (1) formula, when B=0 when, it is achieved the logic of " non-"；For (2) formula, when B=0 when,
Achieve " transmission " logic.Logical operations or arithmetical operation for any complexity can use these basic logic units
Combine and realize in accompanying drawing 2 is with a line.
Logic-operated process is carried out for resistive device with string different rows in Fig. 2 to illustrate with Fig. 4.Fig. 4 shows
Go out by two basic logic units that wordline resistive device is constituted altogether.In the diagram, port 0 applies triggering level Vcc, end
Level triggers level V is applied on mouth 1cc/ 2, port 2 applies triggering level signal 0；If before computing, resistive device A, B are
Storage low resistance state Ron, then, during trigger voltage applies, the voltage being carried in resistive device A, B two ends is-Vcc/ 4 and Vcc/4
Left and right (on port 3, electromotive force is big, for just), it is impossible to change the resistance value in resistive device A, B；If resistor-type A, B before computing
Middle storage for RonWith high-impedance state Roff, the voltage being carried in resistive device A, B two ends during triggering level applies is 0 and
VccAbout/2, in resistive device A, B, the resistance value of storage will not change；If the electricity being stored in before computing in A, unit B
Resistance is RoffAnd Ron, the voltage being carried in resistive device A, B two ends during triggering level applies is-Vcc/ 2 and about 0, resistance
The resistance value become in device A, B will not change；If the resistance being stored in before computing in A, unit B is RoffAnd Roff,
Triggering level is carried in A during applying, the voltage at unit B two ends is Vcc/ 2 and VccLeft and right, the resistance value in resistive device A
Will not change, in B, the resistance of storage can be set to low resistance state；Then after triggering level triggers, the logical value in unit B can
To describe with following formula:
Achieve " containing " logical operation.
For the structure in Fig. 4, when applying triggering level V on port 0cc/ 2, port 1 applies level triggers level
Vcc, port 2 applies triggering level signal 0.If before computing, resistive device A, B are storage Ron, then execute in trigger voltage
During adding, the voltage being carried in resistive device A, B two ends is-Vcc/ 2 and VccAbout/2 (on port 3, electromotive force is big, for just), nothing
Method changes the resistance value in resistive device A, B；If the resistor-type A before computing, storage for R in BonAnd Roff, in triggering level
The voltage being carried in resistive device A, B two ends during applying is 0 and VccLeft and right, in resistive device A, the resistance value of storage will not
Change, be stored in resistance value in B and can be set to Ron；If being stored in A before computing, the resistance in unit B is RoffAnd Ron,
The voltage being carried in resistive device A, B two ends during triggering level applies is-VccElectricity with about 0, in resistive device A, B
Resistance will not change；If the resistance being stored in before computing in A, unit B is RoffAnd Roff, apply process in triggering level
In be carried in A, the voltage at unit B two ends is-Vcc/ 2 and VccAbout/2, resistive device A, the resistance value in B will not change
Become；Then after triggering level triggers, the logical value in unit B can describe with following formula:
B'=A+B (4)
Achieve "or" logical operation.Resistive device for string same in Fig. 2 (being connected to same bit line) can be with logical
Cross the complicated logic of the logic realization of combination (3) (4) formula, arithmetical operation.
Logic cascade example: D=AB+C
The resistive device one participating in this complex logic computing has 5: three input A, B, C；One output D and
Auxiliary unit Assist is as shown in Figure 5.Before computing, Assist and output unit are set to Roff(0), first computing week
Interim, the triggering level signal that port 2 applies is Vcc/ 2, the triggering level signal that port 4 applies is Vcc, port 0 is put
Zero, other ports are for suspending, so the logical value in Assist is after first sub-execution cycleIn second execution cycle
The triggering level applied on port 1 is Vcc/ 2, the triggering level signal that port 4 applies is Vcc, port 0 zero setting, other ports
For suspending, after second sub-execution cycle, the logical value in Assist is3rd execution cycle touching when middle port 4
Generating is put down as Vcc/ 2, on port 5, triggering level is Vcc, port 0 is set to 0, other ports suspend；Logical value on D after computing
For AB；4th sub-execution cycle is V when the triggering level of middle port 5cc, port 0 is set to Vcc/ 2, port 3 puts triggering level
0, other ports suspend, and after computing, the logical value in D is AB+C, and processor active task completes.
Logical reconstruction example:
As shown in Figure 6, using A, B in the first execution cycle, tri-resistive devices of C complete logical operations C=AB
And the result of logical operations is stored in the middle of C, if user needs to input two logical values more also in the middle of computing later
Doing and non-logical operation, it is only necessary to A before computing, first the logical value in the middle of B, C is set to 0, and then write user refers to
Fixed logical value is in A, unit B；Again to A in next arithmetic element, the triggering level that tri-unit of B, C apply to be suitable for is
Can completeLogical operations and store the result in C cell.
According in the above-mentioned resistive computing storage device of the present invention, use resistance value as the input and output thing of gate
Reason variable.Using resistance value as the input and output physical descriptor of gate, the most different Resistance states of resistance value height is as information
Input, the variable that exports and calculate and store, pulse voltage signal triggers computing, and the signal sequence of pulse voltage signal
Row form determines the type of computing.Resistive device is non-volatile-type memorizer, and therefore logic operation result need not triggering level
Maintain, greatly reduce the power consumption of computing.Can complete different by same group of resistive device of the control realization of triggering level
Logic, arithmetical operation task, i.e. realize logic function reconstruct, can be greatly enhanced the utilization ratio of hardware cell.
Although by reference to the exemplary embodiments of the present invention, specifically illustrate and describe the present invention, but the common skill in this area
Art personnel should be appreciated that in the case of the spirit and scope of the present invention limited without departing from claims, can be right
These embodiments carry out the multiple change in form and details.
Claims (10)
1. a resistive computing storage device, including:
The a plurality of wordline extended in a first direction；
The multiple bit lines that the second direction that edge and first direction intersect extends；
It is respectively arranged at each bit line and the intersection of each wordline and the multiple resistives fortune being connected with respective bit line and respective word
Calculate storing sub-units, each resistive computing storing sub-units between high-impedance state and low resistance state changeable and therefore storage corresponding
Data；
Being connected to the bit line reference cell of each bit lines, the first end of bit line reference cell is connected to bit line, and bit line benchmark
The other end of unit gates different triggering level signals by the first input module, and the other end of every bit lines is by resistance
Become computing storing sub-units to be connected with each wordline, and the other end of every bit lines is switched by selection and output module
It is connected,
The wordline reference cell being connected to each wordline is connected, and the first end of wordline reference cell is connected to wordline, and wordline
The other end of reference cell gates different triggering level signals by the second input module, and the other end of every wordline is led to
Cross resistive computing storing sub-units to be connected with each bit lines, and the other end of every wordline is switched by selection and exports
Module is connected；And
Controller, is connected the trigger voltage signal carrying out computing with input module, by the Resistance states that resistance value height is different
Representing input variable, the control described resistive computing storing sub-units with a line or with string is collaborative carries out logic arithmetic fortune
Calculate, control output module and be used for carrying out data exchange with other resistive computing storing sub-units in calculating, and read storage
The resistance value that the height of array is different carries out logical variable output.
Resistive computing storage device the most according to claim 1, wherein said resistive computing storing sub-units include based on
The resistance-variable storing device RRAM of oxide, based on metal ion redox resistance-variable storing device CBRAM, phase transition storage PCM, magnetic
At least one of resistance memorizer MRAM, described resistive computing storing sub-units depends on resistance variations and carries out information storage and fortune
Calculate.
Resistive computing storage device the most according to claim 1, wherein said resistive computing storing sub-units is single
The structure that resistive device or resistive device and two-way choice device are connected.
Resistive computing storage device the most according to claim 1, the resistance of wherein said reference cell is in resistive computing
Between high-impedance state resistance and the low resistance state resistance of storing sub-units.
Resistive computing storage device the most according to claim 1, wherein deposits for being connected to the resistive computing of same bit line
The data " A " stored in storage subelement and " B ", when touching of applying on the port at the first input block being connected with reference cell
Generating pressure VCC, the port of resistive computing input storing sub-units A applies trigger voltage VCC/ 2, and defeated in described storage
On the port of the computing storing sub-units going out variable apply trigger voltage 0, then triggering level trigger after originally store data
Logical value in the resistive computing storing sub-units of " B " achieves logic and " contains " computing:
Resistive computing storage device the most according to claim 5, wherein when B=0 when, it is achieved the logic fortune of " non-"
Calculate.
Resistive computing storage device the most according to claim 1, wherein deposits for being connected to the resistive computing of same bit line
The data " A " stored in storage subelement and " B ", when touching of applying on the port at the first input block being connected with reference cell
Generating pressure VCC/ 2, the port of resistive computing input storing sub-units A applies trigger voltage VCC, and deposit in resistive computing
Trigger voltage 0, then the resistive computing storage output subelement after triggering level triggers is applied on the port of storage output subelement B
On logical value achieve logical "or" computing: B'=A+B.
Resistive computing storage device the most according to claim 7, wherein when B=0 when, it is achieved that " transmission " logic.
9., according to the resistive computing storage device according to any one of claim 2 to 8, also include above-mentioned logic and arithmetic are transported
Calculation carries out logic cascade or logical reconstruction.
Resistive computing storage device the most according to claim 1, wherein uses resistance value as the input and output of gate
Physical descriptor.
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| CN108182959A (en) * | 2018-01-22 | 2018-06-19 | 中国科学院微电子研究所 | Method for realizing logic calculation based on crossing array structure of resistive device |
| CN109214048A (en) * | 2018-07-27 | 2019-01-15 | 西南大学 | Utilize mixing CMOS- memristor fuzzy logic gate circuit and its design method |
| TWI657443B (en) * | 2018-03-19 | 2019-04-21 | 旺宏電子股份有限公司 | Memory device and operation method thereof |
| CN109905115A (en) * | 2019-02-27 | 2019-06-18 | 华中科技大学 | A kind of reversible logic circuits and its operating method |
| CN110007897A (en) * | 2019-03-18 | 2019-07-12 | 北京大学深圳研究生院 | Logic gate, logic circuit and calculation method based on resistance-variable storing device |
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| CN112466365A (en) * | 2020-12-09 | 2021-03-09 | 中国人民解放军国防科技大学 | Three-dimensional memristor state logic circuit and NOR logic implementation method |
| CN113285710A (en) * | 2021-06-04 | 2021-08-20 | 广东工业大学 | Memristor cross array-based logic gate circuit and NAND gate and NOR gate implementation method |
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| CN108182959B (en) * | 2018-01-22 | 2021-02-23 | 中国科学院微电子研究所 | Method for realizing logic calculation based on crossing array structure of resistive device |
| CN108182959A (en) * | 2018-01-22 | 2018-06-19 | 中国科学院微电子研究所 | Method for realizing logic calculation based on crossing array structure of resistive device |
| TWI657443B (en) * | 2018-03-19 | 2019-04-21 | 旺宏電子股份有限公司 | Memory device and operation method thereof |
| CN109214048A (en) * | 2018-07-27 | 2019-01-15 | 西南大学 | Utilize mixing CMOS- memristor fuzzy logic gate circuit and its design method |
| CN109905115A (en) * | 2019-02-27 | 2019-06-18 | 华中科技大学 | A kind of reversible logic circuits and its operating method |
| CN109905115B (en) * | 2019-02-27 | 2020-08-04 | 华中科技大学 | Reversible logic circuit and operation method thereof |
| CN110007897B (en) * | 2019-03-18 | 2021-01-26 | 北京大学深圳研究生院 | Logic gate based on resistive random access memory, logic circuit and calculation method |
| CN110007897A (en) * | 2019-03-18 | 2019-07-12 | 北京大学深圳研究生院 | Logic gate, logic circuit and calculation method based on resistance-variable storing device |
| CN112466365A (en) * | 2020-12-09 | 2021-03-09 | 中国人民解放军国防科技大学 | Three-dimensional memristor state logic circuit and NOR logic implementation method |
| CN112466365B (en) * | 2020-12-09 | 2022-04-15 | 中国人民解放军国防科技大学 | Three-dimensional memristor state logic circuit and NOR logic implementation method |
| CN112466366A (en) * | 2020-12-09 | 2021-03-09 | 中国人民解放军国防科技大学 | Three-dimensional memristor state logic circuit and NOR logic implementation method |
| CN113285710A (en) * | 2021-06-04 | 2021-08-20 | 广东工业大学 | Memristor cross array-based logic gate circuit and NAND gate and NOR gate implementation method |
| CN113437964A (en) * | 2021-06-10 | 2021-09-24 | 安徽大学 | Operational circuit composed of RRAM and capable of being distinguished by resistance states and being reconstructed |
| CN113437964B (en) * | 2021-06-10 | 2022-09-16 | 安徽大学 | Operational circuit composed of RRAM and capable of being distinguished by resistance states and being reconstructed |
| CN113362872A (en) * | 2021-06-16 | 2021-09-07 | 华中科技大学 | Memristor-based complete nonvolatile Boolean logic circuit and operation method |
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