CN106158017B - Resistive operation stores equipment - Google Patents
Resistive operation stores equipment Download PDFInfo
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- CN106158017B CN106158017B CN201610443316.7A CN201610443316A CN106158017B CN 106158017 B CN106158017 B CN 106158017B CN 201610443316 A CN201610443316 A CN 201610443316A CN 106158017 B CN106158017 B CN 106158017B
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- resistive
- bit line
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- wordline
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
The invention proposes a kind of resistive operation storage equipment and its operating methods.The resistive operation storage equipment includes: a plurality of wordline that first direction extends；The multiple bit lines extended along the second direction intersected with first direction；The multiple resistive operation storing sub-units for being respectively arranged at the intersection of each bit line and each wordline and connecting with respective bit line and respective word, each resistive operation storing sub-units can be switched between high-impedance state and low resistance state and therefore store corresponding data；It is connected to the bit line reference cell of each bit line, the one end for being connected to each wordline is connected with wordline reference cell, and controller, the trigger voltage signal for carrying out operation is connected with input module, input variable is indicated by the different Resistance states of resistance value height, and it controls to cooperate with the resistive operation storing sub-units of a line or same row and carries out logic or arithmetical operation, and control the different resistance value of height of the output module for reading storage array to indicate output variable.
Description
Technical field
It, can be with more particularly, to one kind present disclose relates generally to semiconductor integrated circuit and its manufacturing technology field
The method and device for realizing logic and arithmetical operation is transmitted by resistance in resistive device crossed array.
Background technique
The present computer technology is based on von Neumann architectural framework and Boolean algebra logic.In von Neumann architecture
Middle arithmetic section and storage section are separation, and data are swapped between arithmetic section and storage section by bus.Number
Energy and reduction computational efficiency can be consumed according to swapping in bus, with arithmetic section and storage unit based on COMS technology
The development divided, exchange velocity of the data in bus, which has become, restricts the bottleneck that system computing efficiency improves, while data are logical
The energy consumption for crossing bus switch process causes the energy consumption of system to increase.Boolean algebra logical operation is by level in modern computer
Signal triggers and cascade, and the transmitting of data-signal is made there is a continuing need for triggering level signal and input signal is kept in arithmetic section
At biggish quiescent dissipation.In addition, the arithmetic section in modern computer is based primarily upon COMS circuit, logic function is by COMS
The interconnection of unit and combination determine, therefore can not carry out function remodeling easily, this will cause the idle of calculation resources, can not
Most effectively utilize calculation resources.
Under the historical background that current big data and Internet of Things are fast-developing, mobile device is widely available, traditional calculating
Equipment energy consumption, in terms of be gradually difficult to meet the needs of people.In order to break through the limitation of existing counting system framework,
The framework that the neural computing system and calculating/storage based on memristor for proposing emulation human brain structure are integrated.In mind
Through not abiding by Boolean algebra logic in metanetwork counting system, need to develop programming language and corresponding operation system again
System.Counting system based on memristor still follows Boolean algebra logic, but there is new technology in this architecture
Challenge, cannot achieve the cascade of logical message.
Summary of the invention
In view of the above technical problems, the present invention provides a kind of in resistive device carries out the side of Boolean algebra logical operation
Method, and the integrated novel counting system structure of the cascade operation/storage of logic and its operating method based on this method.
The object of the present invention is to provide a kind of using resistive device (including resistance-variable storing device RRAM, base based on oxide
Become in the redox resistance-variable storing device CBRAM of metal ion, phase transition storage PCM, magnetoresistive memory MRAM etc. by resistance
Change the component for carrying out information storage) method for realizing Boolean algebra logical operation, data storage and transmitting is transmitted by resistance
And corresponding architecture.The resistance value of resistive device can be cut between two different resistance values by applied voltage
It changes, referred to as programming (program)/erasing (erase) (or SET/RESET).Program voltage and erasing voltage polarity on the contrary,
The high low resistance state of two resistance values of storage has apparent difference.In this architecture, the different resistance of resistance value height
Variable of the state as the input of information, output and calculating and storage, pulse voltage signal triggers operation, and pulse voltage is believed
Number signal sequence form determine operation type.
According to an aspect of the present invention, it proposes a kind of resistive operations to store equipment, comprising:
The a plurality of wordline extended in a first direction；
The multiple bit lines extended along the second direction intersected with first direction；
The multiple resistances for being respectively arranged at the intersection of each bit line and each wordline and being connect with respective bit line and respective word
Become operation storing sub-units, each resistive operation storing sub-units can be switched between high-impedance state and low resistance state and therefore store
Corresponding data；
It is connected to the bit line reference cell of each bit line, the first end of bit line reference cell is connected to bit line, and bit line
The other end of reference cell gates different triggering level signals by the first input module, and the other end of every bit line is logical
It crosses resistive operation storing sub-units to be connected with each wordline, and the other end of every bit line passes through selection switch and output
Module is connected,
The wordline reference cell for being connected to each wordline is connected, and the first end of wordline reference cell is connected to wordline, and
The other end of wordline reference cell gates different triggering level signals by the second input module, and other the one of every wordline
End is connected by resistive operation storing sub-units with each bit line, and the other end of every wordline by selection switch with
Output module is connected；And controller, the trigger voltage signal for carrying out operation is connected with input module；Pass through resistance value height
Low different Resistance states indicate input variable, control the resistive operation storing sub-units with a line or same row cooperate with into
Row logical-arithmetical operation, control output module is used to carry out data exchange with other equipment in calculating, and reads storage array
Height different resistance value carry out logical variable output.
Preferably, the resistive operation storing sub-units include resistance-variable storing device RRAM based on oxide, based on metal
At least one of the resistance-variable storing device CBRAM of ionic redox, phase transition storage PCM, magnetoresistive memory MRAM, the resistive
Operation storing sub-units carry out information storage and operation dependent on resistance variations.
Preferably, the resistive operation storing sub-units are either resistive device and the two-way choices of individual resistive device
The structure of devices in series.
Preferably, the resistance value of the reference cell is high-impedance state resistance value and the low resistance state resistance in resistive operation storing sub-units
Between value.
Preferably for being connected to the data " A " stored in the resistive operation storing sub-units of same bit line and " B ", when
The trigger voltage V applied on the port for the first input unit being connected with reference cellCC, it is single that storage is inputted in resistive operation
Apply trigger voltage V on the port of first ACC/ 2, and applied on the port of the operation storage output subelement B of storage output variable
Add trigger voltage 0, then the logical value on the resistive operation storage output subelement after triggering level triggering realizes " containing "
Logical operation:When B=0, the logical operation of " non-" is realized.
Preferably for the resistive operation storing sub-units and auxiliary resistive operation storing sub-units for being connected to same bit line
The data " A " of middle storage and " B ", when the trigger voltage applied on the port for the first input unit being connected with reference cell
VCC, apply trigger voltage 0 on the port that the resistive operation stores input subelement A, and in the auxiliary resistive operation
Apply trigger voltage VCC on the port of storing sub-units, then the auxiliary resistive operation storing sub-units after triggering level triggering
On logical value realize logical "or" operation: B'=A+B.When B=0, " transmission " logic is realized.
Preferably for the resistive operation storing sub-units and auxiliary resistive operation storing sub-units for being connected to same bit line
The data " A " of middle storage and " B ", when the trigger voltage applied on the port for the first input unit being connected with reference cell
VCC, apply trigger voltage V on the port that the resistive operation stores input subelement ACC/ 2, and in the resistive operation
Apply trigger voltage 0 on the port of storage output subelement B, then the resistance of the original storing data " B " after triggering level triggering
The logical value become in operation storing sub-units realizes logic and " contains " operation:When B=0, realize
The logic of " non-".
Preferably for being connected to the data " A " stored in the resistive operation storing sub-units of same bit line and " B ", when
The trigger voltage V applied on the port for the first input unit being connected with reference cellCC/ 2, input is stored in resistive operation
Apply trigger voltage V on the port of unit ACC, and apply trigger voltage on the port that resistive operation stores output subelement B
0, then the logical value on the resistive operation output storing sub-units B after triggering level triggering realizes logical "or" operation: B'
=A+B.When B=0, " transmission " logic is realized.
Logic cascade or logical reconstruction can also be carried out to above-mentioned logic and arithmetical operation.
In this architecture, the different Resistance states of resistance value height as the input of information, output and calculating and are deposited
The variable of storage, pulse voltage signal triggers operation, and the signal sequence form of pulse voltage signal determines the type of operation.Resistance
Becoming device is non-volatile-type memory, therefore logic operation result does not need triggering level maintenance, greatly reduces the function of operation
Consumption.It can realize that same group of resistive device completes different logics, arithmetical operation task by the control of triggering level, that is, realize
Logic function reconstruct, can greatly improve the utilization efficiency of hardware cell.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present disclosure, the above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the basic logic unit being made of two total bit line resistive devices；
Fig. 2 shows the crossed array operation memory module schematic diagrames being made of resistive device；
Fig. 3 shows the system schematic based on resistive device resistance operation；
Fig. 4 shows the basic logic unit being made of two total wordline resistive devices；
Fig. 5 shows the circuit diagram called in progress " AB+C " arithmetic logic；And
Fig. 6 shows the schematic diagram and corresponding triggering level timing diagram of logical reconstruction function.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are only exemplary
, and it is not intended to limit the scope of the present disclosure.In addition, in the following description, descriptions of well-known structures and technologies are omitted, with
Avoid unnecessarily obscuring the concept of the disclosure.
The various structural schematic diagrams according to the embodiment of the present disclosure are shown in the attached drawings.These figures are not drawn to scale
, wherein some details are magnified for the purpose of clear expression, and some details may be omitted.It is shown in the drawings
The shape of various elements and relative size, positional relationship between them are merely exemplary, in practice may be due to manufacture
Tolerance or technical restriction and be deviated, and those skilled in the art may be additionally designed as required has not similar shape
Shape, size, relative position element.
In the context of the disclosure, when one layer/element is referred to as located at another layer/element "upper", which can
May exist intermediate layer/element on another layer/element or between them.In addition, if in a kind of direction
In one layer/element be located at another layer/element "upper", then when turn towards when, which can be located at another layer/member
Part "lower".
The object of the present invention is to provide a kind of using resistive device (including the resistance-variable storing device RRAM based on oxide, base
Become in the redox resistance-variable storing device CBRAM of metal ion, phase transition storage PCM, magnetoresistive memory MRAM etc. by resistance
Change the component for carrying out information storage) method for realizing Boolean algebra logical operation, data storage and transmitting is transmitted by resistance
And corresponding architecture.The resistance value of resistive device can be cut between two different resistance values by applied voltage
Change, referred to as programming (program)/erasing (erase) (or set (SET)/resets) RESET) program voltage and wipe
Polarity of voltage is on the contrary, the high low resistance state of two resistance values of storage has apparent difference.In this architecture, resistance value is high
Variable of the low different Resistance states as the input of information, output and calculating and storage, pulse voltage signal trigger operation with
And its signal sequence form determines the type of operation.
The attached logical unit shown in FIG. 1 being made of two resistive devices is suitble to when applying on port 0,1 and 2
Triggering level, the data information value with resistance form storage on resistive device A, B will do it logical operation, the knot after operation
Fruit is stored on resistive device A or B in the form of resistance value.Here, the resistance value on resistive device A and B can be used as logic
Input variable participates in operation, and participates in the resistance value of operation and the resistance logic as output logical variable after operation
Value is all stored in the resistive device for participating in operation, and information data is carried out between arithmetic element and storage unit without progress
Transmitting realizes and realizes data operation and storage using same unit.Resistive device is non-volatile-type memory, therefore logic is transported
It calculates result and does not need triggering level maintenance, greatly reduce the power consumption of operation.It participates in resistance logic arithmetic element and does not limit to 2,
The resistance value of multiple resistor-type storages can be made to participate in operation by the control of triggering level, the resistance logic value storage after operation
On participating in one of resistive device of logical operation, the unit of resistance value can be controlled by triggering level after storage operation
Selection.The memory for storing first time resistance operation result can be by execution cycle after the control of triggering level participation
Resistance logic operation is to realize the cascade of logical operation.Carry out the logic of operation, arithmetic types (with adding, subtracting or, non-)
It is selected by the type of triggering level, this shows that the same resistor-type storage unit can participate in different logic and arithmetic
In fact operation can realize that same group of resistive device completes different logics, arithmetical operation task by the control of triggering level, i.e.,
Existing logic function reconstruct, can greatly utilize hardware cell in this way.
Principle based on resistance operation and transmitting, resistive device can prepare crossed array as shown in Fig. 2.Intersecting
Include a plurality of multiple bit lines parallel to each other, a plurality of wordline being parallel to each other and the resistance between wordline and bit line in array
Become operation storing sub-units；Resistive operation storing sub-units can be single resistive device and be also possible to resistive device and double
To the concatenated structure of selector.Wordline and bit line are mutually perpendicular to, and are deposited in crossed array with the resistive operation of a line and same row
Storage subelement can directly constitute arithmetic element, and the subelement for different lines of not going together can constitute arithmetic element indirectly.Every position
One end of line and reference cell R with fixed resistanceCIt is connected, fixed resistance RCOther end by input module gate not
Same triggering level signal.RCValue between the high value and low resistance that resistive device stores, such as its for both
Geometrical mean.The other end of every bit line is connected by selection switch with input/output module；One end of every wordline
With fixed resistance RCIt is connected, fixed resistance RCOther end different triggering level signals, every word are gated by input module
The other end of line is by selecting switch to be connected with input/output module.Output module is mainly the resistance value for reading storage array
Be transformed into voltage signal facilitate in computing system other output.
Resistive operation stores crossed array and input module, output module constitute a collection information data operation and storage one
The module of body carries out data exchange by register between module and module.As shown in Fig. 3；Module is output and input point
It is not connected with input/output bus, the data on address bus are connected with the input unit in module.Operation control, which issues, to be carried out
The trigger voltage signal of operation is connected with the input module in module；Each of the control signal that operation control issues and system
Module, which is connected, coordinates input and output and operation.
Specifically, as shown in Figure 1, as the trigger voltage 0V applied on port 0, apply trigger voltage V on port 1CC/
2, apply trigger voltage V on port 2CCIf before operation, in resistive device A, B being all storage low resistance state Ron, then in triggering electricity
During pressure applies, loading the voltage at the both ends resistive device A, B is-Vcc/ 4 and Vcc/ 4 or so (voltage is big on port 3
When be negative), the resistance value in resistive device A, B can not be changed；If storing in resistor-type A, B before operation is RonAnd height
Resistance state Roff, voltage of the load at the both ends resistive device A, B is 0 and V during triggering level appliescc/ 2 or so, resistive device
Resistance value in A, B will not change；If being stored in A before operation, the resistance in unit B is RoffAnd Ron, in triggering level
Load is-V in resistive device A, the voltage at the both ends B during applyingcc/ 2 and 0 or so, the resistance value in resistive device A, B will not
It changes；If being stored in A before operation, the resistance in unit B is RoffAnd Roff, load exists during triggering level applies
A, the voltage at unit B both ends are Vcc/ 2 and VccLeft and right, the resistance value that resistor-type stores on B, which can be flipped, is set to low resistance state.Such as
Fruit RoffIt is expressed as 0, RonIt is expressed as 1；Then the logical value after triggering level triggering in unit B can be described with following formula:
B ' indicates the logical value stored in the B after operation, realizes " containing " logical operation.
If the triggering level applied is that port 0 sets 0 ,-V is set in port 1cc/ 2, V is set in port 2cc/2.If before operation, resistance
Becoming in device A, B is all storage low resistance state Ron, then during trigger voltage applies, the electricity at the both ends resistive device A, B is loaded
Pressure is-Vcc/ 2 and Vcc/ 2 or so, the resistance value in resistive device A, B can not be changed；If in resistive device A, B before operation
Storage is RonWith high-impedance state Roff, voltage of the load at the both ends resistive device A, B is 0 and V during triggering level appliescc
Or so, the resistance value stored in resistive device A will not change, and the resistance value in B can be placed in low resistance state from high-impedance state；Such as
A is stored in front of fruit operation, the resistance in unit B is RoffAnd Ron, load is in resistive device A, B during triggering level applies
The voltage at both ends is-VccWith 0 or so, the resistance value in resistive device A, B will not change；If being stored in A, B before operation
Resistance in unit is RoffAnd Roff, voltage of the load at A, unit B both ends is-V during triggering level appliescc/ 2 Hes
Vcc/ 2 or so, the resistance value in resistive device A, B will not change.Logical value after triggering level triggering in unit B can
To be described with following formula:
B'=A+B (2),
Realize the logical operation of "or".
For (1) formula, when B=0, the logic of " non-" is realized；For (2) formula, when B=0,
Realize " transmission " logic.Logical operation or arithmetical operation for any complexity can use these basic logic units
Combination is in attached drawing 2 with realizing in a line.
Carrying out logic-operated process for the resistive device that same row in Fig. 2 is not gone together can be illustrated with Fig. 4.Fig. 4 shows
The basic logic unit being made of two total wordline resistive devices is gone out.In Fig. 4, apply triggering level V on port 0cc, end
Apply level triggers level V on mouth 1cc/ 2, port 2 applies triggering level signal 0；If before operation, being all in resistive device A, B
Store low resistance state Ron, then during trigger voltage applies, loading the voltage at the both ends resistive device A, B is-Vcc/ 4 and Vcc/4
Left and right (potential is big on port 3, is positive), can not change the resistance value in resistive device A, B；If resistor-type A, B before operation
Middle storage is RonWith high-impedance state Roff, voltage of the load at the both ends resistive device A, B is 0 and during triggering level applies
Vcc/ 2 or so, the resistance value stored in resistive device A, B will not change；If being stored in A, the electricity in unit B before operation
Resistance is RoffAnd Ron, voltage of the load at the both ends resistive device A, B is-V during triggering level appliescc/ 2 and 0 or so, resistance
The resistance value become in device A, B will not change；If being stored in A before operation, the resistance in unit B is RoffAnd Roff,
Voltage of the load at A, unit B both ends is V during triggering level appliescc/ 2 and VccOr so, the resistance value in resistive device A
It will not change, the resistance stored in B can be set to low resistance state；Then the logical value after triggering level triggering in unit B can
To be described with following formula:
Realize " containing " logical operation.
For the structure in Fig. 4, as the application triggering level V on port 0cc/ 2, apply level triggers level on port 1
Vcc, port 2 applies triggering level signal 0.If before operation, in resistive device A, B being all storage Ron, then applied in trigger voltage
During adding, loading the voltage at the both ends resistive device A, B is-Vcc/ 2 and Vcc/ 2 or so (potential is big on port 3, is positive), nothing
Method changes the resistance value in resistive device A, B；If storing in the resistor-type A, B before operation is RonAnd Roff, in triggering level
Voltage of the load at the both ends resistive device A, B is 0 and V during applyingccOr so, the resistance value stored in resistive device A will not
It changes, R can be set to by being stored in resistance value in Bon；If being stored in A before operation, the resistance in unit B is RoffAnd Ron,
Voltage of the load at the both ends resistive device A, B is-V during triggering level appliesccElectricity with 0 or so, in resistive device A, B
Resistance value will not change；If being stored in A before operation, the resistance in unit B is RoffAnd Roff, apply process in triggering level
Voltage of the middle load at A, unit B both ends is-Vcc/ 2 and Vcc/ 2 or so, the resistance value in resistive device A, B will not change
Become；Then the logical value after triggering level triggering in unit B can be described with following formula:
B'=A+B (4)
Realize "or" logical operation.It can be with logical for the resistive device of same row in Fig. 2 (being connected to same bit line)
The logic for crossing combination (3) (4) formula realizes complicated logic, arithmetical operation.
Logic cascades example: D=AB+C
The resistive device one for participating in this complex logic operation shares 5: three inputs A, B, C；One exports D and one
Auxiliary unit Assist is as shown in Fig. 5.Assist and output unit are set to R before operationoff(0), first operation week
Interim, the triggering level signal applied on port 2 is Vcc/ 2, the triggering level signal applied on port 4 is Vcc, port 0 is set
Zero, other ports are to suspend, so the logical value after first sub- execution cycle in Assist isIn second execution cycle
The triggering level applied on port 1 is Vcc/ 2, the triggering level signal applied on port 4 is Vcc, 0 zero setting of port, other ports
To suspend, the logical value after second sub- execution cycle in Assist isThird execution cycle works as the touching of middle port 4
Power generation is put down as Vcc/ 2, triggering level is V on port 5cc, 0 is set on port 0, other ports suspend；Logical value after operation on D
For AB；4th sub- execution cycle is V when the triggering level of middle port 5cc, V is set on port 0cc/ 2, triggering level is set on port 3
0, other ports suspend, and the logical value after operation in D is AB+C, and processor active task is completed.
Logical reconstruction example:
As shown in Fig. 6, A, B are used in the first execution cycle, tri- resistive devices of C complete logical operation C=AB
And the result of logical operation is stored in C, if user needs to input two logical values again simultaneously in operation later
It does and non-logical operation, it is only necessary to which A before operation, the logical value in B, C is set to 0 first, and user is then written and refers to
Fixed logical value is in A, unit B；Again to A in next arithmetic element, tri- units of B, C apply suitable triggering level and are
It is achievableLogical operation and store the result into C cell.
Input and output object in above-mentioned resistive operation storage equipment according to the present invention, using resistance value as logic gate
Manage variable.Input and output physical descriptor using resistance value as logic gate, the different Resistance states of resistance value height are as information
Input, output and calculating and storage variable, pulse voltage signal triggers operation, and the signal sequence of pulse voltage signal
The type of column form decision operation.Resistive device is non-volatile-type memory, therefore logic operation result does not need triggering level
It maintains, greatly reduces the power consumption of operation.It is different can to realize that same group of resistive device is completed by the control of triggering level
Logic, arithmetical operation task, the i.e. reconstruct of realization logic function, can greatly improve the utilization efficiency of hardware cell.
Although specifically illustrating and describing the present invention, the common skill in this field by reference to exemplary embodiments of the invention
Art personnel should be appreciated that in the case where not departing from the spirit and scope of the present invention as defined in the appended claims, can be right
These embodiments carry out a variety of changes in form and details.
Claims (10)
1. a kind of resistive operation stores equipment, comprising:
The a plurality of wordline extended in a first direction；
The multiple bit lines extended along the second direction intersected with first direction；
The multiple resistives fortune for being respectively arranged at the intersection of each bit line and each wordline and being connect with respective bit line and respective word
Storing sub-units are calculated, each resistive operation storing sub-units can be switched between high-impedance state and low resistance state and therefore store corresponding
Data；
It is connected to the bit line reference cell of each bit line, wherein one end of each bit line is all connected with a bit line reference cell,
The other end of every bit line is connected by resistive operation storing sub-units with each wordline, and other the one of every bit line
End is connected by selection switch with output module；The first end of bit line reference cell is connected to bit line, and bit line reference cell
The other end different triggering level signals is gated by the first input module；
It is connected to the wordline reference cell of each wordline, wherein one end of each wordline is all connected with a wordline reference cell,
The other end of every wordline is connected by resistive operation storing sub-units with each bit line, and other the one of every wordline
End is connected by selection switch with output module；The first end of wordline reference cell is connected to wordline, and wordline reference cell
The other end different triggering level signals is gated by the second input module；And
The triggering level signal for carrying out operation is connected with the first input module or the second input module, passes through resistance by controller
The value different Resistance states of height indicate input variable, and control assists with the resistive operation storing sub-units of a line or same row
With logical-arithmetical operation is carried out, the output module connecting with wordline is controlled for single with other resistive operations storage in calculating
Member carries out data exchange, and the height that reads storage array different resistance value carries out logical variable output；
Wherein, the resistive operation storing sub-units are memristors, and there is memristor top electrode and lower electrode, memristor to power on
Pole is connected to the bit line reference cell by bit line, and the lower electrode of memristor is connected to the wordline benchmark list by wordline
Member.
2. resistive operation according to claim 1 stores equipment, wherein the resistive operation storing sub-units are based on oxygen
The resistance-variable storing device RRAM of compound, the redox resistance-variable storing device CBRAM of metal ion, phase transition storage PCM, magnetic resistance are based on
At least one storage unit in memory MRAM, the resistive operation storing sub-units carry out information dependent on resistance variations and deposit
Storage and operation.
3. resistive operation according to claim 1 stores equipment, wherein the resistive operation storing sub-units are individual
Resistive device either resistive device and the concatenated structure of two-way choice device.
4. resistive operation according to claim 1 stores equipment, wherein the bit line reference cell and wordline reference cell
Resistance value be between the high-impedance state resistance value and low resistance state resistance value of resistive operation storing sub-units.
5. resistive operation according to claim 1 stores equipment, wherein depositing for the resistive operation for being connected to same bit line
The data " A " stored in storage subelement and " B ", apply when on the port for the first input module being connected with bit line reference cell
Trigger voltage VCC, apply trigger voltage V on the port of the resistive operation storing sub-units of storing data " A "CC/ 2, and
It stores and applies trigger voltage 0V on the port of the operation storing sub-units of output variable, then depositing after trigger voltage triggering originally
Logical value in the resistive operation storing sub-units of storage data " B " realizes logic and " contains " operation:Wherein B '
Indicate the logical value being stored in the resistive operation storing sub-units of storing data " B " after logic " contains " operation.
6. resistive operation according to claim 5 stores equipment, wherein realizing the logic fortune of " non-" when B=0
It calculates.
7. resistive operation according to claim 1 stores equipment, wherein depositing for the resistive operation for being connected to same bit line
The data " A " stored in storage subelement and " B ", apply when on the port for the first input module being connected with bit line reference cell
Trigger voltage VCC/ 2, apply trigger voltage V on the port of the resistive operation storing sub-units of storing data " A "CC, and
Apply trigger voltage 0V on the port of the resistive operation storing sub-units of storing data " B ", then the resistance after triggering level triggering
The logical value become in operation storing sub-units realizes logical "or" operation: B '=A+B, after wherein B ' indicates logical "or" operation
The logical value being stored in the resistive operation storing sub-units of storing data " B ".
8. resistive operation according to claim 7 stores equipment, wherein realizing " transmission " logic when B=0.
It further include to above-mentioned logical-arithmetical operation 9. the resistive operation according to any one of claim 2 to 8 stores equipment
Carry out logic cascade or logical reconstruction.
10. resistive operation according to claim 1 stores equipment, wherein using input and output of the resistance value as logic gate
Physical descriptor.
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| DE102016123689B4 (en) * | 2016-12-07 | 2022-02-24 | Infineon Technologies Ag | Memory circuit and method of operating a memory circuit |
| CN106847335B (en) * | 2016-12-27 | 2019-03-19 | 北京大学 | Convolutional calculation storage integration apparatus and method based on resistance-change memory array |
| US11222259B2 (en) | 2017-12-13 | 2022-01-11 | International Business Machines Corporation | Counter based resistive processing unit for programmable and reconfigurable artificial-neural-networks |
| CN108182959B (en) * | 2018-01-22 | 2021-02-23 | 中国科学院微电子研究所 | Method for realizing logic calculation based on crossing array structure of resistive device |
| TWI657443B (en) * | 2018-03-19 | 2019-04-21 | 旺宏電子股份有限公司 | Memory device and operation method thereof |
| CN109214048A (en) * | 2018-07-27 | 2019-01-15 | 西南大学 | Utilize mixing CMOS- memristor fuzzy logic gate circuit and its design method |
| CN109905115B (en) * | 2019-02-27 | 2020-08-04 | 华中科技大学 | Reversible logic circuit and operation method thereof |
| CN110007897B (en) * | 2019-03-18 | 2021-01-26 | 北京大学深圳研究生院 | Logic gate based on resistive random access memory, logic circuit and calculation method |
| CN112466366B (en) * | 2020-12-09 | 2022-04-15 | 中国人民解放军国防科技大学 | Three-dimensional memristor state logic circuit and NOR logic implementation method |
| CN112466365B (en) * | 2020-12-09 | 2022-04-15 | 中国人民解放军国防科技大学 | Three-dimensional memristor state logic circuit and NOR logic implementation method |
| CN113285710B (en) * | 2021-06-04 | 2023-01-20 | 广东工业大学 | Memristor cross array-based logic gate circuit and NAND gate and NOR gate implementation method |
| CN113437964B (en) * | 2021-06-10 | 2022-09-16 | 安徽大学 | Operational circuit composed of RRAM and capable of being distinguished by resistance states and being reconstructed |
| CN113362872B (en) * | 2021-06-16 | 2022-04-01 | 华中科技大学 | Memristor-based complete nonvolatile Boolean logic circuit and operation method |
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