CN113285710A - Memristor cross array-based logic gate circuit and NAND gate and NOR gate implementation method - Google Patents

Abstract

Aiming at the limitations of the prior art, the invention provides a logic gate circuit based on a memristor crossover array, a NAND gate and a NOR gate implementation method, wherein the circuit mainly comprises two voltage controllers connected with a clock signal and the memristor crossover array composed of a plurality of memristors; the memory resistor cross array can integrate the inclusion logic and the non-inclusion logic into the same memristor cross array, and the NAND logic gate and the NOR logic gate are realized through different combined operations of the two memristor logics when the memory resistor cross array is used.

Description

Memristor cross array-based logic gate circuit and NAND gate and NOR gate implementation method

Technical Field

The invention relates to the technical field of digital circuits, in particular to application of a memristor in realizing NAND gates and NOR gates, and more particularly relates to a logic gate circuit based on a memristor cross array.

Background

With the development of semiconductor manufacturing technology, the integration level and complexity of integrated circuits are increasing, and the feature size thereof is continuously shrinking, which reaches the nanometer level at present. At the nanoscale process stage, IC faces increasing problems. The memristor as a novel nanometer device has the advantages of small size, ultralow energy consumption, short read-write time and the like, can be embedded into a cross array, and is the key for realizing large-scale storage.

Memristors can be used for logic computation in addition to data storage. Various memristor-based logics have been proposed and have been applied to implement basic logic gates in crossbar arrays. However, as the Chinese patent application with publication number CN105356876B, publication number 2018.01.26: as shown in a logic gate circuit based on a memristor, when a complex circuit is realized by applying a single logic to a cross array, the operation steps are complicated due to the single logic operation, and the expense of the memristor is large, so that the prior art still has many limitations.

Disclosure of Invention

Aiming at the limitation of the prior art, the invention provides a method for realizing a logic gate circuit, a NAND gate and a NOR gate based on a memristor cross array, and the technical scheme adopted by the invention is as follows:

a logic gate circuit based on a memristor cross array comprises W word lines WL_wAnd { W ═ 1,2 … W }, B bit lines BL_bAnd { B ═ 1,2 … B }, a first voltage controller, a second voltage controller, and { W × B } memristors M_wb；

Wherein each word line WL_wRespectively connected with each bit line BL_bIntersecting; each bit line BL_bOne end of the first voltage controller is used as an input end to be connected with the output end of the first voltage controller, and the other end of the first voltage controller is connected with an analog switch and a resistor in sequence and then grounded; each word line WL_wOne end of the first voltage controller is used as an input end and is connected with the output end of the second voltage controller, and the other end of the first voltage controller is connected with an analog switch and a resistor in sequence and then is grounded;

the input end of the first voltage controller is connected with a first clock signal CLK 1; the input end of the second voltage controller is connected with a second clock signal CLK 2;

each memristor M_wbThe positive pole of the capacitor is connected with the word line WL corresponding to the lower mark_wThe negative pole is connected with a bit line BL corresponding to the subscript_b。

Compared with the prior art, the invention provides a memristor cross array-based logic gate circuit, which can integrate the inclusion logic and the non-inclusion logic into the same memristor cross array, realize the NAND logic gate and the NOR logic gate through different combinations of two memristor logics, reduce the operation steps for realizing the NAND and NOR gates and the expenditure of memristors, and greatly reduce the overall energy consumption.

Further, the memristor M_wbStoring input quantity P or input quantity Q or logic operation result in the form of resistance value at high resistance R_OFFIn the state of a logic 0, low resistance R_ONThe state represents a logic 1.

Further, in the process of the logic operation:

memristor M according to stored input quantity P_PAnd a memristor M storing an input quantity Q_QFrom other memristors M_wbMiddle selection memristor M for auxiliary operation and storing logic operation result_A；

According to memristor M_PMemristor M_QAnd memristor M_AControl the word line WL corresponding to the subscript_wOr bit line BL_bThe analog switch is closed to communicate with the circuit to be operated at the current stage.

Further, the first clock signal CLK1 and the second clock signal CLK2 control the connected circuit to be operated to execute the implicit logic or the non-implicit logic: when the first clock signal CLK1 and the second clock signal CLK2 are at high level, a logic 1 is represented, and the circuit to be operated performs non-inclusive logic; when the clock signal is at low level, it represents logic 0, and the circuit to be operated executes the implication logic.

Further, if the memristor M_PAnd memristor M_QWord line WL with connected positive pole_wSame, then memristor M_AThe word line WL is connected to the positive pole_wOther memristor M_wbOne of them;

if memory resistor M_PAnd memristor M_QNegative connected bit line BL_bSame, then memristor M_AThe negative electrode is connected with the bit line BL_bOther memristor M_wbOne of them.

Further, if the memristor M_PAnd memristor M_QWord line WL with connected positive pole_wDifferent, bit line BL with negative electrode connected_bIf they are different, then the memristor M_AComprises the following steps: word line WL with connected positive pole_wAND memristor M_PIdentical and cathode-connected bit line BL_bAND memristor M_QThe same other memristors M_wbOr positively connected word lines WL_wAND memristor M_QIdentical and cathode-connected bit line BL_bAND memristor M_PThe same other memristors M_wb。

As a preferred scheme, the word line comprises 3 word lines WL_wAnd { w ═ 1,2,3}, 3 bit lines BL_b{ b ═ 1,2 … 3} and 9 memristors M_wb。

As a preferred scheme, the word line comprises 2 word lines WL_wAnd { w ═ 1,2}, 2 bit lines BL_b{ b ═ 1,2} and 4 memristors M_wb。

The invention also comprises the following:

a method of implementing a nand gate using the aforementioned memristor crossbar array-based logic gate, comprising the steps of:

s1, memory resistor M used for auxiliary operation and storing logic operation result in circuit_AWrite to low resistance;

s2, the memristor M storing the input quantity P is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_PAND memristor M_AExecuting non-implication logic;

s3, the memristor M storing the input quantity Q is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_QAND memristor M_APerforming the implication logic, the NAND result being stored in the memristor M_A。

A method of implementing a nor gate using the aforementioned memristor crossbar array-based logic gate circuit, comprising the steps of:

s4, writing the input Q into the circuit for assistingMemristor M for assisting in operation and storing logical operation result_A；

S5, the memristor M storing the input quantity P is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_PAND memristor M_AExecuting the implication logic;

s6, the memristor M storing the input quantity Q is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_QAND memristor M_APerforming NOT-ENDED logic, or storing the NOT result in the memristor M_A。

Drawings

FIG. 1 is a schematic diagram of a memristor crossbar array-based logic gate circuit provided in embodiment 1 of the present disclosure;

fig. 2 is a schematic diagram illustrating a circuit change of an implementation of an implication logic for a memristor in the same row according to embodiment 1 of the present disclosure;

FIG. 3 is a schematic diagram illustrating a circuit variation of the same row memristor to perform non-inclusive logic according to embodiment 1 of the present invention;

FIG. 4 is a schematic diagram illustrating a circuit variation of the implementation of the implication logic with the memristors in embodiment 1 of the present invention;

FIG. 5 is a schematic diagram of a circuit variation for implementing non-inclusive logic with a column of memristors in accordance with embodiment 1 of the present invention;

FIG. 6 is a schematic diagram of the method steps for implementing a NAND gate using the memristor crossbar array-based logic gate circuit according to embodiment 1 of the present invention;

FIG. 7 is a schematic diagram of method steps for implementing a NOR gate using the memristor crossbar array-based logic gate circuit according to embodiment 1 of the present disclosure;

FIG. 8 shows a memristor M in embodiment 2 of the present invention_P、M_QThe circuit change schematic diagram of the circuit in the functional process of realizing the NAND logic gate when the circuit is in different rows and different columns;

fig. 9 is a schematic diagram of simulation waveforms of input pulses at four pulse input terminals when the input quantity P, Q for performing nand logic is logic 1 and logic 0, respectively, according to embodiment 2 of the present invention;

FIG. 10 an embodiment of the present invention2 when the input P, Q of the nand logic is logic 1 and logic 0, respectively, it acts as a memristor M_AMemristor M₁₂A resistance value change diagram in each stage;

FIG. 11 shows a memristor M in embodiment 2 of the present invention_P、M_QThe circuit change schematic diagram of the circuit in the functional process of realizing the NOR logic gate when the circuit is in different rows and different columns;

FIG. 12 is a diagram illustrating simulation waveforms of input pulses at four pulse input terminals when the input quantity P, Q for performing NOR logic is logic 1 and logic 0, respectively, according to embodiment 2 of the present invention;

FIG. 13 shows the memristor M in embodiment 2 when the input P, Q for performing the NOR logic is logic 1 and logic 0, respectively_AMemristor M₁₂A resistance value change diagram in each stage;

FIG. 14 shows a memristor M in embodiment 4 of the present invention_P、M_QA circuit change schematic diagram of the circuit in the same row in the functional process of realizing the NAND logic gate;

FIG. 15 shows a memristor M in embodiment 4 of the present invention_P、M_QA circuit change schematic diagram of a circuit in the same row in the functional process of realizing the NOR logic gate;

FIG. 16 shows a memristor M in embodiment 5 of the present invention_P、M_QA circuit change schematic diagram of the same-column time circuit in the functional process of realizing the NAND logic gate;

FIG. 17 shows a memristor M in embodiment 5 of the present invention_P、M_QCircuit variation schematic diagram of the circuit in the process of realizing the function of the NOR logic gate in the same column.

Detailed Description

The drawings are for illustrative purposes only and are not to be construed as limiting the patent;

it should be understood that the embodiments described are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the embodiments in the present application.

The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of the present application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the application, as detailed in the appended claims. In the description of the present application, it is to be understood that the terms "first," "second," "third," and the like are used solely to distinguish one from another and are not necessarily used to describe a particular order or sequence, nor are they to be construed as indicating or implying relative importance. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

Further, in the description of the present application, "a plurality" means two or more unless otherwise specified. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. The invention is further illustrated below with reference to the figures and examples.

In order to solve the limitation of the prior art, the present embodiment provides a technical solution, and the technical solution of the present invention is further described below with reference to the accompanying drawings and embodiments.

Example 1

A logic gate circuit based on memristor crossbar array, please refer to FIG. 1, comprising W word lines WL_w，{w＝1,2 … W }, B bit lines BL_b{ B ═ 1,2 … B }, a first voltage controller 1, a second voltage controller 2, and { W × B } memristors M_wb；

Wherein each word line WL_wRespectively connected with each bit line BL_bIntersecting; each bit line BL_bOne end of the first voltage controller 1 is used as an input end to be connected with the output end of the first voltage controller 1, and the other end of the first voltage controller is connected with an analog switch and a resistor in sequence and then grounded; each word line WL_wOne end of the first voltage controller is used as an input end to be connected with the output end of the second voltage controller 2, and the other end of the first voltage controller is connected with an analog switch and a resistor in sequence and then grounded;

the input end of the first voltage controller 1 is connected with a first clock signal CLK 1; the input end of the second voltage controller 2 is connected with a second clock signal CLK 2;

each memristor M_wbThe positive pole of the capacitor is connected with the word line WL corresponding to the lower mark_wThe negative pole is connected with a bit line BL corresponding to the subscript_b。

Compared with the prior art, the invention provides a memristor cross array-based logic gate circuit, which can integrate the inclusion logic and the non-inclusion logic into the same memristor cross array, realize the NAND logic gate and the NOR logic gate through different combinations of two memristor logics, reduce the operation steps for realizing the NAND and NOR gates and the expenditure of memristors, and greatly reduce the overall energy consumption.

Specifically, the word line WL_wAnd bit line BL_bAre nanowires. W is more than or equal to 2, and B is more than or equal to 2. In fig. 1, Vin1, Vin2, Vin3, and Vin4 respectively represent bit lines BL₁、BL₂Word line WL₁、WL₂The ellipses next to the first voltage controller 1 represent the other bit lines BL at the input of_bThe ellipses beside the second voltage controller 2 represent the other word lines WL_w。

About "each memristor M_wbThe positive pole of the capacitor is connected with the word line WL corresponding to the lower mark_wThe negative pole is connected with a bit line BL corresponding to the subscript_b": for example memristor M₁₂The positive pole of the word line is connected with the word line WL corresponding to the first subscript "1₁The negative pole is connected with the bit line BL corresponding to the second subscript "2₂(ii) a And by analogy, a memristor cross array is formed.

And the same word line WL is connected to the positive pole_wThe memristors in the "same row" can be regarded as memristors: for example memristor M₁₁、M₁₂Word lines WL, the anodes of which are connected to the word line WL, each corresponding to a first index "1₁Both are memristors located "in the same row".

And the same bit line BL is connected to the negative electrode_bThe memristors in the "same column" can be regarded as memristors: for example memristor M₁₁、M₂₁The negative poles of which are connected bit lines BL corresponding to the second subscript "1₁Both are memristors located "in the same column".

Thus, memristor M_wbIt can also be understood as a memristor located in the w-th row and b-th column of the memristor crossbar array.

The logic gate circuit based on the memristor crossbar array provided by the embodiment controls the communication of the corresponding line through the analog switch, and combines the signal of the input end to realize the inclusion logic and the non-inclusion logic on the corresponding line, so that the nand logic gate and the nor logic gate are realized through the combination of the inclusion logic and the non-inclusion logic.

Further, the memristor M_wbStoring input quantity P or input quantity Q or logic operation result in the form of resistance value at high resistance R_OFFIn the state of a logic 0, low resistance R_ONThe state represents a logic 1.

Further, in the process of logic operation, according to the memristor M storing the input quantity P_PAnd a memristor M storing an input quantity Q_QFrom other memristors M_wbMiddle selection memristor M for auxiliary operation and storing logic operation result_A。

Further, in the process of logic operation, according to the memristor M_PMemristor M_QAnd memristor M_AControl the word line WL corresponding to the subscript_wOr bit line BL_bAnalog switch ofAnd closing and communicating the circuit to be operated at the current stage.

In particular, memristor M_PMemristor M_QAnd memristor M_ARefer to its role in the logic operation process only, the specific corresponding memristor M_wbThe subscript indicating the connection relationship with the word line and the bit line is not changed. The input quantity P or Q is stored in the memristor M in advance before logic operation_P、M_QIn (1).

Further, the first clock signal CLK1 and the second clock signal CLK2 control the connected circuit to be operated to execute the implicit logic or the non-implicit logic: when the first clock signal CLK1 and the second clock signal CLK2 are at high level, a logic 1 is represented, and the circuit to be operated performs non-inclusive logic; when the clock signal is at low level, it represents logic 0, and the circuit to be operated executes the implication logic.

Specifically, for the implementation principle of implementing the inclusion logic and the non-inclusion logic based on the logic gate circuit of the memristor crossbar array, four memristors M are used next₁₁、M₁₂、M₂₁、M₂₂The description is given for the sake of example:

referring to FIG. 2 and truth table 1, when the first clock signal CLK1 is low, the word line WL is asserted₁When the analog switch S1 is closed, the first voltage controller 1 is at the bit line BL₁、BL₂Respectively input a negative low level and a negative high level, wherein V_CONDAnd V_SETRespectively representing bit lines BL of the circuit when the same row of memristors execute the implication logic circuit₁、BL₂The level of the input of (1); memristor M₁₁Memristor M₁₂And word line WL₁Resistance R of_G1Forming a via, memristor M₁₁AND memristor M₁₂Executing the implication logic, storing the execution result in the form of resistance in the memristor M₁₂Performing the following steps; in truth table, M₁₁' and M₁₂' respectively being memristors M₁₁And memristor M₁₂Logic state after the logic operation is performed.

Referring to FIG. 3 and truth table 1, when the first clock signal CLK1 is high, the word line is assertedWL₁When the analog switch S1 is closed, the first voltage controller 1 is at the bit line BL₁、BL₂Respectively input a negative low level and a positive high level, V in the figure_COND-and V_COND+ represents the bit line BL when the circuit performs the non-inclusive logic circuit with the same row of memristors₁、BL₂The level of the input of (1); memristor M₁₁Memristor M₁₂And word line WL₁Resistance R of_G1Forming a via, memristor M₁₁Memristor M₁₂Executing non-implication logic, storing the execution result in the form of resistance value in the memristor M₁₂Performing the following steps; in truth table, M₁₁' and M₁₂' respectively being memristors M₁₁And memristor M₁₂Logic state after the logic operation is performed.

Truth table 1

Referring to FIG. 4 and truth table 2, when the second clock signal CLK2 is low, the bit line BL is asserted₂When the analog switch S4 is closed, the second voltage controller 2 is at the word line WL₁、WL₂The input end respectively inputs a positive low level and a positive high level, and the memristor M₂₂Memristor M₁₂And bit line BL₂Resistance R of_G4Forming a via, memristor M₂₂And memristor M₁₂Execution implication logic, the execution result is stored in the memristor M₁₂Performing the following steps; in truth table, M₂₂' and M₁₂' respectively being memristors M₂₂And memristor M₁₂Logic state after the logic operation is performed.

Referring to FIG. 5 and truth table 2, when the second clock signal CLK2 is high, the bit line BL is asserted₂When the analog switch S4 is closed, the second voltage controller 2 is at the word line WL₁、WL₂The upper input end respectively inputs a positive low level and a negative high level, V in the figure₁And V₂Respectively representing word lines WL of the circuit when the same column of memristors execute non-inclusive logic circuit₁、WL₂Level of input at input terminal, memristor M₂₂Memristor M₁₂And bit line BL₂Resistance R of_G4Forming a via, memristor M₂₂And memristor M₁₂Executing non-implication logic, storing the execution result in the memristor M₁₂Performing the following steps; in truth table, M₂₂' and M₁₂' respectively being memristors M₂₂And memristor M₁₂Logic state after the logic operation is performed.

Truth table 2

For the logic gate circuit based on the memristor crossbar array, the process of realizing the inclusion logic and the non-inclusion logic by other memristor combinations is similar to the above description, and a person skilled in the art can perform expansion transformation according to the above description, and also belongs to the protection scope of the patent, and details are not repeated here. The first voltage controller 1 and the second voltage controller 2 change the word line WL according to the input clock signal_wAnd bit line BL_bThe signals at the input terminals belong to the prior art, and are not specifically described herein.

So far, the different combinations of the inclusive logic and the non-inclusive logic can realize the functions of the nand logic gate and the nor logic gate on the logic gate circuit based on the memristor crossbar array provided by the embodiment:

specifically, a method for implementing a nand gate using the aforementioned logic gate circuit based on the memristor crossbar array, please refer to fig. 6, includes the following steps:

s1, in the circuitMemristor M for auxiliary operation and storing logic operation result_AWrite to low resistance;

s2, the memristor M storing the input quantity P is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_PAND memristor M_AExecuting non-implication logic;

s3, the memristor M storing the input quantity Q is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_QAND memristor M_APerforming the implication logic, the NAND result being stored in the memristor M_A。

Specifically, a method for implementing a nor gate using the aforementioned memristor crossbar array-based logic gate circuit, please refer to fig. 7, includes the following steps:

s4, writing the input quantity Q into the memristor M used for auxiliary operation and storing logic operation result in the circuit_A；

S5, the memristor M storing the input quantity P is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_PAND memristor M_AExecuting the implication logic;

s6, the memristor M storing the input quantity Q is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_QAND memristor M_APerforming NOT-ENDED logic, or storing the NOT result in the memristor M_A。

Example 2

This embodiment can be regarded as a modification or improvement on the basis of embodiment 1: specifically, if memristor M_PAnd memristor M_QWord line WL with connected positive pole_wDifferent, bit line BL with negative electrode connected_bIf they are different, then the memristor M_AComprises the following steps: word line WL with connected positive pole_wAND memristor M_PIdentical and cathode-connected bit line BL_bAND memristor M_QThe same other memristors M_wbOr positively connected word lines WL_wAND memristor M_QAre identical to each otherAnd bit line BL connected to negative electrode_bAND memristor M_PThe same other memristors M_wb。

In other words, if the memristor M_PAND memristor M_QNeither in the same row nor in the same column, should be in the same row as the memristor M_PIn the same line and with memristor M_QOther memristors M in the same column_wbOr with memristor M_PIn-line and with memristor M_QOther memristors M in the same row_wbMiddle selection memristor M_A。

Next with three of the memristors M₁₁、M₂₂、M₁₂Respectively as memristors M_P、M_Q、M_AFor example, briefly describe the memristor M_P、M_QThe process of implementing the function of a nand logic gate, nor logic gate, on a memristor crossbar array-based logic gate circuit when neither the row nor the column is the same:

the process of implementing the function of the nand logic gate is shown in fig. 6: first, the memristor M₁₂Write to low resistance; second, memristor M₁₁AND memristor M₂₂Executing non-implication logic; thirdly, memory resistor M₂₂And memristor M₁₂Performing the implication logic, the final NAND result is stored in the memristor M₁₂In (1).

The following is a specific description of the process of implementing the nand logic gate function in this embodiment in conjunction with the magnitude of the input P, Q:

when the input amount P, Q of the execution NAND logic is all logic 0, the memristor M₁₁And memristor M₂₂All are high resistance; first step, bit line BL₂Is inputted with a negative high level, the analog switch S1 is closed, and the word line WL₁On, current flows from resistor R_G1Flowing-through memristor M₁₂Memristor M₁₂When the voltage reaches the turn-on threshold voltage, the memristor M₁₂Written as low resistance; second, CLK1 applies a high signal, and first voltage controller 1 is on bit line BL₁Input negative low level, at bit line BL₂Is input with a positive high level, the analog switch S1 is closed, and the word line WL₁Switching on, memory resistanceMachine M₁₁And memristor M₁₂Performing non-inclusive logic, memristor M₁₂The resistance value is not changed; in a third step, CLK2 applies a low signal, and the second voltage controller 2 is on the word line WL₂Input terminal of the word line WL receives a positive low voltage₁Input with a positive high voltage, analog switch S4 closed, bit line BL₂Switch-on, memory resistor M₂₂And memristor M₁₂Performing an inclusion logic, memristor M₁₂Becomes on state R_ONNamely, the output result is logic 1;

when the two inputs of the NAND logic are logic 0 and logic 1, respectively, the memristor M₁₁The resistance value of (1) is high resistance, and the memristor M₂₂Is low resistance, first step, bit line BL₂Is inputted with a negative high level, the analog switch S1 is closed, and the word line WL₁On, current flows from resistor R_G1Flowing-through memristor M₁₂Memristor M₁₂When the voltage reaches the turn-on threshold voltage, the memristor M₁₂Written as low resistance, the second step, CLK1 applies a high signal, the first voltage controller 1 is on the bit line BL₁Input negative low level, at bit line BL₂Is input with a positive high level, the analog switch S1 is closed, and the word line WL₁Switch-on, memory resistor M₁₁And memristor M₁₂Performing non-inclusive logic, memristor M₁₂The resistance is not changed, in the third step, CLK2 applies low level signal, the second voltage controller 2 is on the word line WL₂Input terminal of the word line WL receives a positive low voltage₁Input with a positive high voltage, analog switch S4 closed, bit line BL₂On, memristor M22 and memristor M₁₂Performing an inclusion logic, memristor M₁₂Resistance R when the resistance is still in the on state_ONNamely, the output result is logic 1;

when the two inputs of the NAND logic are logic 1 and logic 0, respectively, the memristor M₁₁The resistance value of (1) is low resistance, and the memristor M₂₂The resistance value of (B) is high, first step, bit line BL₂Is inputted with a negative high level, the analog switch S1 is closed, and the word line WL₁On, current flows from resistor R_G1Flowing-through memristor M₁₂Memristor M₁₂When the voltage reaches the turn-on threshold voltage, the memristor M₁₂Written as low resistance, the second step, CLK1 applies a high signal, the first voltage controller 1 is on the bit line BL₁Input negative low level, at bit line BL₂Is input with a positive high level, the analog switch S1 is closed, and the word line WL₁Switch-on, memory resistor M₁₁And memristor M₁₂Performing non-inclusive logic, memristor M₁₂Resistance R when the resistance gradually increases to the off state_OFF(ii) a In a third step, CLK2 applies a low signal, and the second voltage controller 2 is on the word line WL₂Input terminal of the word line WL receives a positive low voltage₁Input with a positive high voltage, analog switch S4 closed, bit line BL₂Switch-on, memory resistor M₂₂And memristor M₁₂Performing an inclusion logic, memristor M₁₂Resistance R when the resistance is gradually reduced to the on state_ONNamely, the output result is logic 1; more specifically, in the pulse waveform simulation, see fig. 7, when two inputs of the nand logic are respectively logic 1 and logic 0, the input pulse diagram of four pulse input terminals can be seen; as memristors M_AMemristor M₁₂The resistance value change in each stage is shown in FIG. 8, and the resistance value of the memristor M2 is low-resistance R through three logic operation steps_ONI.e. a logical 1, corresponds to the expected result.

When the two inputs of the NAND logic are all logic 1, the memristor M₁₁And memristor M₂₂The resistance values are all low resistance; first step, bit line BL₂Is inputted with a negative high level, the analog switch S1 is closed, and the word line WL₁On, current flows from resistor R_G1Flowing-through memristor M₁₂Memristor M₁₂When the voltage reaches the turn-on threshold voltage, the memristor M₁₂Written as low resistance; second, CLK1 applies a high signal, and first voltage controller 1 is on bit line BL₁Input negative low level, at bit line BL₂Is input with a positive high level, the analog switch S1 is closed, and the word line WL₁Switch-on, memory resistor M₁₁And memristor M₁₂Performing non-inclusive logic, memristor M₁₂Resistance chasingResistance R gradually increases to an off state_OFF(ii) a In a third step, CLK2 applies a low signal, and the second voltage controller 2 is on the word line WL₂Input terminal of the word line WL receives a positive low voltage₁Input with a positive high voltage, analog switch S4 closed, bit line BL₂Switch-on, memory resistor M₂₂And memristor M₁₂Performing an inclusion logic, memristor M₁₂Resistance remains off state R_OFFAnd the output result is not changed, namely the output result is logic 0.

The process of implementing the function of nor gate, please refer to fig. 9: first, write the input Q to the memristor M₁₂Performing the following steps; second, memristor M₁₁And memristor M₁₂Executing the implication logic; thirdly, memory resistor M₂₂And memristor M₁₂Performing NOT-IMPLANT logic, the final NOT result being stored in the memristor M₁₂In (1).

The following is a specific description of the process of implementing the nor gate function of the present embodiment in conjunction with the magnitude of the input P, Q:

when both inputs of the NOR logic are all logic 0, the memristor M₁₁And memristor M₂₂All are high-impedance, first step, bit line BL₂Is input with a positive high level, the analog switch S1 is closed, and the word line WL₁On, current flows from resistor R_G1Flowing-through memristor M₁₂Memristor M₁₂Reaches the turn-off threshold voltage, memristor M₁₂Written as high impedance, and the second step, CLK1 applies a low signal, the first voltage controller 1 is on bit line BL₁Input negative low level, at bit line BL₂Is inputted with a negative high level, the analog switch S1 is closed, and the word line WL₁Switch-on, memory resistor M₁₁And memristor M₁₂Performing an inclusion logic, memristor M₁₂The resistance R is gradually reduced to the on state_ONIn the third step, CLK2 applies a high signal, and the second voltage controller 2 applies a high signal to the word line WL₂Input terminal of the word line WL receives a positive low voltage₁Input negative high voltage, analog switch S4 closed, bit line BL₂Switch-on, memory resistor M₂₂Memory and resistance deviceM₁₂Performing non-inclusive logic, memristor M₁₂Resistance value of (1) remains on-state R_ONNamely, the output result is logic 1;

when the two inputs of the NOR logic are logic 0 and logic 1, respectively, the memristor M₁₁Resistance value of high resistance, memory resistor M₂₂Resistance value of low resistance, first step, bit line BL₂Is inputted with a negative high level, the analog switch S1 is closed, and the word line WL₁On, current flows from resistor R_G1Flowing-through memristor M₁₂Memristor M₁₂When the voltage reaches the turn-on threshold voltage, the memristor M₁₂Written as low resistance, the second step, CLK1 applies a low level signal, the first voltage controller 1 is on the bit line BL₁Input negative low level, at bit line BL₂Is inputted with a negative high level, the analog switch S1 is closed, and the word line WL₁Switch-on, memory resistor M₁₁And memristor M₁₂Performing an inclusion logic, memristor M₁₂Resistor R with resistance kept in on state_ONIn a third step, CLK2 applies a high signal and the second voltage controller 2 is applied to the word line WL₂Input terminal of the word line WL receives a positive low voltage₁Input negative high voltage, analog switch S4 closed, bit line BL₂Switch-on, memory resistor M₂₂And memristor M₁₂Performing non-inclusive logic, memristor M₁₂The resistance value of can only gradually reach the state R when the switch is turned off_OFFNamely, the output result is logic 0;

when the two inputs of the NOR logic are respectively logic 1 and logic 0, the memristor M₁₁Resistance value of low resistance, memory resistor M₂₂Resistance value is high, first step, bit line BL₂Is input with a positive high level, the analog switch S1 is closed, and the word line WL₁On, current flows from resistor R_G1Flowing-through memristor M₁₂Memristor M₁₂Reaches the turn-off threshold voltage, memristor M₁₂Written as high impedance, and the second step, CLK1 applies a low signal, the first voltage controller 1 is on bit line BL₁Input negative low level, at bit line BL₂Input negative high, analog switch S1 closed, word lineWL₁Switch-on, memory resistor M₁₁And memristor M₁₂Performing an inclusion logic, memristor M₁₂Resistance R when resistance remains off state_OFFIn a third step, CLK2 applies a high signal and the second voltage controller 2 is applied to the word line WL₂Input terminal of the word line WL receives a positive low voltage₁Input negative high voltage, analog switch S4 closed, bit line BL₂Switch-on, memory resistor M₂₂And memristor M₁₂Performing non-inclusive logic, memristor M₁₂Resistance value of (1) remains off-state R_OFFNamely, the output result is logic 0; more specifically, in the pulse waveform simulation, see fig. 10, when two inputs of the nor logic are respectively logic 1 and logic 0, the input pulse diagram of four pulse input terminals can be seen; as memristors M_AMemristor M₁₂The resistance value change in each phase is shown in FIG. 11, and the resistance value of the memristor M2 is low-resistance R through three logic operation steps_OFFI.e., logic 0, consistent with the expected result;

when both inputs of the NOR logic are all logic 1, the memristor M₁₁And memristor M₂₂All are low resistance, first step, bit line BL₂Is inputted with a negative high level, the analog switch S1 is closed, and the word line WL₁On, current flows from resistor R_G1Flowing-through memristor M₁₂Memristor M₁₂When the voltage reaches the turn-on threshold voltage, the memristor M₁₂Written as low resistance, the second step, CLK1 applies a low level signal, the first voltage controller 1 is on the bit line BL₁Input negative low level, at bit line BL₂Is inputted with a negative high level, the analog switch S1 is closed, and the word line WL₁Switch-on, memory resistor M₁₁And memristor M₁₂Performing an inclusion logic, memristor M₁₂Resistor R with resistance kept in on state_ONIn a third step, CLK2 applies a high signal and the second voltage controller 2 is applied to the word line WL₂Input terminal of the word line WL receives a positive low voltage₁Input negative high voltage, analog switch S4 closed, bit line BL₂Switch-on, memory resistor M₂₂And memristor M₁₂Performing non-implication logicEditing and memory resistor M₁₂Gradually decreases to the off-state R_OFFI.e. the output result is logic 0.

Example 3

This embodiment can be regarded as a modification or improvement on the basis of embodiment 2: specifically, in the present embodiment, W ═ B ═ 2, that is, the memristor crossbar array-based logic gate circuit includes 2 word lines WL_wAnd { w ═ 1,2}, 2 bit lines BL_b{ b ═ 1,2} and 4 memristors M_wb。

The embodiment is a scheme that the minimum number of memristors is needed for realizing functions of a NAND logic gate or a NOR logic gate based on a logic gate circuit of a memristor crossbar array.

Example 4

This embodiment can be regarded as a modification or improvement on the basis of embodiment 1 or 2: specifically, if memristor M_PAnd memristor M_QWord line WL with connected positive pole_wSame, then memristor M_AThe word line WL is connected to the positive pole_wOther memristor M_wbOne of them. In other words, if the memristor M_PAND memristor M_QOther memristors M in the same row_wbOne of which selects the memristor M_A。

Next with three of the memristors M₁₁、M₁₂、M₁₃Respectively as memristors M_P、M_Q、M_AFor example, briefly describe the memristor M_P、M_Q、M_AWhen the logic gate circuits are positioned on the same row, the logic gate circuits based on the memristor cross array realize the functions of a NAND logic gate or a NOR logic gate:

the process of implementing the function of the NAND gate, referring to FIG. 12, first step, will be to memristor M₁₃Write to low resistance; second, memristor M₁₁AND memristor M₁₃Executing non-implication logic; thirdly, memory resistor M₁₂And memristor M₁₃Performing the implication logic, the final NAND result is stored in the memristor M₁₃In (1).

Implementing the function of a NOR logic gateReferring to fig. 13, in a first step, an input quantity Q is written into a memristor M₁₃Performing the following steps; second, memristor M₁₁And memristor M₁₃Executing the implication logic; thirdly, memory resistor M₁₂And memristor M₁₃Performing NOT-IMPLANT logic, the final NOT result being stored in the memristor M₁₃In (1).

Example 5

This embodiment can be regarded as a modification or improvement on the basis of embodiment 1 or 2: specifically, if memristor M_PAnd memristor M_QNegative connected bit line BL_bSame, then memristor M_AThe negative electrode is connected with the bit line BL_bOther memristor M_wbOne of them. In other words, if the memristor M_PAND memristor M_QOther memristors M in the same column_wbOne of which selects the memristor M_A。

Next with three of the memristors M₁₁、M₂₁、M₃₁Respectively as memristors M_P、M_Q、M_AFor example, briefly describe the memristor M_P、M_Q、M_AWhen located in the same column, the logic gate circuit based on the memristor crossbar array realizes the functions of a NAND logic gate or a NOR logic gate:

the process of implementing the function of the NAND gate, referring to FIG. 14, first step, will be to memristor M₃₁Write to low resistance; second, memristor M₁AND memristor M₃₁Executing non-implication logic; thirdly, memory resistor M₂₁And memristor M₃₁Performing the implication logic, the final NAND result is stored in the memristor M₃₁In (1).

The process of implementing the function of the nor gate, see fig. 15, first step, writes an input quantity Q to a memristor M₃₁Performing the following steps; second, memristor M₁₁And memristor M₃₁Performing the implication logic, third step, memristor M₂₁And memristor M₃₁Performing NOT-IMPLANT logic, the final NOT result being stored in the memristor M₃₁In

Example 6

This embodiment can be regarded as a modification or improvement on the basis of embodiments 1,2, 4, 5: specifically, in the present embodiment, W ═ B ═ 3, that is, the memristor crossbar array-based logic gate circuit includes 3 word lines WL_wAnd { w ═ 1,2,3}, 3 bit lines BL_b{ b ═ 1,2 … 3} and 9 memristors M_wb，

The embodiment is that the logic gate circuit based on the memristor cross array realizes the functions of a NAND logic gate and a NOR logic gate, and the memristor M can be used for memorizing_P、M_QUnder the condition of different rows and different columns, the memristor M can be used_P、M_QIn the case of the same row, the memristor M can be used_P、M_QIn the same column, the solution of minimum number of memristors is needed to execute the implication logic and the non-implication logic.

It should be understood that the above-described embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the protection scope of the claims of the present invention.

Claims (10)

1. A logic gate circuit based on a memristor cross array is characterized by comprising W word lines WL_wAnd { W ═ 1,2 … W }, B bit lines BL_bAnd { B ═ 1,2 … B }, a first voltage controller (1), a second voltage controller (2), and { W × B } memristors M_wb；

Wherein each word line WL_wRespectively connected with each bit line BL_bIntersecting; each bit line BL_bOne end of the first voltage controller is respectively used as an input end to be connected with the output end of the first voltage controller (1), and the other end of the first voltage controller is respectively connected with an analog switch and a resistor in sequence and then grounded; each word line WL_wIs respectively used as an input end to be connected with the output end of the second voltage controller (2)The other end of the analog switch is connected with an analog switch and a resistor in sequence and then grounded;

the input end of the first voltage controller (1) is connected with a first clock signal CLK 1; the input end of the second voltage controller (2) is connected with a second clock signal CLK 2;

each memristor M_wbThe positive pole of the capacitor is connected with the word line WL corresponding to the lower mark_wThe negative pole is connected with a bit line BL corresponding to the subscript_b。

2. The memristor crossbar array-based logic gate circuit of claim 1, wherein the memristor M is_wbStoring input quantity P or input quantity Q or logic operation result in the form of resistance value at high resistance R_OFFIn the state of a logic 0, low resistance R_ONThe state represents a logic 1.

3. The memristor crossbar array-based logic gate circuit of claim 1, wherein during the logic operation:

memristor M according to stored input quantity P_PAnd a memristor M storing an input quantity Q_QFrom other memristors M_wbMiddle selection memristor M for auxiliary operation and storing logic operation result_A；

According to memristor M_PMemristor M_QAnd memristor M_AControl the word line WL corresponding to the subscript_wOr bit line BL_bThe analog switch is closed to communicate with the circuit to be operated at the current stage.

4. The memristor crossbar array-based logic gate circuit of claim 3, wherein during the logic operation, the first clock signal CLK1 and the second clock signal CLK2 control the connected to-be-operated circuit to perform either the implied logic or the non-implied logic: when the first clock signal CLK1 and the second clock signal CLK2 are at high level, a logic 1 is represented, and the circuit to be operated performs non-inclusive logic; when the clock signal is at low level, it represents logic 0, and the circuit to be operated executes the implication logic.

5. The memristor crossbar array-based logic gate circuit of claim 4, wherein if memristor M_PAnd memristor M_QWord line WL with connected positive pole_wSame, then memristor M_AThe word line WL is connected to the positive pole_wOther memristor M_wbOne of them;

if memory resistor M_PAnd memristor M_QNegative connected bit line BL_bSame, then memristor M_AThe negative electrode is connected with the bit line BL_bOther memristor M_wbOne of them.

6. The memristor crossbar array-based logic gate circuit of claim 4, wherein if memristor M_PAnd memristor M_QWord line WL with connected positive pole_wDifferent, bit line BL with negative electrode connected_bIf they are different, then the memristor M_AComprises the following steps: word line WL with connected positive pole_wAND memristor M_PIdentical and cathode-connected bit line BL_bAND memristor M_QThe same other memristors M_wbOr positively connected word lines WL_wAND memristor M_QIdentical and cathode-connected bit line BL_bAND memristor M_PThe same other memristors M_wb。

7. The memristor crossbar array-based logic gate circuit of any one of claims 1 to 5, comprising 3 word lines WL_wAnd { w ═ 1,2,3}, 3 bit lines BL_b{ b ═ 1,2 … 3} and 9 memristors M_wb。

8. The memristor crossbar array-based logic gate circuit of claims 1-4 and 6, comprising 2 word lines WL_wAnd { w ═ 1,2}, 2 bit lines BL_b{ b ═ 1,2} and 4 memristors M_wb。

9. A method of implementing a nand gate using the memristor crossbar array-based logic gate circuit of claims 1-8, comprising the steps of:

s1, memory resistor M used for auxiliary operation and storing logic operation result in circuit_AWrite to low resistance;

s2, the memristor M storing the input quantity P is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_PAND memristor M_AExecuting non-implication logic;

s3, the memristor M storing the input quantity Q is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_QAND memristor M_APerforming the implication logic, the NAND result being stored in the memristor M_A。

10. A method of implementing a nor gate using the memristor crossbar array-based logic gate circuit of claims 1-8, comprising the steps of:

s4, writing the input quantity Q into the memristor M used for auxiliary operation and storing logic operation result in the circuit_A；

S5, the memristor M storing the input quantity P is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_PAND memristor M_AExecuting the implication logic;

s6, the memristor M storing the input quantity Q is controlled by changing the communication condition in the circuit and the input quantity of the first clock signal CLK1 or the second clock signal CLK2_QAND memristor M_APerforming NOT-ENDED logic, or storing the NOT result in the memristor M_A。

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