CN205881419U - Driver chip and LED display device of LED display screen - Google Patents
Driver chip and LED display device of LED display screen Download PDFInfo
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- CN205881419U CN205881419U CN201620680699.5U CN201620680699U CN205881419U CN 205881419 U CN205881419 U CN 205881419U CN 201620680699 U CN201620680699 U CN 201620680699U CN 205881419 U CN205881419 U CN 205881419U
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Abstract
The utility model provides a driver chip and LED display device of LED display screen relates to circuit technical field. The utility model provides a pair of the driver chip of LED display screen holds with a plurality of return circuits including the data output end who links to each other with the LED display screen respectively, and driver chip still includes: output register unit, aversion register unit and output driver unit, triggering signal is received to output register unit's trigger end, the messenger of output driver unit can receive enable signal by the termination, output register unit sends data signal according to triggering signal to aversion register unit, the output driver unit sends data signal according to enable signal and shows for the LED display screen, output register unit after sending data signal to aversion register unit alright receive new data signal immediately again, and then send data signal the data content in refreshing output register unit for the LED display screen when showing at the output driver unit, with the data refresh rate that can improve driver chip.
Description
Technical field
This utility model belongs to circuit engineering field, particularly relates to driving chip and the LED display dress of a kind of LED display
Put.
Background technology
The driving chip operation principle of existing LED display is first to sample data signal according to clock, and by
Position is deposited, and further according to triggering signal (latch signal), by the outfan of driving chip, data signal is sent to LED and shows
Display screen shows.But, along with LED display trend towards all the more lamp LED in close mode, i.e. LED display it
Between distance more and more less, the data scanning line number of LED display increases therewith, and the driving chip of existing LED display is only
By increasing corresponding clock signal frequency, and then improve the driving chip refresh rate to transmission data, cannot ensure LED
The normal display of display screen.
In sum, the driving chip of existing LED display exists cannot provide higher data brush for LED display
The problem of new rate.
Utility model content
The purpose of this utility model embodiment is to provide the driving chip of a kind of LED display, it is intended to solve existing
There is the problem that cannot provide higher Refresh Data rate for LED display in the driving chip of LED display.
This utility model embodiment is achieved in that the driving chip of a kind of LED display, including showing with LED respectively
The data output end that display screen is connected and multiple loops end, described driving chip also includes: output deposit unit, shifting deposit unit
And output driver element；
The triggering end of described output deposit unit receives and triggers signal, and the signal input part of described output deposit unit receives
Data signal, the signal output part of described output deposit unit is connected with the signal receiving end of described shifting deposit unit；
The signal sending end of described shifting deposit unit is connected with the signal input part of described output driver element, described defeated
The Enable Pin going out driver element receives enable signal；
Described output deposit unit sends described data signal, institute according to described triggering signal to described shifting deposit unit
State output driver element, according to described enable signal, the described data signal in described shifting deposit unit is sent to described LED
Display screen shows, described output deposit unit connects after sending described data signal to described shifting deposit unit again
Receive new data signal, show described data signal being sent to described LED display at described output driver element
While refresh the data content in described output deposit unit.
Further, described driving chip also includes: primary shifting deposit unit；
First signal input part of described primary shifting deposit unit receives data signal, described primary shifting deposit unit
Secondary signal input receive clock signal, the first signal output part of described primary shifting deposit unit is posted with described output
The signal input part of memory cell is connected, and the secondary signal outfan of described primary shifting deposit unit is the outputs of driving chip data
End, described primary shifting deposit unit is sent to the signal input part of described output deposit unit by its first signal output part
Described data signal.
Further, described output deposit unit includes resistance R1, the first phase inverter and output latch；
First end of described resistance R1 is connected with the input of described first phase inverter and forms a node, and this node is institute
Stating the triggering end of output deposit unit, the outfan of described first phase inverter is connected with the triggering end of described output latch, institute
Stating the signal input part that input is described output deposit unit of output latch, the outfan of described output latch is institute
State the signal output part of output deposit unit.
Further, described shifting deposit unit includes that shift register, the input of described shift register are described
The signal receiving end of shifting deposit unit, the outfan of described shift register is that the signal of described shifting deposit unit sends
End, the controlled end of described shift register is connected with described output driver element.
Further, described output driver element includes that resistance R2, the second phase inverter, output driver, output electric current are adjusted
Joint device and multiple constant-current source；
First termination power of described resistance R2, the input phase of second end of described resistance R2 and described second phase inverter
Even, the input of described second phase inverter is the Enable Pin of described output driver element, and the outfan of described second phase inverter is altogether
Connect described output driver triggers end and the controlled end of described shift register, and described output driver includes with the plurality of
Multiple loops end that constant-current source is corresponding, the input of the plurality of constant-current source is multiple loops end of described driving chip, described
The outfan of multiple constant-current sources is connected with multiple loops end one_to_one corresponding of described driver, it is achieved described driving chip is with described
Loop is formed between LED display.
Further, described primary shifting deposit unit includes: the first trigger, the second trigger, primary depositor with
And output state；
The input of described first trigger is the first signal input part of described primary shifting deposit unit, described first
The output of trigger terminates the data input pin of described depositor, and the input of described second trigger is that described primary displacement is posted
The secondary signal input of memory cell, the clock signal input of the described primary depositor of output termination of described second trigger
End, the first outfan of described primary depositor is the first signal output part of described primary shifting deposit unit, described primary
Second output of depositor terminates the first end of described output buffer, and the second end of described output buffer is described primary shifting
The secondary signal outfan of position deposit unit.
Further, described first trigger and described second trigger are respectively Schmidt trigger, and described primary is posted
Storage is sixteen bit register, 32 bit registers or 64 bit registers.
Further, described shift register is sixteen bit register, 32 bit registers or 64 bit registers.
Further, described output latch is sixteen bit register, 32 bit registers or 64 bit registers.
Another object of the present utility model is to provide a kind of LED display, and described LED display includes as above
The driving chip of LED display.
This utility model provides driving chip and LED display, the driving of this LED display of a kind of LED display
Including the data output end being connected with LED display respectively and multiple loops end, driving chip also includes: output deposit unit,
Shifting deposit unit and output driver element；The triggering end of output deposit unit receives and triggers signal；Shifting deposit unit
Signal sending end is connected with the signal input part of output driver element, and the Enable Pin of output driver element receives and enables signal；Defeated
Going out deposit unit and send data signal according to triggering signal to shifting deposit unit, output driver element is according to enabling signal by number
The number of it is believed that is sent to LED display and shows, output deposit unit is sending after data signal just to shifting deposit unit
Can the most again receive new data signal, and then at output driver element, data signal is sent to LED display and show
The data content in output deposit unit is refreshed, so that the Refresh Data rate of driving chip can be improved while showing.
Accompanying drawing explanation
The structural representation of the driving chip of the LED display that Fig. 1 provides for this utility model embodiment；
The physical circuit figure of the driving chip of the LED display that Fig. 2 provides for this utility model embodiment；
The overall schematic diagram of the driving chip of the LED display that Fig. 3 provides for this utility model embodiment；
The structured flowchart of the LED display that Fig. 4 provides for this utility model embodiment.
Detailed description of the invention
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing and enforcement
Example, is further elaborated to this utility model.Should be appreciated that specific embodiment described herein is only in order to explain this
Utility model, is not used to limit this utility model.
The purpose of this utility model embodiment is to provide a kind of chip, it is intended to solves prior art chips and does not possesses
The problem that oneself adjusts the function of work shape body.
Fig. 1 shows the structural representation of the driving chip of the LED display that the present embodiment provides.
As it is shown in figure 1, the driving chip 100 of a kind of LED display, including the data being connected with LED display 200 respectively
Outfan and multiple loops end, driving chip 100 also includes: output deposit unit 10, shifting deposit unit 20 and output are driven
Moving cell 30；
The triggering end LE of output deposit unit 10 receives and triggers signal, and the signal input part of output deposit unit 10 receives number
The number of it is believed that, the signal output part of output deposit unit 10 is connected with the signal receiving end of shifting deposit unit 20；
The signal sending end of shifting deposit unit 20 is connected with the signal input part of output driver element 30, and output drives single
Enable Pin OE of unit 30 receives and enables signal；
Output deposit unit 10 sends data signal according to triggering signal to shifting deposit unit 20, exports driver element 30
According to enable signal, the data signal in shifting deposit unit 20 is sent to LED display 200 show, exports storage receipt
Unit 10 receives new data signal after sending data signal to shifting deposit unit 20 again, with at output driver element 30
It is sent to data signal while LED display 200 shows refresh the data content in output deposit unit.
In the present embodiment, the voltage input end of output driver element 30 accesses a reference voltage REXT, provides ginseng for it
Examine or power.
As it is shown in figure 1, driving chip 100 also includes: primary shifting deposit unit 40；
First signal input part SIN of primary shifting deposit unit 40 receives data signal, primary shifting deposit unit 40
Secondary signal input CLK receive clock signal, the first signal output part of primary shifting deposit unit 40 is deposited with output
The signal input part of unit 10 is connected, and the secondary signal outfan of primary shifting deposit unit 40 is that driving chip 100 data are defeated
Going out and hold SOUT, primary shifting deposit unit 40 is sent out to the signal input part of output deposit unit 10 by its first signal output part
Send data signal.
In the present embodiment, primary shifting deposit unit 40 receives data signal by the first signal input part SIN, passes through
Secondary signal input CLK receives clock signal, the signal input part of output deposit unit 10 and primary shifting deposit unit 40
The first signal output part be connected, and receive data signal according to triggering signal and clock signal.The letter of shifting deposit unit 20
Number receiving terminal and signal sending end respectively with the signal output part of output deposit unit 10 and to export the signal of driver element 30 defeated
Entering end to be connected, after data signal is sent to shifting deposit unit 20 by output deposit unit 10, output driver element 30 is according to making
Data signal in shifting deposit unit 20 is sent to LED display and shows by energy signal.
Wherein, just by data while output deposit unit 10 receives data signal according to triggering signal and clock signal
Signal sends and gives shifting deposit unit 20, by output driver element 30 according to enabling signal by the number in shifting deposit unit 20
The number of it is believed that is sent to LED display and shows.Output deposit unit 10, can be previous in acquisition without being limited to enable signal
After the data signal in cycle, data signal is sent to shifting deposit unit 20, vacates the memory space of output deposit unit 10
Receive next data signal.I.e. data signal is sent to while LED display 200 shows at output driver element 30
Refresh the data content in output deposit unit 10, it is not necessary to clock signal is adjusted, the number of driving chip 100 can be improved
According to refresh rate.
Fig. 2 shows the physical circuit figure of the driving chip of the LED display that the present embodiment provides；As in figure 2 it is shown, output
Deposit unit 10 includes resistance R1, the first phase inverter U1 and output latch 11；
First end of resistance R1 and the input of the first phase inverter U1 are connected and form a node, and this node is that output is deposited
The triggering end LE of unit 10, the outfan of the first phase inverter U1 is connected with the triggering end of output latch 11, output latch 11
Input be output deposit unit 10 signal input part, the outfan of output latch 11 be output deposit unit 10 letter
Number outfan.
As in figure 2 it is shown, shifting deposit unit 20 includes that shift register 21, the input of shift register 21 are that displacement is posted
The signal receiving end of memory cell 20, the outfan of shift register 21 is the signal sending end of shifting deposit unit 20, and displacement is posted
The controlled end of storage 21 is connected with output driver element 30.
As in figure 2 it is shown, output driver element 30 includes resistance R2, the second phase inverter U2, output driver 31, output electric current
Actuator 32 and multiple constant-current source (V1, V2 ... Vn)；
Second end of the first termination power VDD of resistance R2, resistance R2 and the input of the second phase inverter U2 are connected, and second
The input of phase inverter U2 is the Enable Pin of output driver element 30, and the outfan of the second phase inverter U2 connects output driver 31 altogether
Trigger end and the controlled end of shift register 21, output driver 31 includes the multiple loops corresponding with multiple constant-current sources 33
End, multiple loops end that input is driving chip 100 of multiple constant-current sources (V1, V2 ... Vn), multiple constant-current sources (V1,
V2 ... Vn) outfan be connected with multiple loops end one_to_one corresponding of driver 31, it is achieved driving chip 100 and LED show
Loop is formed between screen 200.
As in figure 2 it is shown, primary shifting deposit unit 40 includes: the first trigger M1, the second trigger M2, primary depositor
41 and output state M3；
The input of the first trigger M1 is the first signal input part SIN of primary shifting deposit unit 40, and first triggers
The data input pin of the primary depositor 41 of output termination of device M1, the input of the second trigger M2 is primary shifting deposit unit
The secondary signal input of 40, the clock signal input terminal of the primary depositor 41 of output termination of the second trigger M2, primary is posted
First outfan of storage 41 is the first signal output part of primary shifting deposit unit 40, the second output of primary depositor 41
First end of termination output buffer M3, second end of output buffer M3 is driving chip 100 data output end.
It is all Schmidt trigger as an embodiment of the present utility model, the first trigger M1 and the second trigger M2.
As an embodiment of the present utility model, primary depositor 41 be sixteen bit register, 32 bit registers or
64 bit registers.
As an embodiment of the present utility model, shift register 21 be sixteen bit register, 32 bit registers or
64 bit registers.
As an embodiment of the present utility model, output latch 11 be sixteen bit register, 32 bit registers or
64 bit registers.
Fig. 3 shows the overall schematic diagram of the driving chip of the LED display that the present embodiment provides, below in conjunction with Fig. 3 pair
The operation principle of the driving chip of the LED display that the present embodiment provides is described:
As it is shown on figure 3, order the most from left to right, it is followed successively by output rheonome, multiple constant-current source, output
Driver, shift register, output latch and primary depositor.Drive as it is shown on figure 3, shift register is connected to output
Between device and output latch.After data signal is by SIN end input to primary depositor, defeated according to LE end by output latch
The triggering signal (or latch signal) entered is read out.Shift register is according to the enable signal pair being energy signal end OE non-input
Data signal latches, then is exported by output driver.Transmit to output driver by shift register in data signal
Output latch can update simultaneously simultaneously, and the data of quickening update, and makes full use of data bandwidth, improves the refreshing that LED shows
Rate.
Fig. 4 shows the structured flowchart of the LED display that the present embodiment provides.As shown in Figure 4, of the present utility model separately
One purpose is to provide a kind of LED display, and including LED display 200, this LED display also includes above-described embodiment
In the driving chip 100 of LED display.
The improvement relevant to this utility model content due to the present embodiment and implementation in the above-described embodiments and
Describe in detail, therefore here is omitted.
This utility model provides driving chip and LED display, the driving of this LED display of a kind of LED display
Including the data output end being connected with LED display respectively and multiple loops end, driving chip also includes: output deposit unit,
Shifting deposit unit and output driver element；The triggering end of output deposit unit receives and triggers signal；Shifting deposit unit
Signal sending end is connected with the signal input part of output driver element, and the Enable Pin of output driver element receives and enables signal；Defeated
Going out deposit unit and send data signal according to triggering signal to shifting deposit unit, output driver element is according to enabling signal by number
The number of it is believed that is sent to LED display and shows, output deposit unit is sending after data signal just to shifting deposit unit
Can the most again receive the number of it is believed that number is new, and then at output driver element, data signal is sent to LED display and show
The data content in output deposit unit is refreshed, so that the Refresh Data rate of driving chip can be improved while showing.
The foregoing is only preferred embodiment of the present utility model, not in order to limit this utility model, all at this
Any amendment, equivalent and the improvement etc. made within the spirit of utility model and principle, should be included in this utility model
Protection domain within.
Claims (10)
1. a driving chip for LED display, including the data output end being connected with LED display respectively and multiple loops
End, it is characterised in that described driving chip also includes: output deposit unit, shifting deposit unit and output driver element；
The triggering end of described output deposit unit receives and triggers signal, and the signal input part of described output deposit unit receives data
Signal, the signal output part of described output deposit unit is connected with the signal receiving end of described shifting deposit unit；
The signal sending end of described shifting deposit unit is connected with the signal input part of described output driver element, and described output is driven
The Enable Pin of moving cell receives and enables signal；
Described output deposit unit sends described data signal according to described triggering signal to described shifting deposit unit, described defeated
Go out driver element according to described enable signal, the described data signal in described shifting deposit unit to be sent to described LED and show
Screen shows, described output deposit unit receives new after sending described data signal to described shifting deposit unit again
Data signal, same with at described output driver element described data signal is sent to that described LED display carries out showing
Time refresh the data content in described output deposit unit.
2. the driving chip of LED display as claimed in claim 1, it is characterised in that described driving chip also includes: primary
Shifting deposit unit；
First signal input part of described primary shifting deposit unit receives data signal, the of described primary shifting deposit unit
Binary signal input receives clock signal, the first signal output part of described primary shifting deposit unit and described output storage receipt
The signal input part of unit is connected, and the secondary signal outfan of described primary shifting deposit unit is driving chip data output end,
Described primary shifting deposit unit sends institute by its first signal output part to the signal input part of described output deposit unit
State data signal.
3. the driving chip of LED display as claimed in claim 1, it is characterised in that described output deposit unit includes electricity
Resistance R1, the first phase inverter and output latch；
First end of described resistance R1 is connected with the input of described first phase inverter and forms a node, and this node is described defeated
Going out the triggering end of deposit unit, the outfan of described first phase inverter is connected with the triggering end of described output latch, described defeated
Going out the signal input part that input is described output deposit unit of latch, the outfan of described output latch is described defeated
Go out the signal output part of deposit unit.
4. the driving chip of LED display as claimed in claim 1, it is characterised in that described shifting deposit unit includes moving
Bit register, the input of described shift register is the signal receiving end of described shifting deposit unit, described shift register
The signal sending end that outfan is described shifting deposit unit, the controlled end of described shift register drives single with described output
Unit is connected.
5. the driving chip of LED display as claimed in claim 4, it is characterised in that described output driver element includes electricity
Resistance R2, the second phase inverter, output driver, output rheonome and multiple constant-current source；
First termination power of described resistance R2, second end of described resistance R2 is connected with the input of described second phase inverter,
The input of described second phase inverter is the Enable Pin of described output driver element, and the outfan of described second phase inverter meets institute altogether
That states output driver triggers end and the controlled end of described shift register, and described output driver includes and the plurality of constant current
Multiple loops end that source is corresponding, the input of the plurality of constant-current source is multiple loops end of described driving chip, the plurality of
The outfan of constant-current source is connected with multiple loops end one_to_one corresponding of described driver, it is achieved described driving chip and described LED
Loop is formed between display screen.
6. the driving chip of LED display as claimed in claim 2, it is characterised in that described primary shifting deposit unit bag
Include: the first trigger, the second trigger, primary depositor and output state；
The input of described first trigger is the first signal input part of described primary shifting deposit unit, and described first triggers
The data input pin of the described primary depositor of output termination of device, the input of described second trigger is that described primary displacement is posted
The secondary signal input of memory cell, the clock signal input of the described primary depositor of output termination of described second trigger
End, the first outfan of described primary depositor is the first signal output part of described primary shifting deposit unit, described primary
Second output of depositor terminates the first end of described output buffer, and the second end of described output buffer is described driving core
Sheet data output end.
7. the driving chip of LED display as claimed in claim 6, it is characterised in that described first trigger and described the
Two triggers are respectively Schmidt trigger, and described primary depositor is sixteen bit register, 32 bit registers or 60
Four bit registers.
8. the driving chip of LED display as claimed in claim 3, it is characterised in that described shift register is sixteen bit
Depositor, 32 bit registers or 64 bit registers.
9. the driving chip of LED display as claimed in claim 4, it is characterised in that described output latch is sixteen bit
Depositor, 32 bit registers or 64 bit registers.
10. a LED display, including LED display, it is characterised in that described LED display also includes that right such as is wanted
Seek the driving chip of LED display described in 1-9 any one.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620680699.5U CN205881419U (en) | 2016-06-30 | 2016-06-30 | Driver chip and LED display device of LED display screen |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620680699.5U CN205881419U (en) | 2016-06-30 | 2016-06-30 | Driver chip and LED display device of LED display screen |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601190A (en) * | 2017-03-06 | 2017-04-26 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, gate drive circuit and display device |
| CN107358912A (en) * | 2017-08-18 | 2017-11-17 | 深圳市德普微电子有限公司 | A kind of single dual-colored LED display screen drive chip |
| CN110070827A (en) * | 2019-05-22 | 2019-07-30 | 深圳市富满电子集团股份有限公司 | LED display driver IC, latch signal generation method and system |
| CN114283741A (en) * | 2021-12-28 | 2022-04-05 | 富满微电子集团股份有限公司 | System-cascaded cross-stage LED driving data transmission circuit |
| CN116403517A (en) * | 2023-06-09 | 2023-07-07 | 中科(深圳)无线半导体有限公司 | Self-adaptive control method for power source of LED display system |
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2016
- 2016-06-30 CN CN201620680699.5U patent/CN205881419U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601190A (en) * | 2017-03-06 | 2017-04-26 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, gate drive circuit and display device |
| CN107358912A (en) * | 2017-08-18 | 2017-11-17 | 深圳市德普微电子有限公司 | A kind of single dual-colored LED display screen drive chip |
| CN110070827A (en) * | 2019-05-22 | 2019-07-30 | 深圳市富满电子集团股份有限公司 | LED display driver IC, latch signal generation method and system |
| CN110070827B (en) * | 2019-05-22 | 2023-05-23 | 富满微电子集团股份有限公司 | LED display screen driving chip, latch signal generation method and system |
| CN114283741A (en) * | 2021-12-28 | 2022-04-05 | 富满微电子集团股份有限公司 | System-cascaded cross-stage LED driving data transmission circuit |
| CN116403517A (en) * | 2023-06-09 | 2023-07-07 | 中科(深圳)无线半导体有限公司 | Self-adaptive control method for power source of LED display system |
| CN116403517B (en) * | 2023-06-09 | 2023-08-29 | 中科(深圳)无线半导体有限公司 | Self-adaptive control method for power source of LED display system |
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Address after: 518000 1701, building 1, Shenzhen new generation industrial park, 136 Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen City, Guangdong Province Patentee after: Fuman microelectronics Group Co.,Ltd. Address before: Unit b7-b8, 9 / F, Yanxiang science and technology building, 31 Gaoxin Zhongsi Road, Nanshan District, Shenzhen, Guangdong 518000 Patentee before: SHENZHEN FUMAN ELECTRONIC GROUP Co.,Ltd. |
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