CN111340835A - FPGA-based video image edge detection system - Google Patents

Abstract

The embodiment of the invention discloses a video image edge detection system based on FPGA, comprising a video acquisition module, a video detection module and a video processing module, wherein the video acquisition module is used for acquiring a video image; the image type conversion module is used for converting the video image from a Bayer pattern to an RGB pattern; the device comprises a synchronous dynamic random access memory, a first read-out port, a second read-out port, a first write-in port and a second write-in port, wherein the synchronous dynamic random access memory is used for caching RGB mode images, the first write-in port is used for writing in all 10 bits of B signals and all 5 bits of G in a pixel point, and the second write-in port is used for writing in all 10 bits of R signals and all 5 bits of G in the pixel point; the FPGA is used for controlling the reading of the synchronous dynamic random access memory and carrying out edge detection on a video image; and for converting the RGB image into a grayscale image; performing median filtering on the gray level image; and (4) carrying out edge detection on the image after median filtering by using a Sobel operator.

Description

FPGA-based video image edge detection system

Technical Field

The invention relates to the technical field of image processing, in particular to a video image edge detection system based on an FPGA (field programmable gate array).

Background

Edge detection is a fundamental problem in image processing and computer vision, and the purpose of edge detection is to identify points in a digital image where brightness changes are significant. Significant changes in image attributes typically reflect significant events and changes in the attributes.

The edge detection of the image has a long research history, the existing edge detection methods are various, but all the methods have defects, the optimal edge of a target object cannot be detected under certain specific conditions, and no commonly-applied edge detection method exists so far.

The edge detection is used as the basis of image processing, and the effect and the operation time of the edge detection directly influence the quality and the duration of subsequent image processing. Currently, edge detection is usually implemented in a software manner. However, the software method consumes a large amount of computing resources, such as hardware resources like memory, CPU, and graphics card. Resulting in a slow overall image processing process, especially if large amounts of image data are processed.

Disclosure of Invention

The embodiment of the invention provides a video image edge detection system based on an FPGA (field programmable gate array), which aims to solve the technical problems.

In a first aspect, an embodiment of the present invention provides a video image edge detection system based on an FPGA, including:

the video acquisition module is used for acquiring video images;

the image type conversion module is used for converting the video image from a Bayer pattern to an RGB pattern;

a synchronous dynamic random access memory for caching RGB mode images, the synchronous dynamic random access memory comprising: the read-in port comprises a first read-out port, a second read-out port, a first write-in port and a second write-in port, wherein the first write-in port is used for writing all 10 bits of B signals and all 5 bits of G in a pixel point, and the second write-in port is used for writing all 10 bits of R signals and all 5 bits of G in the pixel point;

the FPGA is used for controlling the reading of the synchronous dynamic random access memory and carrying out edge detection on a video image;

the FPGA comprises: the image processing module is used for converting the RGB image into a gray image;

the median filtering module is used for performing median filtering on the gray level image;

and the edge detection module is used for carrying out edge detection on the image after the median filtering by utilizing a Sobel operator.

Further, the FPGA is configured to control reading of the synchronous dynamic random access memory, and includes:

the FPGA comprises: and the second write-in port is used for writing all 10 bits of R signals and high 5 bits of G signals in the pixel points as input signals of the write FIFO, and automatically generating read-write requests for the SDRAM according to the state of the cache FIFO.

Further, the image processing module is configured to:

carrying out equal-proportion amplification on the gray value calculation formula to obtain an amplification result;

and obtaining a gray level image by using the amplification result through shift transformation.

Further, the median filtering module is configured to:

setting a filtering window;

for window data, first sort each column in ascending order, then sort each row in ascending order, and then take the median of the diagonal pixels as the filtering result.

Further, the filtering window is a 3 × 3 window.

Further, the IP core of the shift register is called to generate filtering window data.

Further, the edge detection module is configured to:

setting a horizontal convolution kernel template and a vertical convolution kernel template;

obtaining a pixel point gradient value template value, and calculating an extreme value according to the horizontal convolution kernel template, the vertical convolution kernel template and the pixel point gradient value template value;

and determining whether the edge is the edge according to the comparison result of the extreme value and a preset threshold value.

Further, the obtaining of the gradient template value of the pixel point includes:

3 Line buffers are achieved by using altshift _ tab of Megafunction, input image data is processed by dividing into 3 lines, each Line receives the image data 3 clock pulses later than the previous Line, namely the image data is received at the time of three pixel points, and therefore the data of 9 adjacent pixel points are intercepted at three lines at the same time point.

Further, the FPGA further includes:

and the corrosion module is used for carrying out corrosion treatment on the image.

Further, the FPGA further comprises:

and the expansion module is used for performing expansion processing on the image.

According to the FPGA-based video image edge detection system provided by the embodiment of the invention, through the video acquisition module, the video acquisition module is used for acquiring a video image; the image type conversion module is used for converting the video image from a Bayer pattern to an RGB pattern; a sdram for caching RGB mode images, the sdram comprising: the read-in circuit comprises a first read-out port, a second read-out port, a first write-in port and a second write-in port, wherein the first write-in port is used for writing all 10 bits of B signals and all 5 bits of G in a pixel point, and the second write-in port is used for writing all 10 bits of R signals and all 5 bits of G in the pixel point; the FPGA is used for controlling the reading of the synchronous dynamic random access memory and carrying out edge detection on a video image; the FPGA comprises: the image processing module is used for converting the RGB image into a gray image; the median filtering module is used for performing median filtering on the gray level image; and the edge detection module is used for carrying out edge detection on the image after the median filtering by utilizing a Sobel operator. The image edge detection can be completed by utilizing the operation function of the FPGA and carrying out corresponding configuration on hardware matched with the FPGA and utilizing a simple instruction. The method can effectively improve the accuracy of image edge detection, reduce the processing time, reduce the consumption of operation resources, and is particularly suitable for processing a large number of images.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

fig. 1 is a flow chart of an FPGA-based video image edge detection system according to an embodiment of the present invention;

fig. 2 is a timing diagram of output data and control signals in the FPGA-based video image edge detection system according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a median filtering module in the FPGA-based video image edge detection system according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of altshift _ taps in the FPGA-based video image edge detection system according to the embodiment of the present invention;

fig. 5 is a structural diagram of Sobel algorithm operation in the FPGA-based video image edge detection system according to the embodiment of the present invention;

fig. 6 is a hardware structure diagram of an expansion module in the FPGA-based video image edge detection system according to an embodiment of the present invention;

fig. 7 is a hardware structure diagram of a corrosion module in the FPGA-based video image edge detection system according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It is to be further noted that, for the convenience of description, only a part of the structure relating to the present invention is shown in the drawings, not the whole structure.

Fig. 1 is a video image edge detection system based on FPGA provided in the embodiment of the present invention, including: the video acquisition module is used for acquiring video images; the image type conversion module is used for converting the video image from a Bayer pattern to an RGB pattern; a synchronous dynamic random access memory for caching RGB mode images, the synchronous dynamic random access memory comprising: the read-in port comprises a first read-out port, a second read-out port, a first write-in port and a second write-in port, wherein the first write-in port is used for writing all 10 bits of B signals and all 5 bits of G in a pixel point, and the second write-in port is used for writing all 10 bits of R signals and all 5 bits of G in the pixel point; the FPGA is used for controlling the reading of the synchronous dynamic random access memory and carrying out edge detection on a video image; the FPGA comprises: the image processing module is used for converting the RGB image into a gray image; the median filtering module is used for performing median filtering on the gray level image; and the edge detection module is used for carrying out edge detection on the image after the median filtering by utilizing a Sobel operator.

In this embodiment, video information is collected by a CMOS camera and enters the FPGA to perform the motion target detection. After the system is powered on, the FPGA configures a CMOS sensor chip through a data bus, and the CMOS sensor enters acquired data into the FPGA after the configuration is completed. Optionally, a TRDB-DC2 CMOS camera of Youking science and technology company is adopted, and the video acquisition module mainly has I²And the C configuration module and the CMOS module are composed of two sub-modules.

In I²After the C bus start signal, the first byte of data is sent to select the slave address, where the first 7 bits are the address code and the 8 th bit is the direction (R/W).

A direction bit of "0" indicates transmission, i.e., the master device writes information to the selected slave device; a direction bit of "1" indicates that the master reads the slave data. After the start signal, each device in the system compares its own address with the address transmitted by the master device to the bus, if the address is consistent with the address transmitted by the master device to the bus, the device is the device to be addressed by the master device, and whether the device receives or transmits data is determined by the 8 th bit direction bit (R/W). In I²Each time transmission on C busThe data bytes sent are not limited, but each byte must be 8 bits, and each transmitted byte must be followed by an acknowledge bit (9 th bit), also called an acknowledge bit (ACK), which is a reply signal to the data sender whether the data receiver has received a byte of data correctly or not. When the master device finishes sending a byte of data, a clock response bit on the corresponding SCL line is sent out, the master device releases the SDA line in the clock, one byte of data is transmitted, the response signal of the slave device pulls the SDA line to be low level, the SDA is enabled to be stable low level in the high level period of the clock, and after the response signal of the slave device is finished, the SDA line returns to be high level and enters the next transmission period. I is²C control Module, I2C _ DATA [23: 0)]Configuring data for CMOS cameras I²The C control module sets I2C _ DATA [23: 0)]Is converted to conform to I²Control signals SCLK, SDAT of the C bus protocol. GO and END are handshake signals to indicate the start and END of transmission.

The CMOS module detects a line-field synchronizing signal of the CMOS camera, determines a frame header of an image, counts a pixel clock, and collects effective data of the camera into the FPGA. Fig. 2 is a timing diagram of output data and control signals in the video image edge detection system of the FPGA according to an embodiment of the present invention.

In fig. 2, PIXCLK is a pixel clock signal, and is synchronized with the active pixels, the rising edge data is active, and the falling edge data is updated; DOUT 9-DOUT 0 are 10bit data outputs. FRAME _ VALID is a FRAME VALID signal, and a high level period represents one FRAME of VALID image data; LINE _ VALID is a LINE VALID signal, and a high period indicates that one LINE of data is VALID. P denotes frame start/end blanking for 6 pixel clocks, a denotes valid data time of 1280 pixel clocks, Q denotes horizontal blanking for 396 pixel clocks. Therefore, according to the timing analysis of the output signal control, the specific operation flow of the CMOS module is: detecting the rising edge of FRAME _ VALID, judging the start of a FRAME image, clearing the LINE count, and under the condition that LINE _ VALID is VALID, starting the counting of a pixel clock by a column counter, recording 1280 as data of one LINE, recording the LINE count of 0, and adding 1 to the LINE count. The image data is driven into the registers of the CMOS module at the rising edge of the pixel clock as input to the next module. The output data valid signal is the result of the AND of the frame valid signal and the row valid signal as the write enable signal of the memory, and the row and column count signal as the output signal

Since the image sensor outputs pixel data in a Bayer pattern and the display displays RGB, the image format needs to be converted to see the correct captured image. The conversion method is to calculate the RGB value of one point by taking four points as the neighborhood, the R value is the red value, the average value of two G values is the green value, B is the blue value, and so on, and the RGB value of each point can be obtained by calculating three points around each point.

When the RGB extraction module is designed, a shift register IP core provided by QuartusII needs to be called, the data width is 10 bits, and the length setting is larger than 1280. The data input and the clock enable signal are provided by the CMOS module, two data with the interval of 1280 are taken as output, two rows of data in the same column can be simultaneously extracted, the two data are cached in the register, a four-point neighborhood is formed by the two data to be cached, whether the row and the column of a point represented by the neighborhood are odd numbers or even numbers is judged according to the lowest bit of the row-column counting provided by the CMOS module, and the R, G, B value of the point is calculated according to different points and different values.

Because the cached image needs to be read for edge detection, the embodiment uses SDRAM to cache the image.

The RGB formats of videos shot by the CMOS sensor after format conversion are respectively 10 bits, and 30 bits exist for 1 pixel, so that 4 FIFO buffers are opened up by utilizing on-chip resources of the FPGA, and the data port of the SDRAM is designed to be 4 ports which are 2Read and 2Write, so that one SDRAM can be used as two SDRAMs to buffer two frames of images.

The RGB extraction module outputs 30 bits of signals, and the SDRAM data width is 16 bits, so 2 banks are needed to store 1 pixel, and 2Write ports are needed to Write images in 2 times: the Write1 writes the full 10 bits of the B signal and the lower 5 bits of G, and the Write2 writes the full 10 bits of the R signal and the upper 5 bits of G as input signals to the Write FIFO. The controller sends out read-write requests to the SDRAM according to the state of the buffer FIFO, and the timing sequence requirements are matched in a page mode burst transmission mode and a BANK switching mode.

Pins of SDRAM devices are classified into three categories, control signals, addresses, and data. An SDRAM contains several BNAKs, and the memory cells of each BANK are addressed by row and column.

The SDRAM can automatically generate read-write requests and data buffering processing for the SDRAM according to the state of the buffer FIFO. The data obtained by the RGB extraction module is cached in the write cache FIFO, and as long as the data in the write cache reaches the data size of each page of the SDRAM, a write request to the SDRAM is generated, and the data can be stored continuously at the moment because the size of each cache is two pages of the SDRAM. Similarly, the data of the VGA display module is obtained from the read buffer FIFO, and as long as the data in the read buffer is smaller than the data of each page of the SDRAM, a read request to the SDRAM is generated, so that two pages in each buffer operate in a round-robin manner.

Before the image processing algorithm is performed, a gray scale image must be generated, and the image format in the data buffer is the color RGB format, so the RGB format image must be converted into a gray scale image. The RGB to grayscale image formula is generally:

Gray＝0.299*R+0.587*G+0.114*B

the above conversion formula involves floating point operations. In the FPGA implementation process, the method can be implemented by adopting a shift conversion mode, firstly, a gray conversion result amplified by 1000 times is obtained by calculation according to a formula (3.2), and then, a final gray conversion result is obtained by shifting 10 bits to the left according to the formula.

Gray_temp＝299*R+587*G+114*B

Gray＝(Gray_temp>>10)

In the embodiment, the preliminary processing of the image by using filtering is needed, an exemplary adopted fast median filtering algorithm is a 3 × 3 window, and the basic idea is that for the 3 × 3 window data, each column is sorted in ascending order, each row is sorted in ascending order, and then the median value of pixels on the diagonal line is taken as the filtering result, fig. 3 is a schematic diagram of a median filtering Module in the FPGA-based video image edge detection system provided by the embodiment of the invention, and fig. 3 shows that W11-W33 are window data and Sort three-point Module in the diagram, and after the delay of three clock cycles, the sorting of three pixels is completed in each clock cycle thereafter, and the whole circuit can work at a higher clock frequency.

3 × 3 filtering window data generation, calling shift register IP core altshift _ taps provided by quartus ii to implement fig. 4 is a schematic structural diagram of altshift _ taps in the FPGA-based video image edge detection system according to the embodiment of the present invention.

And 3-line parallel output is carried out on the single-row serial image, when altshift _ taps is LineBuffer _3, parameters are set to be 3 taps for output, the interval width between taps is 640(VGA display pixels are 640 x 480), and the data width is 8 bits (gray scale image).

In the aspect of algorithm complexity, the rapid median filtering algorithm needs 3 times for each column sorting, 3 times for each row sorting, 3 times for 3 rows and 3 columns sorting being 3 × 3 × 2-18 times, and 3 times for finally solving the median of the diagonal elements of the window, so that the total needed sorting times are 21 times.

In this embodiment, in consideration of the fact that the Sobel operator has better edge detection performance than Roberts and Prewitt operators, and has lower computational complexity compared with Laplace, LOG and Canny operators, and is easy to implement in hardware and meet the real-time requirement, the Sobel operator is selected for edge detection on the acquired image in the horizontal and vertical directions.

The edge detection operator actually detects edges by utilizing the mutation property of the edges of the images, the gradients of pixel points on two sides of the edges have large differences, the Sobel operator provides a 3 × 3 template in the horizontal direction and the vertical direction as a core to be convolved with each pixel point on the images and calculate to obtain a gradient value, and then the edges can be judged by selecting a threshold according to the actual environment.

Firstly, defining three templates of a horizontal convolution kernel template, a vertical convolution kernel template and an operation template which participate in operation by using a hardware language. Since the two convolution kernel templates of the Sobel operator are given numerical values, it can be directly defined as a constant type of data:

//mask x

parameter X1＝8'hff,X2＝8'h00,X3＝8'h01；

parameter X4＝8'hfe,X5＝8'h00,X6＝8'h02；

parameter X7＝8'hff,X8＝8'h00,X9＝8'h01；

//mask y

parameter Y1＝8'h01,Y2＝8'h02,Y3＝8'h01；

parameter Y4＝8'h00,Y5＝8'h00,Y6＝8'h00；

parameter Y7＝8'hff,Y8＝8'hfe,Y9＝8'hff；

since X1 is-1, it is represented by the complement of 2, and the rest negative numbers are the same.

The pixel gradient value template is somewhat complex, although only the pixel itself, i.e., P5 in fig. 5, is operated, the data of the adjacent pixels P1, P2, P3, P4, P6, P7, P8, and P9 must be known at the same time, and the data must be sequentially transmitted, which is not a problem because the data are all in groups, only the directory of the groups needs to be changed, but the data cannot be obtained in Verilog, and therefore a special hardware structure needs to be designed for implementation.

The special design is to use the altshift _ tab of Megafunction to achieve 3 Line buffers, the principle is that only 9 pixel points are assumed in one frame of image, operation is carried out by matching with Sx, input image data is processed by 3 lines, each Line receives image data 3 clock pulses later than the previous Line, namely the time of three pixel points, and the data of the adjacent 9 pixel points can be intercepted in three lines at the same time point.

After the last pixel point 9 is input, the next clock pulse obtains pixel points 1, 4 and 7, the next clock pulse is 2, 5 and 8, the last clock pulse is 9, 6 and 3, namely Line0 obtains 9, 8 and 7 in turn, Line1 obtains 6, 5 and 4, Line3 obtains 3, 2 and 1, and the expected effect is achieved through verification.

Then, according to a Sobel algorithm, the pixel points respectively operate with Sx and Sy:

Sx＝X1*P1+X2*P2+X3*P3+X4*P4+X5*P5+X6*P6+X7 *P7+X8*P8+X9*P9。

line0 must be multiplied and added with X9, X8 and X7, the multiplication is realized by using a 3-input multiplication and addition IP core MAC _3, and the rest of X1 and X2 are the same as y0, y1 and y 2. And finally, adding the multiplication and addition results of the 3 rows by using a 3-input parallel accumulation module to obtain Sx and Sy. The final hardware implementation structure is shown in fig. 5, and fig. 5 is a structural diagram of Sobel algorithm operation in the FPGA-based video image edge detection system according to the embodiment of the present invention.

And finally, according to a Sobel algorithm, adding Sx and Sy squares and then opening a root number, and calling an opening operation IP core ALTSSQRT by the opening operation to realize:

after the result is obtained, a threshold value ithreshold is set for comparison and determination, and it is necessary to set an appropriate threshold value in advance according to the intensity of light irradiation.

In the embodiment, a video acquisition module is used for acquiring video images; the image type conversion module is used for converting the video image from a Bayer pattern to an RGB pattern; a synchronous dynamic random access memory for caching RGB mode images, the synchronous dynamic random access memory comprising: the read-in port comprises a first read-out port, a second read-out port, a first write-in port and a second write-in port, wherein the first write-in port is used for writing all 10 bits of B signals and all 5 bits of G in a pixel point, and the second write-in port is used for writing all 10 bits of R signals and all 5 bits of G in the pixel point; the FPGA is used for controlling the reading of the synchronous dynamic random access memory and carrying out edge detection on a video image; the FPGA comprises: the image processing module is used for converting the RGB image into a gray image; the median filtering module is used for performing median filtering on the gray level image; and the edge detection module is used for carrying out edge detection on the image after the median filtering by utilizing a Sobel operator. The image edge detection can be completed by utilizing the operation function of the FPGA and carrying out corresponding configuration on hardware matched with the FPGA and utilizing a simple instruction. The method can effectively improve the precision of image edge detection, reduce the processing time, reduce the consumption of operation resources, and is particularly suitable for processing a large number of images.

In a preferred implementation of this embodiment, the FPGA further includes: and the expansion module is used for performing expansion processing on the image. The image subjected to edge detection has a plurality of fine discrete black points, and the discrete black points need to be removed through morphological open operation to obtain a better display effect. The open operation is realized by firstly corroding and then expanding, and the close operation is realized by firstly expanding and then corroding, so that the open operation and the close operation can be divided into two sub-modules, namely a corrosion module and an expansion module. According to the definition of the expansion, for the sets A and B in Z, the process of expanding B to A is as follows:

(1) scanning each pixel of image a with structuring element B;

(2) carrying out OR operation on the structural elements and the binary image covered by the structural elements;

(3) if both are 0, the pixel of the resulting image is 0, otherwise it is 1.

The structural elements used in this embodiment are flat structural elements (all 1) of 3 × 3, and the hardware implementation structure of the expansion module is shown in fig. 6.

Accordingly, according to the definition of corrosion, for the sets A and B in Z, the process of corrosion of B on A is as follows: (1) scanning each pixel of image a with structuring element B; (2) carrying out AND operation on the structural elements and the binary image covered by the structural elements; (3) if both are 1, the pixel of the resulting image is 1, otherwise it is 0.

The hardware implementation module of the corrosion operation is shown in fig. 7, and the image can be quickly and accurately corroded by the structure.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions without departing from the scope of the invention. Therefore, although the present invention has been described in more detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. An FPGA-based video image edge detection system, comprising:

the video acquisition module is used for acquiring video images;

the image type conversion module is used for converting the video image from a Bayer pattern to an RGB pattern;

a synchronous dynamic random access memory for caching RGB mode images, the synchronous dynamic random access memory comprising: the read-in port comprises a first read-out port, a second read-out port, a first write-in port and a second write-in port, wherein the first write-in port is used for writing all 10 bits of B signals and all 5 bits of G in a pixel point, and the second write-in port is used for writing all 10 bits of R signals and all 5 bits of G in the pixel point;

the FPGA is used for controlling the reading of the synchronous dynamic random access memory and carrying out edge detection on a video image;

the FPGA comprises: the image processing module is used for converting the RGB image into a gray image;

the median filtering module is used for performing median filtering on the gray level image;

and the edge detection module is used for carrying out edge detection on the image after the median filtering by utilizing a Sobel operator.

2. The system of claim 1, wherein the FPGA configured to control the sdram read comprises:

the FPGA comprises: and the second write-in port is used for writing all 10 bits of R signals and high 5 bits of G signals in the pixel points as input signals of the write FIFO, and automatically generating read-write requests for the SDRAM according to the state of the cache FIFO.

3. The system of claim 1, wherein the image processing module is configured to:

carrying out equal-proportion amplification on the gray value calculation formula to obtain an amplification result;

and obtaining a gray level image by using the amplification result through shift transformation.

4. The system of claim 1, wherein the median filtering module is configured to:

setting a filtering window;

for window data, first sort each column in ascending order, then sort each row in ascending order, and then take the median of the diagonal pixels as the filtering result.

5. The system of claim 4, wherein the filter window is a 3 × 3 window.

6. The system of claim 4, wherein invoking the shift register IP core generates filter window data.

7. The system of claim 1, wherein the edge detection module is configured to:

setting a horizontal convolution kernel template and a vertical convolution kernel template;

obtaining a pixel gradient value template value, and calculating an extreme value according to the horizontal convolution kernel template, the vertical convolution kernel template and the pixel gradient value template value;

and determining whether the edge is the edge according to the comparison result of the extreme value and a preset threshold value.

8. The system of claim 7, wherein said obtaining gradient value template values for pixel points comprises:

3 Line buffers are achieved by using altshift _ tab of Megafunction, input image data is processed by dividing into 3 lines, each Line receives the image data 3 clock pulses later than the previous Line, namely the time of three pixel points, so that the data of 9 adjacent pixel points are intercepted in three lines at the same time point.

9. The system of claim 1, wherein the FPGA further comprises:

and the expansion module is used for performing expansion processing on the image.

10. The system of claim 1, wherein the FPGA further comprises:

and the corrosion module is used for carrying out corrosion treatment on the image.

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