CN107516296A - A kind of moving object detection tracking system and method based on FPGA - Google Patents

A kind of moving object detection tracking system and method based on FPGA Download PDF

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CN107516296A
CN107516296A CN201710554813.9A CN201710554813A CN107516296A CN 107516296 A CN107516296 A CN 107516296A CN 201710554813 A CN201710554813 A CN 201710554813A CN 107516296 A CN107516296 A CN 107516296A
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data
module
ddr3
image
rgb
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李彬华
陶勇
毛栊哗
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Kunming University of Science and Technology
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Kunming University of Science and Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T5/00—Image enhancement or restoration
    • G06T5/20—Image enhancement or restoration by the use of local operators
    • G06T5/30—Erosion or dilatation, e.g. thinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G06T5/70—
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T7/00—Image analysis
    • G06T7/20—Analysis of motion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/20—Special algorithmic details
    • G06T2207/20024—Filtering details
    • G06T2207/20032—Median filtering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/20—Special algorithmic details
    • G06T2207/20036—Morphological image processing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2207/00—Indexing scheme for image analysis or image enhancement
    • G06T2207/30—Subject of image; Context of image processing
    • G06T2207/30232—Surveillance

Abstract

The present invention relates to a kind of moving object detection tracking system and method based on FPGA, belong to technical field of image processing.Present invention view data first carries out data conversion and then divides two-way to export；Enter outside DDR3 memory modules by data input DDR3 fifo modules all the way to be cached, another way is cached after RGB turns gray proces, median filter process into DDR3 memory modules；The two frame greyscale image datas continuously exported from DDR3 buffers obtain the coordinate value of Motion mask after carrying out inter-frame difference computing, binary conversion treatment, corrosion expansion process, feed back to again on rgb format coloured image to obtain templates of moving objects, it is deposited into the storage of FPGA ram in slice, finally using its template matches of taking exercises, to realize the tracking of color motion target.The present invention has reached balance well in target identification speed, accuracy, cost, power consumption etc..

Description

A kind of moving object detection tracking system and method based on FPGA
Technical field
The present invention relates to a kind of moving object detection tracking system and method based on FPGA, belongs to image processing techniques neck Domain.
Background technology
Vision is that people recognize the most important means in the world, machine vision and the key technology that perception is automatic field, Computer Vision is then the basis of visually-perceptible, and as the hot issue of research and application and development and among these with motion Target detection and the focus being tracked as in focus.
Video Supervision Technique rises and late 1970s, from the information of the simple displaying scene of beginning, reduces people's Workload, to the detecting and tracking for the mobile target that gradually begins one's study, there is provided more information.At present, video object detection and with Track has widely been used in the various aspects of people's life, such as traffic, national defence, Aero-Space etc..
At present, the research and realization of the detecting and tracking algorithm of moving target, usually used is computer platform.Although meter Advanced language programming can be used by calculating machine platform, but computer platform has that volume is big, power consumption is high, processing speed is slow, poor real The shortcomings of, these all constrain the further development of research.
With the development of modern microelectronic technology, field programmable gate array（That is FPGA）Device arises at the historic moment, and makes in the past The digital display circuit of bulky complex is minimized, and makes it possible on-chip system.Substantial amounts of can configure is provided with inside FPGA to patrol Volume resource, PLL resources, RAM resources, DSP operation unit etc. on piece.And there is parallel hardware configuration and pipeline processes side Formula, the calculating speed on software can be broken through, realize the hardware-accelerated of algorithm.So FPGA to be used for the detection of moving target Tracking is possible, and real time implementation, miniaturization or miniaturization for such vision processing system have great importance and practicality Value.
The content of the invention
The technical problem to be solved in the present invention is：The present invention provides a kind of moving object detection tracking system based on FPGA And method, to solve, the detecting and tracking system and method speed of service of the existing moving target based on computer platform is slow, volume Greatly, the problem of power consumption is high, and the detecting and tracking system and method for the existing moving target based on ARM platforms slow-footed are asked Topic, improve the accuracy rate of moving object detection；Realize moving object detection in the flat of speed, device volume and power consumption etc. Weighing apparatus.
The technical scheme is that：A kind of moving object detection tracking system and method based on FPGA, including CMOS take the photograph As head module, data conversion module, RGB, to turn gray scale module, medium filtering module, data input DDR3 fifo modules, data defeated Go out DDR3 fifo modules, inter-frame difference and binarization block, corrosion expansion module, Motion mask extraction module, Motion mask With module, VGA displays driving and serially printing module, DDR3 Read-write Catrol modules；
The CMOS camera module collection view data is transmitted to data conversion module, carries out data conversion and then divides two-way defeated Go out；It is directly entered outside DDR3 memory modules by data input DDR3 fifo modules all the way to be cached, another way is passed through RGB turns gray scale module RGB and turned after gray proces, medium filtering module median filter process again by data input DDR3 FIFO Module enters outside DDR3 memory modules and cached, and wherein DDR3 Read-write Catrols module is used for the outside DDR3 of control data disengaging Memory module；The two frame greyscale image datas continuously exported by data output DDR3 fifo modules from DDR3 memory modules Inter-frame difference computing, binary conversion treatment, corrosion expansion process are carried out by inter-frame difference and binarization block, corrosion expansion module The coordinate value of Motion mask is obtained afterwards, then by Motion mask extraction module, the coordinate value of Motion mask is fed back into rgb format To obtain templates of moving objects on coloured image, the storage of FPGA ram in slice is deposited into, finally passes through Motion mask using it Taken exercises template matches with module, to realize the tracking of color motion target, and its movement locus can be depicted and passed through VGA displays driving and serially printing module carry out upper computer software and show and print movement locus coordinate values.
CMOS camera module：For by the rgb format image information of collection, including more bit image datas, 1 bit field Synchronizing signal, 1 bit line synchronising signal, CMOS gathered data synchronizing clock signals, all deliver to data conversion module；
Data conversion module：The conversion of data bit width is carried out for 8 bit datas that will collect, be converted into 16 bit datas or The bit data of person 24, and deliver to RGB respectively and turn gray scale module and DDR3 storage moulds are sent into by data input DDR3 fifo modules Block is cached；Because the data of CMOS camera acquisition module collection are 8 bit datas, but in rgb format coloured image, One pixel is generally 16 bit datas or 24 bit datas.So to carry out the conversion of data bit width.Equally, CMOS takes the photograph As the synchronous acquisition clock of head is also corresponding slack-off 2 times or 3 times.The field line synchronising signal not dealt with will also pass through corresponding Delay form new field line synchronising signal, these new data then are delivered into RGB turns gray scale module.
RGB turns gray scale module：, can for the rgb format image of 16 or 24 to be changed into 8 grayscale format images Amount of calculation is reduced for later calculating.The greyscale image data converted is delivered into medium filtering module；
Medium filtering module：After rgb format coloured image is changed into grayscale format image, medium filtering is carried out, by intermediate value View data after filtering delivers to data input DDR3 fifo modules；Because rgb format coloured image changes into grayscale format figure As after, the inside can noisy presence, noise on image quality has a great impact, and progress medium filtering can not only remove orphan Spot noise, moreover it is possible to keep the local edge of image, image will not produce significant fuzzy.Become using picture quality after medium filtering The high processing more to prepare behind aspect.
Data input DDR3 fifo modules：This fifo module is mainly for the treatment of across clocked data transfer and data bit Width conversion；Data after medium filtering are sent into DDR3 read-write clock zone and data bit width from synchronous acquisition clock zone Change into the same bit wide length of same DDR3 reading-writing ports；Data after processing are delivered into outside DDR3 memory modules；
DDR3 memory modules：Because image data amount is big, FPGA piece memory storage resources use far from enough, outside you must use Memory come cached with solve the problems, such as big data across clock transfer；
Data output DDR3 fifo modules：This fifo module turns mainly for the treatment of across clocked data transfer and data bit width Change；Data are from DDR3 read-write clock zone feeding VGA read clocks domain and the same from DDR3 reading-writing ports data bit width Bit wide change into the bit wide size of a pixel data；Data after processing are delivered into inter-frame difference and binarization block；
Inter-frame difference and binarization block：Including interframe subtraction module, binary conversion treatment module；Interframe subtraction module is by continuous two The data that frame greyscale image data subtracts each other to obtain deliver to binary conversion treatment module and carry out binary conversion treatment；By inter-frame difference and two Value module goes out moving target for Preliminary detection, and the data after processing are delivered into corrosion expansion module；If do not move mesh Target is present, then the data of continuous two two field pictures correspondence position can be relatively.On the contrary, in some position of continuous two frame View data can have a greater change, so tentatively can detect moving target by inter-frame difference and binarization block.
Corrode expansion module：For removing the noise spot in the image after inter-frame difference and binaryzation and to remove cavity existing As；Data after processing are delivered into Motion mask extraction module；Image by difference and binaryzation output occurs that cavity is existing As and noise spot, processing below can be had an impact, so to remove noise spot in image simultaneously by corroding expansion module Remove cavitation.Data after processing are delivered into Motion mask extraction module.
Motion mask extraction module：Moving target is extracted according to block size, the moving target detected is big with template Small deposit FPGA on-chip memories, to be supplied to Motion mask matching module；
Motion mask matching module：Each two field picture after being matched using obtained Motion mask, calculates optimal match point, Reach tracking effect；And the data that processing can be gone out deliver to VGA displays driving and serially printing module；
VGA displays driving and serially printing module：For tracking result to be presented directly into user；VGA displays are used to show Tracking effect and movement locus, serially printing are used to print movement locus numerical value.
A kind of moving object detection tracking based on FPGA, methods described step are：View data carries out data and turned Change and then divide two-way to export；DDR3 memory modules are directly entered all the way to be cached, another way by RGB turn gray proces, in Cached after value filtering processing into DDR3 memory modules；The two frame greyscale image datas continuously exported from DDR3 buffers The coordinate value of Motion mask is obtained after carrying out inter-frame difference computing, binary conversion treatment, corrosion expansion process, then feeds back to RGB lattice To obtain templates of moving objects on formula coloured image, the storage of FPGA ram in slice is deposited into, finally utilizes its template of taking exercises Match somebody with somebody, to realize the tracking of color motion target, and its movement locus and upper computer software display movement locus can be depicted Coordinate values.
When described image data carry out data conversion and then divide the two-way to export, the method for data conversion is spliced using displacement Method.Such as 8 bit data inputs are required, 16 bit data outputs.Two 8 bit datas are exactly spliced into one 16 ratio Special data.Then clock rate becomes original speed half all the time.
The method that the RGB turns gray proces is that RGB changes into YCbCr format, then only takes its Y-component to obtain gray-scale map Picture；The formula that RGB turns YCbCr is as follows：
Y= 0.183R + 0.614G + 0.062B + 16；
Cb = -0.101R – 0.338G + 0.439B + 128；
Cr = 0.439R – 0.399G – 0.040B + 128；
Because Verilog can not carry out floating-point operation, therefore first expand 256 times, in 8 bit-wises that move right, after conversion Formula is：
Y= （47R + 157G + 16B + 4096）>> 8；
Cb = （26R – 86G + 112B + 32768）>> 8；
Cr = （112R – 102G – 10B + 32768）>> 8；
Finally, RGB Three-channel datas originally all take the numerical value of Y-component, and image is just converted into grayscale format from rgb format.
The method of the median filter process includes；First, three pixels of every row are ranked up respectively；Then, it is right The sequence that three row pixels obtain is handled, i.e. minimum value in three maximums of extraction, the maximum in three minimum values, with And the median of three medians；Finally, by obtained in second step three values, intermediate value is taken again, has thus finally given 9 The median of individual pixel.
The method of inter-frame difference computing and binary conversion treatment is exactly that data are subtracted each other and then are compared with threshold value, more than threshold value Complete 1 is just set to as white, it is black to be otherwise just set to full 0, and wherein threshold value takes 25.
Corroding the method for expansion process is：Corrosion treatment is following three step, first, with 3 × 3 window modules to input two Value image traversal；Then, AND operation all is done with 1 to the total data in 3 × 3 windows；Finally, as long as there is pixel Value is 0, is as a result 0；1 is all, is as a result only 1；Expansion process equally point three steps；First, with 3 × 3 window modules to input Binary image travels through；Then, inclusive-OR operation all is done with 1 to the total data in 3 × 3 windows；Finally, as long as there is a pixel Numerical value be 1, be as a result 1；0 is all, is as a result just 0.
Templates of moving objects extraction method be：To numerical value in binary image for 1 transverse and longitudinal coordinate a little carry out Statistics, calculate minimum row where target, maximum row and minimum row, maximum column and barycenter；Then this parameter is returned to The coloured image of rgb format.
Motion mask matching method be：Absolute value sum algorithm, i.e. SAD matching algorithms；It is empty for RGB color image Between, its formula is as follows：
C = ∑（ |Rx– Rx+1| + |Gx– Gx+1| + |Bx– Bx+1| ）
The minimum point of numerical value, is exactly optimal match point；
Wherein in above-mentioned formula represent two continuous frames image same position corresponding to tri- components of RGB numerical value subtract each other absolute value it With R=red, G=green, B=blue.
The beneficial effects of the invention are as follows：
The present invention determines moving target using frame difference method, can adapt to the detection under different background.And it have passed through filtering, two The processing such as value, morphology so that moving object detection is more accurate.FPGA parallel pipelines are taken when template matches Processing mode, matching speed can be greatly speeded up, and be the matching carried out under RGB color image, colored fortune can be realized The tracking of moving-target, and movement locus is depicted, and trajectory coordinates are shown on host computer；
Present system can be parallel, and overall operation speed is faster than PC platform；In terms of volume, the present invention adds for circuit board to be taken the photograph It is certainly smaller than PC platform by volume as head is added some points encapsulation；In terms of power consumption, much lower than PC platform of the present invention；With arm platforms pair Than faster than ARM platform in speed.
Brief description of the drawings
Fig. 1 is the system block diagram of the present invention；
Fig. 2 is flow chart of the method for the present invention.
Embodiment
Below in conjunction with the accompanying drawings and specific embodiment, the invention will be further described.
Embodiment 1：As shown in Figure 1-2, a kind of moving object detection tracking system and method based on FPGA, including CMOS Camera module, data conversion module, RGB turn gray scale module, medium filtering module, data input DDR3 fifo modules, data Export DDR3 fifo modules, inter-frame difference and binarization block, corrosion expansion module, Motion mask extraction module, Motion mask Matching module, VGA displays driving and serially printing module, DDR3 Read-write Catrol modules；
The CMOS camera module collection view data is transmitted to data conversion module, carries out data conversion and then divides two-way defeated Go out；It is directly entered outside DDR3 memory modules by data input DDR3 fifo modules all the way to be cached, another way is passed through RGB turns gray scale module RGB and turned after gray proces, medium filtering module median filter process again by data input DDR3 FIFO Module enters outside DDR3 memory modules and cached, and wherein DDR3 Read-write Catrols module is used for the outside DDR3 of control data disengaging Memory module；The two frame greyscale image datas continuously exported by data output DDR3 fifo modules from DDR3 memory modules Inter-frame difference computing, binary conversion treatment, corrosion expansion process are carried out by inter-frame difference and binarization block, corrosion expansion module The coordinate value of Motion mask is obtained afterwards, then by Motion mask extraction module, the coordinate value of Motion mask is fed back into rgb format To obtain templates of moving objects on coloured image, the storage of FPGA ram in slice is deposited into, finally passes through Motion mask using it Taken exercises template matches with module, to realize the tracking of color motion target, and its movement locus can be depicted and passed through VGA displays driving and serially printing module carry out upper computer software and show and print movement locus coordinate values.
As the further scheme of the present invention, in addition to Clock management module, SCCB communication modules；
Clock management module：Crystal oscillator 50MHZ clocks pass through Clock management DCM IP kernels on plate, produce four that whole system needs Clock, it is global system clock, CMOS camera driving clock, DDR3 memory modules driving clock and VGA display modules respectively Drive clock.
SCCB communication modules：Effect is for driving CMOS camera module.SCCB agreements one share 2 lines, respectively It is clock line and data wire, according to the agreement of regulation, carries out data transmission.Using SCCB agreements, related CMOS register counts Value delivers to CMOS camera module, to drive CMOS camera to work.
CMOS camera module：For by the rgb format image information of collection；Specifically include more bit image datas, 1 Bit field sync signal, 1 bit line synchronising signal, CMOS gathered data synchronizing clock signals, all deliver to data conversion module； The movable information of the target color of CMOS camera shooting（Track and coordinate values etc.）, dynamically it is presented on VGA displays simultaneously It is transferred in host computer；The 500W high definitions CMOS that camera image acquisition module can produce using Omnivision companies Camera OV5640, fpga chip can use the XC6SLX16 of the Spartan6 series of Xilinx companies product；
Data conversion module：The conversion of data bit width is carried out for 8 bit datas that will collect, be converted into 16 bit datas or The bit data of person 24, and deliver to RGB respectively and turn gray scale module and DDR3 storage moulds are sent into by data input DDR3 fifo modules Block is cached；Because the data of CMOS camera acquisition module collection are 8 bit datas, but in rgb format coloured image, One pixel is generally 16 bit datas or 24 bit datas.So to carry out the conversion of data bit width.Equally, CMOS takes the photograph As the synchronous acquisition clock of head is also corresponding slack-off 2 times or 3 times.The field line synchronising signal not dealt with will also pass through corresponding Delay form new field line synchronising signal, these new data then are delivered into RGB turns gray scale module.
Specifically, according to 1 bit（I.e. 1）Field sync signal, 1 bit line synchronising signal and synchronous acquisition clock, will be more Bit image data carries out bit width conversion, is typically translated into the bit wide of a pixel number evidence, such as RGB565 of 16 bit wides or The RGB888 of 24 bit wides.The data for producing 1 new bit field sync signal, 1 new bit line synchronising signal and 1 bit simultaneously have Imitate signal.And will it is new caused by more bit image datas, 1 new bit field sync signal, 1 new bit line synchronising signal, same Step collection clock and 1 bit data useful signal deliver to RGB and turn gray scale module and data input DDR3 fifo modules respectively.
RGB turns gray scale module：, can for the rgb format image of 16 or 24 to be changed into 8 grayscale format images Amount of calculation is reduced for later calculating.The greyscale image data converted is delivered into medium filtering module；
Specifically, according to 1 new bit field sync signal, 1 new bit line synchronising signal, 1 bit data valid signal and Synchronous acquisition clock, new more bit rgb format data are changed into grayscale format image.Rgb format turns grayscale format can be first YCbCr format is changed into by RGB, then only takes its Y-component to obtain gray level image.The formula that RGB turns YCbCr is as follows：
Y= 0.183R + 0.614G + 0.062B + 16
Cb = -0.101R – 0.338G + 0.439B + 128
Cr = 0.439R – 0.399G – 0.040B + 128
Because Verilog can not carry out floating-point operation, therefore can first expand 256 times, in 8 bit-wises that move right, conversion Formula afterwards is：
Y= （47R + 157G + 16B + 4096）>> 8
Cb = （26R – 86G + 112B + 32768）>> 8
Cr = （112R – 102G – 10B + 32768）>> 8
To synchronously it believe by transformed grayscale format data and caused 1 new bit field sync signal, 1 new bit-rows Number, 1 new bit data useful signal and synchronous acquisition clock deliver to 3 × 3 window modules.
3 × 3 window modules：The module is and medium filtering module together cooperating.In the exploitation of altera corp It can be built in external member using Shift Register IP kernels.In addition, also have by RAM or FIFO to build.
Medium filtering module：After rgb format coloured image is changed into grayscale format image, medium filtering is carried out, will View data after medium filtering delivers to data input DDR3 fifo modules；Because rgb format coloured image changes into gray scale lattice After formula image, the inside can noisy presence, noise on image quality has a great impact, and carrying out medium filtering can not only go Except acnode noise, moreover it is possible to keep the local edge of image, image will not produce significant fuzzy.Use image matter after medium filtering Processing of the quantitative change height more to prepare behind aspect.Using 3 × 3 window modules, the purpose of median filtering algorithm only require 3 × 3 The median of pel array.Specific method only needs three steps, and first, three pixels of every row are arranged respectively Sequence.Then, the sequence obtained to three row pixels is handled, i.e. minimum value in three maximums of extraction, in three minimum values Maximum, and the median of three medians.Finally, by obtained in second step three values, intermediate value is taken again, thus The median of 9 pixels is finally given.Using Verilog HDL parallel characteristics, this process only needs three clocks. Likewise, field sync signal, line synchronising signal and data valid signal also want corresponding three clocks of delay to obtain new field Synchronizing signal, new line synchronising signal and new data valid signal.And these new data-signals are delivered into data input DDR3 fifo modules.
Data input DDR3 fifo modules：This fifo module is mainly for the treatment of across clocked data transfer and data bit Width conversion；Data after medium filtering are sent into DDR3 read-write clock zone and data bit width from synchronous acquisition clock zone Change into the same bit wide length of same DDR3 reading-writing ports；Data after processing are delivered into outside DDR3 memory modules；
DDR3 memory modules：Because image data amount is big, FPGA piece memory storage resources use far from enough, outside you must use Memory come cached with solve the problems, such as big data across clock transfer；
DDR3 Read-write Catrol modules：The main function of this module is the outside DDR3 memory modules of control data disengaging, in FPGA Corresponding IP kernel can be typically integrated in development kit, has corresponding user interface.As long as these user interfaces are correctly controlled, just DDR3 memory modules can very easily be read and write.Here DDR3 memory modules are arranged to 2 input ports and 3 output ports, and 2 What individual input port was respectively that a port enters is rgb format coloured picture view data, and what a port was entered is by grey scale change And the grayscale format view data after medium filtering；3 output ports be respectively 1 port go out be rgb format colour View data, what 2 ports went out is two continuous frames greyscale image data.These data deliver to data output DDR3 fifo modules.
Data output DDR3 fifo modules：This fifo module is mainly for the treatment of across clocked data transfer and data bit Width conversion；Data are sent into VGA read clocks domain from DDR3 read-write clock zone and data bit width from DDR3 reading-writing ports The same bit wide changes into the bit wide size of a pixel data；Data after processing are delivered into interframe subtraction module；
Interframe subtraction module：The effect of this module is to detect moving target.Specific formula is as follows：
D(x,y) = |Fx(x,y) – Fx+1(x,y)|
The data that two continuous frames greyscale image data subtracts each other to obtain are delivered into binary conversion treatment module.
Binary conversion treatment module：This module is to more preferably more obviously come out moving target indication.If greater than Threshold value is set to 1, is otherwise set to 0.Specific formula is as follows：
Data after binaryzation are delivered into corrosion expansion process module.
The data that two continuous frames greyscale image data subtracts each other to obtain are delivered to binary conversion treatment module and entered by interframe subtraction module Row binary conversion treatment；Go out moving target for Preliminary detection by inter-frame difference and binarization block, the data after processing are sent To corrosion expansion module；If without the presence of moving target, then the data of continuous two two field pictures correspondence position, which can compare, to be connect Closely.On the contrary, some location drawing picture data in continuous two frame can have a greater change, so by inter-frame difference and binaryzation Module tentatively can detect moving target.
Corrode expansion module：For removing the noise spot in the image after inter-frame difference and binaryzation and to remove cavity existing As；Data after processing are delivered into Motion mask extraction module；Image by difference and binaryzation output occurs that cavity is existing As and noise spot, processing below can be had an impact, thus need Morphological scale-space reduce cavity and remove isolated noise Point.Here Morphological scale-space is exactly to first carry out erosion operation to carry out expansion process again.Corrosion expansion process needs also exist for 3 × 3 Window module.Corrosion treatment is specifically divided into three steps：First, the binary image of input is traveled through with 3 × 3 window modules；Then, AND operation all is done with 1 to the total data in 3 × 3 windows；Finally, it is as a result 0 as long as the value for having a pixel is 0.It is all 1, as a result it is only 1.Expansion process equally point three steps：First, the binary image of input is traveled through with 3 × 3 window modules；So Afterwards, inclusive-OR operation all is done with 1 to the total data in 3 × 3 windows；Finally, as long as the numerical value for having a pixel is 1, as a result for 1.0 is all, is as a result just 0.Data after treated are delivered to moving target recognition template.
Motion mask extraction module：Moving target is extracted according to block size, the moving target detected is big with template Small deposit FPGA on-chip memories, to be supplied to Motion mask matching module；Specific method is 1 transverse and longitudinal coordinate a little counted, calculate minimum row where target, maximum row and minimum row, maximum column and matter The heart.Then the coloured image of this parameter feedback to rgb format, such moving target are just extracted, but from From the aspect of resource considers two in track speed and FPGA pieces, this module is not conducive to excessive.Can according to actual conditions and resource come Select the template of suitable size.The template of extraction delivers to the storage of FPGA ram in slice and finally delivers to Motion mask from ram in slice storage Matching module.
Motion mask matching module：Each two field picture after being matched using obtained Motion mask, calculates optimal With point, reach tracking effect；And the data that processing can be gone out deliver to VGA displays driving and serially printing module；Template matches are calculated Method has many kinds, used here as most suitable FPGA matching algorithm, i.e. absolute value sum algorithm（SAD）.It is colored for rgb format Image space, its formula are as follows：
C = ∑（ |Rx– Rx+1| + |Gx– Gx+1| + |Bx– Bx+1| ）
FPGA parallel behavior can be utilized herein, take flowing water technology to accelerate computing.Then, it is exactly to similarity measurements The result of calculation of amount is compared, and finds the position of SAD minimum points, and the point is exactly optimal match point.Finally by data result Deliver to VGA display modules and serially printing module.
VGA display modules：The effect of the module is for driving VGA displays, and final result is presented on into VGA displays On.First, the resolution sizes of VGA displays are determined, then provide corresponding driving clock again, field sync signal, row is synchronously Signal and process handle obtained final image data above, and moving target quilt can be just shown on rgb format coloured image The effect of tracking and the movement locus of moving target.
Serially printing module：The effect of the module is that the track data of moving target motion is shown on upper computer software, That is moving target center-of-mass coordinate value.The baud rate of serial ports is first determined, correctly description, which sends and receives sequential, just can correctly exist Continually changing center-of-mass coordinate numerical value is printed in upper computer software.
A kind of moving object detection tracking based on FPGA, methods described step are：View data carries out data and turned Change and then divide two-way to export；DDR3 memory modules are directly entered all the way to be cached, another way by RGB turn gray proces, in Cached after value filtering processing into DDR3 memory modules；The two frame greyscale image datas continuously exported from DDR3 buffers The coordinate value of Motion mask is obtained after carrying out inter-frame difference computing, binary conversion treatment, corrosion expansion process, then feeds back to RGB lattice To obtain templates of moving objects on formula coloured image, the storage of FPGA ram in slice is deposited into, finally utilizes its template of taking exercises Match somebody with somebody, to realize the tracking of color motion target, and its movement locus and upper computer software display movement locus can be depicted Coordinate values.
As the further scheme of the present invention, when described image data carry out data conversion and then divide the two-way to export, data The method of conversion is using displacement splicing method.Such as 8 bit data inputs are required, 16 bit data outputs.It is exactly two 8 Bit data is spliced into 16 bit datas.Then clock rate becomes original speed half all the time.
As the further scheme of the present invention, the method that the RGB turns gray proces is that RGB changes into YCbCr format, then Its Y-component is only taken to obtain gray level image；The formula that RGB turns YCbCr is as follows：
Y= 0.183R + 0.614G + 0.062B + 16；
Cb = -0.101R – 0.338G + 0.439B + 128；
Cr = 0.439R – 0.399G – 0.040B + 128；
Because Verilog can not carry out floating-point operation, therefore first expand 256 times, in 8 bit-wises that move right, after conversion Formula is：
Y = （47R + 157G + 16B + 4096）>> 8；
Cb = （26R – 86G + 112B + 32768）>> 8；
Cr = （112R – 102G – 10B + 32768）>> 8；
Finally, RGB Three-channel datas originally all take the numerical value of Y-component, and image is just converted into grayscale format from rgb format.
As the further scheme of the present invention, the method for the median filter process includes；First, respectively to the three of every row Individual pixel is ranked up；Then, the sequence obtained to three row pixels is handled, that is, extracts the minimum value in three maximums, Maximum in three minimum values, and the median of three medians；Finally, by obtained in second step three values, again Intermediate value is taken, has thus finally given the median of 9 pixels.
As the further scheme of the present invention, the method for inter-frame difference computing and binary conversion treatment is exactly then data are subtracted each other It is compared with threshold value, complete 1 is just set to more than threshold value as white, it is black to be otherwise just set to full 0, and wherein threshold value takes 25.
As the further scheme of the present invention, corroding the method for expansion process is：Corrosion treatment is following three step, first, The binary image of input is traveled through with 3 × 3 window modules；Then, "AND" fortune is all done with 1 to the total data in 3 × 3 windows Calculate；Finally, it is as a result 0 as long as the value for having a pixel is 0；1 is all, is as a result only 1；Expansion process equally point three steps；It is first First, the binary image of input is traveled through with 3 × 3 window modules；Then, the total data in 3 × 3 windows is all done with 1 Inclusive-OR operation；Finally, it is as a result 1 as long as the numerical value for having a pixel is 1；0 is all, is as a result just 0.
As the further scheme of the present invention, the method for templates of moving objects extraction is：It is 1 to numerical value in binary image Transverse and longitudinal coordinate a little counted, calculate minimum row where target, maximum row and minimum row, maximum column and matter The heart；Then this parameter is returned to the coloured image of rgb format.
As the further scheme of the present invention, the method for Motion mask matching is：Absolute value sum algorithm, i.e. SAD matchings Algorithm；It is as follows for RGB color image space, its formula：
C = ∑（ |Rx– Rx+1| + |Gx– Gx+1| + |Bx– Bx+1| ）
The minimum point of numerical value, is exactly optimal match point；
Wherein in above-mentioned formula represent two continuous frames image same position corresponding to tri- components of RGB numerical value subtract each other absolute value it With R=red, G=green, B=blue.
The specific embodiment of the present invention is explained in detail above in conjunction with accompanying drawing, but the present invention is not limited to above-mentioned reality Example is applied, can also be on the premise of present inventive concept not be departed from those of ordinary skill in the art's possessed knowledge Various changes can be made.

Claims (10)

  1. A kind of 1. moving object detection tracking system based on FPGA, it is characterised in that：Turn including CMOS camera module, data Mold changing block, RGB turn gray scale module, medium filtering module, data input DDR3 fifo modules, data output DDR3 FIFO moulds Block, inter-frame difference and binarization block, corrosion expansion module, Motion mask extraction module, Motion mask matching module, VGA show Show driving and serially printing module, DDR3 Read-write Catrol modules；
    The CMOS camera module collection view data is transmitted to data conversion module, carries out data conversion and then divides two-way defeated Go out；It is directly entered outside DDR3 memory modules by data input DDR3 fifo modules all the way to be cached, another way is passed through RGB turns gray scale module RGB and turned after gray proces, medium filtering module median filter process again by data input DDR3 FIFO Module enters outside DDR3 memory modules and cached, and wherein DDR3 Read-write Catrols module is used for the outside DDR3 of control data disengaging Memory module；The two frame greyscale image datas continuously exported by data output DDR3 fifo modules from DDR3 memory modules Inter-frame difference computing, binary conversion treatment, corrosion expansion process are carried out by inter-frame difference and binarization block, corrosion expansion module The coordinate value of Motion mask is obtained afterwards, then by Motion mask extraction module, the coordinate value of Motion mask is fed back into rgb format To obtain templates of moving objects on coloured image, the storage of FPGA ram in slice is deposited into, finally passes through Motion mask using it Taken exercises template matches with module, to realize the tracking of color motion target, and its movement locus can be depicted and passed through VGA displays driving and serially printing module carry out upper computer software and show and print movement locus coordinate values.
  2. 2. the moving object detection tracking system according to claim 1 based on FPGA, it is characterised in that：
    CMOS camera module：For by the rgb format image information of collection, including more bit image datas, 1 bit field synchronization Signal, 1 bit line synchronising signal, CMOS gathered data synchronizing clock signals, all deliver to data conversion module；
    Data conversion module：The conversion of data bit width is carried out for 8 bit datas that will collect, be converted into 16 bit datas or The bit data of person 24, and deliver to RGB respectively and turn gray scale module and DDR3 storage moulds are sent into by data input DDR3 fifo modules Block is cached；
    RGB turns gray scale module：For the rgb format image of 16 or 24 to be changed into 8 grayscale format images, will convert Greyscale image data deliver to medium filtering module；
    Medium filtering module：After rgb format coloured image is changed into grayscale format image, medium filtering is carried out, by intermediate value View data after filtering delivers to data input DDR3 fifo modules；
    Data input DDR3 fifo modules：This fifo module turns mainly for the treatment of across clocked data transfer and data bit width Change；Data after medium filtering are sent into DDR3 read-write clock zone from synchronous acquisition clock zone and data bit width is converted The bit wide length the same into same DDR3 reading-writing ports；Data after processing are delivered into outside DDR3 memory modules；
    DDR3 memory modules：For it is data cached with solve big data across clock transfer；
    Data output DDR3 fifo modules：This fifo module turns mainly for the treatment of across clocked data transfer and data bit width Change；Data are from DDR3 read-write clock zone feeding VGA read clocks domain and the same from DDR3 reading-writing ports data bit width Bit wide change into the bit wide size of a pixel data；Data after processing are delivered into inter-frame difference and binarization block；
    Inter-frame difference and binarization block：Including interframe subtraction module, binary conversion treatment module；Interframe subtraction module is by continuous two The data that frame greyscale image data subtracts each other to obtain deliver to binary conversion treatment module and carry out binary conversion treatment；By inter-frame difference and two Value module goes out moving target for Preliminary detection, and the data after processing are delivered into corrosion expansion module；
    Corrode expansion module：For removing the noise spot in the image after inter-frame difference and binaryzation and removing cavitation；Will Data after processing deliver to Motion mask extraction module；
    Motion mask extraction module：Moving target is extracted according to block size, the moving target detected is deposited with template size Enter FPGA on-chip memories, to be supplied to Motion mask matching module；
    Motion mask matching module：Each two field picture after being matched using obtained Motion mask, calculates optimal match point, Reach tracking effect；And the data that processing can be gone out deliver to VGA displays driving and serially printing module；
    VGA displays driving and serially printing module：For tracking result to be presented directly into user；VGA displays are used to show Tracking effect and movement locus, serially printing are used to print movement locus numerical value.
  3. A kind of 3. moving object detection tracking based on FPGA, it is characterised in that：Then view data carries out data conversion Divide two-way output；It is directly entered DDR3 memory modules all the way to be cached, another way turns gray proces, medium filtering by RGB Cached after processing into DDR3 memory modules；The two frame greyscale image datas continuously exported from DDR3 buffers carry out frame Between calculus of differences, binary conversion treatment, corrosion expansion process after obtain the coordinate value of Motion mask, then feed back to rgb format colour To obtain templates of moving objects on image, the storage of FPGA ram in slice is deposited into, finally using its template matches of taking exercises, with The tracking of color motion target is realized, and its movement locus and upper computer software display movement locus number of coordinates can be depicted Value.
  4. 4. the moving object detection tracking according to claim 3 based on FPGA, it is characterised in that：Described image number During according to carrying out data conversion and then divide the two-way to export, the method for data conversion is using displacement splicing method.
  5. 5. the moving object detection tracking according to claim 3 based on FPGA, it is characterised in that：The RGB turns The method of gray proces is that RGB changes into YCbCr format, then only takes its Y-component to obtain gray level image；RGB turns YCbCr public affairs Formula is as follows：
    Y= 0.183R + 0.614G + 0.062B + 16；
    Cb = -0.101R – 0.338G + 0.439B + 128；
    Cr = 0.439R – 0.399G – 0.040B + 128；
    Because Verilog can not carry out floating-point operation, therefore first expand 256 times, in 8 bit-wises that move right, after conversion Formula is：
    Y= （47R + 157G + 16B + 4096）>> 8；
    Cb = （26R – 86G + 112B + 32768）>> 8；
    Cr = （112R – 102G – 10B + 32768）>> 8；
    Finally, RGB Three-channel datas originally all take the numerical value of Y-component, and image is just converted into grayscale format from rgb format.
  6. 6. the moving object detection tracking according to claim 3 based on FPGA, it is characterised in that：The intermediate value filter The method of ripple processing includes；First, three pixels of every row are ranked up respectively；Then, the sequence three row pixels obtained Handled, i.e. minimum value in three maximums of extraction, the maximum in three minimum values, and the centre of three medians Value；Finally, by obtained in second step three values, intermediate value is taken again, has thus finally given the median of 9 pixels.
  7. 7. the moving object detection tracking according to claim 3 based on FPGA, it is characterised in that：Frame-to-frame differences partite transport Calculate and the method for binary conversion treatment is exactly that data are subtracted each other and then are compared with threshold value, complete 1 is just set to more than threshold value as white, it is no It is black to be then just set to full 0, and wherein threshold value takes 25.
  8. 8. the moving object detection tracking according to claim 3 based on FPGA, it is characterised in that：Corrode at expansion The method of reason is：Corrosion treatment is following three step, and first, the binary image of input is traveled through with 3 × 3 window modules；Then, AND operation all is done with 1 to the total data in 3 × 3 windows；Finally, it is as a result 0 as long as the value for having a pixel is 0；It is all 1, as a result it is only 1；Expansion process equally point three steps；First, the binary image of input is traveled through with 3 × 3 window modules；So Afterwards, inclusive-OR operation all is done with 1 to the total data in 3 × 3 windows；Finally, as long as the numerical value for having a pixel is 1, as a result for 1；0 is all, is as a result just 0.
  9. 9. the moving object detection tracking according to claim 3 based on FPGA, it is characterised in that：Moving target mould Plate extraction method be：To numerical value in binary image for 1 transverse and longitudinal coordinate a little count, where calculating target Minimum row, maximum row and minimum row, maximum column and barycenter；Then this parameter is returned to the coloured image of rgb format.
  10. 10. the moving object detection tracking according to claim 3 based on FPGA, it is characterised in that：Motion mask The method of matching is：Absolute value sum algorithm, i.e. SAD matching algorithms；It is as follows for RGB color image space, its formula：
    C = ∑（ |Rx – Rx+1| + |Gx – Gx+1| + |Bx – Bx+1| ）
    The minimum point of numerical value, is exactly optimal match point；
    Wherein in above-mentioned formula represent two continuous frames image same position corresponding to tri- components of RGB numerical value subtract each other absolute value it With R=red, G=green, B=blue.
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CN110728617A (en) * 2019-09-30 2020-01-24 上海电机学院 FPGA-based dynamic target identification and real-time tracking system
CN111340841A (en) * 2020-03-19 2020-06-26 昆明理工大学 Real-time multi-moving-object detection method and system
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CN113610221A (en) * 2021-06-29 2021-11-05 西安电子科技大学 Variable expansion convolution operation hardware system based on FPGA
CN113610221B (en) * 2021-06-29 2024-02-13 西安电子科技大学 FPGA-based variable expansion convolution operation hardware system
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