CN109429043A - The acquisition system and method for traffic sign video image based on FPGA - Google Patents
The acquisition system and method for traffic sign video image based on FPGA Download PDFInfo
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Abstract
The acquisition system and method for the invention discloses a kind of traffic sign video image based on FPGA, acquisition system includes camera control module, Bayer image processing module, image filtering module, Image Edge-Detection module, image storage module, ethernet communication module and NIOS II processor, FPGA is used to realize with upper module, it then follows Avalon Memory-Mapped interface specification and Avalon Streaming interface specification.The video image acquisition method that the characteristics of present invention is a kind of feature and traffic sign recognition method according to traffic sign color is designed, utilize the concurrency feature of FPGA, by the way of assembly line, while picture collection, picture is pre-processed, the real-time of picture processing is substantially increased, while reducing the requirement to picture memory capacity.
Description
Technical field
The present invention relates to image acquisition technology, the acquisition system of especially a kind of traffic sign video image based on FPGA
And method.
Background technique
As the living standard of economic continuous development, the continuous development of auto industry, the people is continuously improved, China is
Stride into automotive society.Thus a series of problem, such as traffic jam, traffic noise, traffic accident etc. are also brought.In order to solve
Traffic problems, intelligent transportation system are come into being.Unmanned, intelligent automobile, car steering auxiliary system etc. continues to develop.It hands over
Important component of the identification of logical mark as intelligent automobile, can feed back to driver for road signs information, can make
The case where driver understands specific road conditions and needs to pay attention to, to reduce traffic accident.Traffic sign mainly has
Instruction, warning, and forbid class etc..Every one kind traffic sign is all made of the pattern and text of specific color and shape, often
The color seen has red, yellow, blue etc., common shape to have circle, triangle, rectangle etc..
Current traffic sign Video Image Collecting System Based is buffered in storage core after generally having acquired image using camera
In piece, original image is transmitted directly to host computer, the detection of traffic sign is completed by host computer and knows method for distinguishing.Software system
Serial processing mode is used as unified, causes the speed of image procossing slower, real-time performance is poor, is very difficult to apply in actual system
In system.
Summary of the invention
The acquisition system and method for the purpose of the present invention is to provide a kind of traffic sign video image based on FPGA.
Realize the technical solution of the object of the invention are as follows: a kind of acquisition system of the traffic sign video image based on FPGA,
By camera control module, Bayer image processing module, image filtering module, Image Edge-Detection module, image storage module,
Ethernet communication module and NIOS II processor composition；It is realized using FPGA hardware logic with upper module, it then follows Avalon
Memory-Mapped interface specification, Avalon Streaming interface specification and SCCB camera control bus specification；
Camera control module is for being configured camera parameter；
Bayer image processing module converts images into satisfactory image for handling Bayer image；
Image filtering module is used to carry out noise filtering to by Bayer image processing module treated image；
Edge of the Image Edge-Detection module for image after the processing of detection image filter module, and will treated image
Data conversion is at the data for meeting Avalon Streaming interface specification；
Image storage module is for storing the image after edge detection；
Ethernet communication module is used to read the image data of image storage module storage, and image data is passed through ether
Net is sent to host computer；
NIOS II processor is used for the Collaborative Control of whole system.
A kind of acquisition method of the traffic sign video image based on FPGA, comprising the following steps:
Step 1, camera parameter information is sent to camera, camera is configured；
Step 2, camera data is handled image by Bayer image processing module；
Step 3, the processed image of Bayer image processing module is passed through into image filtering module, be filtered；
Step 4, edge detection module carries out edge detection to filtered image, while being accorded with by the way that stream compression to be melted into
Close the data flow of Avalon Streaming；
Step 5, the data received are stored in DDR3 by data memory module, and ethernet communication module is waited to read number
According to.
Step 6, the data being stored in DDR3 are sent to host computer by ethernet controller.
Compared with prior art, remarkable advantage of the invention are as follows: the traffic sign acquisition system that the present invention designs is basis
The acquisition method dedicated for traffic sign video image that the characteristics of traffic sign and traffic sign recognition method is designed, fills
The characteristics of dividing the concurrency using FPGA carries out picture during picture collection using the processing mode of pipelining line
Processing, algorithm is simple, data volume is big previous work is realized using FPGA, reduces the pre-processing of picture recognition system
Time enhances the real-time of Traffic Sign Recognition System.
Detailed description of the invention
Fig. 1 is that the present invention is based on the hardware block diagrams of the acquisition system of the traffic sign video image of FPGA.
Fig. 2 is that the present invention is based on the functional block diagrams of the acquisition system of the traffic sign video image of FPGA.
Fig. 3 is acquisition method flow chart of the invention.
Fig. 4 is acquisition method flow chart in the embodiment of the present invention.
Specific embodiment
In conjunction with Fig. 1, Fig. 2, a kind of acquisition system of the traffic sign video image based on FPGA, by camera control module,
Bayer image processing module, image filtering module, Image Edge-Detection module, image storage module, ethernet communication module and
NIOS II processor composition；It is realized using FPGA hardware logic with upper module, it then follows Avalon Memory-Mapped interface rule
Model, Avalon Streaming interface specification and SCCB camera control bus specification；
Camera control module is for being configured camera parameter；
Bayer image processing module converts images into satisfactory image for handling Bayer image；
Image filtering module is used to carry out noise filtering to by Bayer image processing module treated image；
Edge of the Image Edge-Detection module for image after the processing of detection image filter module, and will treated image
Data conversion is at the data for meeting Avalon Streaming interface specification；
Image storage module is for storing the image after edge detection；
Ethernet communication module is used to read the image data of image storage module storage, and image data is passed through ether
Net is sent to host computer；
NIOS II processor is used for the Collaborative Control of whole system.
Further, camera control module includes SCCB bus control unit and camera parameter register cell, camera ginseng
Number register cell is used to store the parameter used when setting camera register；SCCB bus control unit is used for logical with camera
Letter, is sent to camera for relevant parameter in camera parameter register cell, is configured to camera internal register.
Further, Bayer image processing module includes line count unit, shift register cell, picture element interpolation list
Member and color comparing unit；Line count unit receives the image data that camera sends over, and adds for each pixel of image
Upper line count signal；Image data is passed sequentially through the shift register that 3 length are picture traverse by shift register cell,
For next step interpolation processing；Picture element interpolation unit carries out interpolation processing to image data, is 10 Bayer by data bit width
Image becomes the RGB image that data bit width is 24, and wherein the most-significant byte of each pixel of RGB image saves red component, intermediate
8 preservation green components, least-significant byte save blue component；Color comparing unit by each pixel of RGB image with it is preset
Red, yellow, blue three-color threshold value is compared, and judges the color of each pixel, and the rgb value of red pixel is converted
It is stored in the most-significant byte of 24 data at the gray value that data bit width is 8, the rgb value of yellow pixel is converted into data bit
The gray value that width is 8 is stored in the centre 8 of 24 data, and it is 8 that the rgb value of blue pixel point, which is converted into data bit width,
Gray value be stored in least-significant byte.
Further, image filtering module includes median filter unit and gaussian filtering unit；At Bayer image module
What 24 data of each pixel for the image managed were divided into high, intermediate, low three eight bit datas passes through median filtering respectively
Unit and gaussian filtering unit, filter out the noise in image.
Further, Image Edge-Detection module includes Sobel edge detection unit, image buffer storage unit and Avalon
Streaming Bus Wrapper unit；By 24 data of each pixel for the image crossed by image filtering resume module
High, medium and low three eight, respectively by Sobel edge detection unit, detect corresponding edge；Image buffer storage unit, is used for
The caching of image data after edge detection；Avalon Streaming Bus Wrapper unit is used for the image data that will be cached, envelope
Dress up the data for meeting Avalon Streaming bus interface specifications.
Further, image storage module includes writing cell fifo, DDR3 read-write reading control unit, reading cell fifo；It writes
Cell fifo will treated that image data is buffered in FIFO by edge detection module, while realizing turning for data bit width
It changes, 4 24 bit image data is combined into 96 data；DDR3 read-write control unit is detecting to write in cell fifo have
When data, the data write in cell fifo are read, data are written into DDR3 memory, DDR3 read-write control unit receives reading
When cell fifo needs readout data signal, the data in DDR3 memory are read, DDR3 read-write control unit realizes figure simultaneously
As the inspection of data, when detecting that a frame image has loss of data, then the frame image is abandoned；Read cell fifo for cache from
The data read in DDR3 memory, while realizing the conversion of data bit width, 96 data are splitted into 4 24 data.
Further, ethernet communication module by Triple-Speed Ethernet IP kernel that Quartus II is provided with
And Avalon Streaming Bus Wrapper unit composition；Avalon Streaming Bus Wrapper module encapsulates data into symbol
Close the data mode of Avalon Streaming bus request；Triple-Speed Ethernet IP kernel is for receiving Avalon
The data received are added upper necessary information and are converted into meeting Ethernet transmission requirement by the data of Streaming format
Data are transferred to host computer by Ethernet.
Further, NIOS II processor module is used to filter camera control module, Bayer image processing module, image
Wave module, Image Edge-Detection module, ethernet communication module issue the corresponding command: posting camera parameter in camera control module
Relevant parameter carries out on-line tuning in storage unit；To three colors red, yellow, blue in Bayer image processing module judgement threshold value into
Row adjustment；Image filtering module and edge detection module are closed in starting；To the Triple- in ethernet communication module
Related register parameter in Speed Ethernet IP kernel is configured.
As shown in figure 3, a kind of acquisition method of the traffic sign video image based on FPGA, comprising the following steps:
Step 1, the camera parameter information in register cell is read and is sent to camera by SCCB bus control unit,
Camera is configured；
Step 2, camera data is handled image by Bayer image processing module；
Step 3, the processed image of Bayer image processing module is passed through into image filtering module, be filtered；
Step 4, edge detection module carries out edge detection to filtered image, while being accorded with by the way that stream compression to be melted into
Close the data flow of Avalon Streaming；
Step 5, the data received are stored in DDR3 by data memory module, and ethernet communication module is waited to read number
According to.
Step 6, the data being stored in DDR3 are sent to host computer by ethernet controller, are further located
Reason.
The present invention is described in detail combined with specific embodiments below.
Embodiment
In conjunction with Fig. 1, a kind of acquisition system of the traffic sign video image based on FPGA is carried out real using FPGA system
Existing, main hardware includes fpga chip, power module, DDR3 memory, PHY chip, CMOS camera, and fpga chip, which uses, is
The 10M50DAF484C6GES of 10 series of MAX of Altera；DDR3 particle is magnesium light IS46TR16640AL；PHY chip is
The 88E1111 chip of Marvell；CMOS camera using OmniVision OV8865 camera module；
In conjunction with Fig. 2, the module that the present embodiment uses on FPGA mainly has camera control module, Bayer image procossing mould
Block, image filtering module, Image Edge-Detection module, image storage module, ethernet communication module and NIOS II processor.
In conjunction with Fig. 4, a kind of acquisition method of the traffic sign video image based on FPGA, specific implementation step is as follows:
Step 1, NIOS II controls the parameter in SCCB bus control unit reading camera parameter register cell, by phase
It closes parameter and is sent to camera, Initialize installation is carried out to camera, including the clock frequency that camera internal uses, the output figure of camera
The size of piece is 800*600, and image output speed is that 60 frames are per second and the time for exposure of image, white balance parameter.
Step 2, Bayer image being converted to RGB image, the picture element signal that camera is passed to adds line count signal,
The shift register that three length are picture traverse is recycled to carry out shifting cache to image.By linear interpolation algorithm to image
Interpolation is carried out, monochromatic pixel is converted to the pixel of tri- color of RGB, is convenient for subsequent processing.
Wherein one pixel column counter of the every input of line count module adds one, in the decline of image line useful signal
Edge, column counter is set to zero, while linage-counter adds one, is set to data line column counter in picture frame useful signal failing edge
Zero.
Picture element interpolation unit judges the color of the pixel according to the ranks number of each pixel, with point same color
RGB component takes the point value, other components take the mean value of same color component in the matrix of 3X3.
Step 3, each pixel of RGB image is fed respectively into color comparing unit, if red component is than green
And blue component is big by 20, then is determined as red, is determined as blue point if blue component is bigger by 3 than green and red component
Amount, if red component than blue component big 30 and green component big 30 than blue component if be determined as yellow.If it is it is red,
One of yellow, Lan Sanse, then be converted into corresponding gray value for the color, will be determined as the red corresponding ash of pixel
Angle value is placed on the high eight-bit of data, remaining each point zero setting；By the corresponding gray value of the pixel for being determined as yellow be placed in 8 its
Remaining each point zero setting；The corresponding gray value of pixel for being determined as blue is placed on least-significant byte, remaining each position zero.If not it is red,
Everybody of 24 data bit is then set to zero by one of yellow, Lan Sanse.
Step 4, image data is cached using the shift register that three length are picture traverse, then by image
High, medium and low three 8 of 24 data of each pixel are respectively fed to corresponding median filter unit and gaussian filtering unit to figure
As being filtered；
Median filtering first carries out three column and sorts that column maximum value, low level are minimum value thus for each column high-order respectively.Three column rows
After the completion of sequence, then each row is ranked up, by the intermediate value and the third line of the first row maximum value and the second row after sequence
Minimum value is ranked up.Obtained intermediate value is required intermediate value.This process needs three clock cycle.
Gaussian filtering will be required 8 pixels of current pixel point and surrounding and Gaussian template multiplication, then will
9 obtained product additions, the as value of the gaussian filtering.
Step 5, by high, medium and low three 8 of the image data by filtering processing, it is respectively fed to Image Edge-Detection
Module detects image border, and by treated, image data passes through data buffer storage unit, and cache unit uses asynchronous
FIFO is realized, the conversion that data are carried out with clock domain is realized, and convenient for communicating data with memory control module, by data
It is converted into meeting the data of Avalon Streaming bus protocol, be transmitted.
1) displacement is carried out to the data after edge detection using the shift register that three length are a line picture traverse to delay
It deposits, takes three rows three to arrange the result needed that is multiplied with Sobel template the image data after displacement.
2) image data is converted into meeting the data of Avalon Streaming agreement, needs to add a data starting
Position, indicates the beginning of a frame data, and a stop bits indicates the end of a frame data.Forward pass is worked as in a data significance bit, expression
Defeated data are effective.And a receiving end prepares position, for indicating that receiving module is ready to receive data
Step 6, it will be stored by pretreated data, first image data is buffered in and is write in FIFO, when caching
After image data reaches certain amount, image data is written in DDR3, in order to accelerate storage efficiency, using prominent when storing data
Hair mode, data, which are read, equally uses burst mode, will read image data and be temporarily stored in reading cell fifo, convenient for communicating below
Reading of the module to data.
1) conversion that cell fifo realizes the caching and data bit width of data is write, by 4 24 data conversions at 1 96
Position data make the requirement of data fit write-in DDR3 register.
2) DDR3 read-write control unit is low by write address when detecting a frame end signal during data are written
20 position zeros, a high position remain unchanged.Signal, which will be write complete, sets height simultaneously.
3) for DDR3 read-write control unit when receiving reading FIFO read data request, judgement runs through whether signal is height,
If it is height, without read operation, otherwise, data are read, data are stored in and read to read in FIFO convenient for ethernet control module
It takes.The reading for completing a frame data will run through signal and set height, and by low 20 position zero of read address, a high position is remained unchanged.
4) when it is simultaneously high that signal is completed in reading and writing, signal removal is completed into read-write.Reading, writing address is exchanged simultaneously.
5) during write operation, if detecting that a frame data have the case where loss, the frame data, i.e. reading and writing are abandoned
Address does not exchange, while will write complete signal clearing.
Step 7, the image data read from memory module conversion is first met Triple-Speed by ethernet communication module
The data for the Avalon Streaming data format that Ethernet IP kernel requires, are sent the data to upper by Ethernet
Machine.
In the present embodiment, the acquisition method of the traffic sign video image based on FPGA has consumed about more than 14100
Storage resource in the piece of logic unit, more than 8000 a register resources and 14000 multibytes is 800* in acquisition image pixel
480, under the Bayer image condition that data width is 10, it is per second that the received rate of image has reached 60 frames.
Claims (9)
1. a kind of acquisition system of the traffic sign video image based on FPGA, which is characterized in that by camera control module,
Bayer image processing module, image filtering module, Image Edge-Detection module, image storage module, ethernet communication module and
NIOS II processor composition；It is realized using FPGA hardware logic with upper module, it then follows Avalon Memory-Mapped interface rule
Model, Avalon Streaming interface specification and SCCB camera control bus specification；
Camera control module is for being configured camera parameter；
Bayer image processing module converts images into satisfactory image for handling Bayer image；
Image filtering module is used to carry out noise filtering to by Bayer image processing module treated image；
Edge of the Image Edge-Detection module for image after the processing of detection image filter module, and will treated image data
It is converted into meeting the data of Avalon Streaming interface specification；
Image storage module is for storing the image after edge detection；
Ethernet communication module is used to read the image data of image storage module storage, and image data is sent out by Ethernet
Give host computer；
NIOS II processor is used for the Collaborative Control of whole system.
2. the acquisition system of the traffic sign video image according to claim 1 based on FPGA, which is characterized in that camera
Control module includes SCCB bus control unit and camera parameter register cell, and camera parameter register cell is set for storing
The parameter used when setting camera register；SCCB bus control unit with camera for communicating, by camera parameter register cell
Middle relevant parameter is sent to camera, is configured to camera internal register.
3. the acquisition system of the traffic sign video image according to claim 1 based on FPGA, which is characterized in that
Bayer image processing module includes line count unit, shift register cell, picture element interpolation unit and color comparing unit；
Line count unit receives the image data that camera sends over, and is that each pixel of image adds line count signal；It moves
Image data is passed sequentially through the shift register that 3 length are picture traverse by bit register unit, at next step interpolation
Reason；Picture element interpolation unit carries out interpolation processing to image data, is that 10 Bayer images become data bit width by data bit width
For 24 RGB images, wherein the most-significant byte of each pixel of RGB image saves red component, intermediate 8 preservation green components,
Least-significant byte saves blue component；Color comparing unit is by each pixel of RGB image and preset red, yellow, blue three-color
Threshold value is compared, and judges the color of each pixel, and it is 8 that the rgb value of red pixel, which is converted into data bit width,
Gray value is stored in the most-significant byte of 24 data, and the rgb value of yellow pixel is converted into the gray value that data bit width is 8 and is protected
There are the centres 8 of 24 data, and the rgb value of blue pixel point is converted into the gray value that data bit width is 8 and is stored in low 8
Position.
4. the acquisition system of the traffic sign video image according to claim 1 based on FPGA, which is characterized in that image
Filter module includes median filter unit and gaussian filtering unit；By each pixel of the processed image of Bayer image module
24 data of point be divided into high, intermediate, low three eight bit datas respectively by median filter unit and gaussian filtering unit, filter
Except the noise in image.
5. the acquisition system of the traffic sign video image according to claim 1 based on FPGA, which is characterized in that image
Edge detection module includes Sobel edge detection unit, image buffer storage unit and Avalon Streaming Bus Wrapper unit；
High, medium and low three eight of 24 data of each pixel for the image crossed by image filtering resume module are led to respectively
Sobel edge detection unit is crossed, detects corresponding edge；Image buffer storage unit, for after edge detection image data it is slow
It deposits；Avalon Streaming Bus Wrapper unit is used for the image data that will be cached, and is packaged into and meets Avalon
The data of Streaming bus interface specifications.
6. the acquisition system of the traffic sign video image according to claim 1 based on FPGA, which is characterized in that image
Memory module includes writing cell fifo, DDR3 read-write reading control unit, reading cell fifo；Edge detection will be passed through by writing cell fifo
Image data after resume module is buffered in FIFO, while realizing the conversion of data bit width, combines 4 24 bit image data
At 96 data；DDR3 read-write control unit detect write have data in cell fifo when, reading write in cell fifo
Data, be written data into DDR3 memory, DDR3 read-write control unit, which receives, to be read cell fifo and need readout data signal
When, the data in DDR3 memory are read, DDR3 read-write control unit realizes the inspection of image data simultaneously, detects a frame figure
As when having loss of data, then the frame image being abandoned；Read cell fifo for caching the data read from DDR3 memory, together
96 data are splitted into 4 24 data by the conversion of Shi Shixian data bit width.
7. the acquisition system of the traffic sign video image according to claim 1 based on FPGA, which is characterized in that ether
Network Communication module is total by the Quartus II Triple-Speed Ethernet IP kernel provided and Avalon Streaming
Line encapsulation unit composition；Avalon Streaming Bus Wrapper module encapsulates data into that meet Avalon Streaming total
The data mode that line requires；Triple-Speed Ethernet IP kernel is used to receive the number of Avalon Streaming format
According to by the data received addition, above necessary information is converted into meeting the data of Ethernet transmission requirement, is passed by Ethernet
It is defeated by host computer.
8. the acquisition system of the traffic sign video image according to claim 1 based on FPGA, which is characterized in that NIOS
II processor module is used for camera control module, Bayer image processing module, image filtering module, Image Edge-Detection mould
Block, ethernet communication module issue the corresponding command: in camera control module in camera parameter register cell relevant parameter into
Row on-line tuning；The threshold value of three colors red, yellow, blue in Bayer image processing module judgement is adjusted；Image is closed in starting
Filter module and edge detection module；To the phase in the Triple-Speed Ethernet IP kernel in ethernet communication module
Register parameters are closed to be configured.
9. a kind of acquisition method of the acquisition system based on the traffic sign video image described in claim 1 based on FPGA,
It is characterized in that, comprising the following steps:
Step 1, camera parameter information is sent to camera, camera is configured；
Step 2, camera data is handled image by Bayer image processing module；
Step 3, the processed image of Bayer image processing module is passed through into image filtering module, be filtered；
Step 4, edge detection module carries out edge detection to filtered image, while by meeting stream compression chemical conversion
The data flow of Avalon Streaming；
Step 5, the data received are stored in DDR3 by data memory module, and ethernet communication module is waited to read data；
Step 6, the data being stored in DDR3 are sent to host computer by ethernet controller.
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