CN106294234B - A kind of data transmission method and device - Google Patents
A kind of data transmission method and device Download PDFInfo
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- CN106294234B CN106294234B CN201610619878.2A CN201610619878A CN106294234B CN 106294234 B CN106294234 B CN 106294234B CN 201610619878 A CN201610619878 A CN 201610619878A CN 106294234 B CN106294234 B CN 106294234B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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Abstract
The embodiment of the invention discloses a kind of data transmission method and device, the method includes：First data of the first data bit width that bit wide matching module receiving sensor is sent；First data conversion is sent to first in first out cache module by the bit wide matching module at the second data of the second data bit width, and by second data；Second data are sent to first memory by the first in first out cache module with preset data transmission rate.The second data that the first data of the first data bit width are converted to the second data bit width are realized by bit wide matching module, and the second data are used for transmission to first memory by the way that preset data transmission rate is arranged in first in first out cache module, so that the processing chip need not occupy block storage when carrying out data transmission, block storage resource is saved, data-handling efficiency is improved.
Description
Technical field
The present invention relates to the communications fields, and in particular to a kind of data transmission method and device.
Background technology
With the development of science and technology, image processing techniques is also increasingly being applied to various fields so as to image procossing
Technology also proposed increasingly higher demands, for example, when Computer Vision to be applied to the industrial circle of pipeline system, need
Video image is handled in real time, and processing has very high requirement to video to embedded system in real time.
Currently, since image processing algorithm is complex, the flowing water of pixel-by-pixel can not be carried out to image algorithm
Line operates, so needing to cache full frame image data, but carries out caching to image and needs to carry out using on processor
Fifo is cached.For example, working as use site programmable gate array (Field-Programmable Gate Array, abbreviation FPGA)
When being cached, general block random access memory (Block Random-Access Memory, abbreviation using on FPGA
BRAM fifo cachings) are realized, but since BRAM resources are limited so that FPGA will be occupied by carrying out video image caching using BRAM
The upper resource applied to image procossing is reduced, it would be possible to cause image processing efficiency to reduce, or use possesses larger BRAM
FPGA resources costs will be caused to greatly improve.
Invention content
An embodiment of the present invention provides a kind of data transmission method and devices, to utilize the logical resource on FPGA
The fifo cachings for realizing image, save BRAM resources, improve data-handling efficiency.
In a first aspect, the embodiment of the present invention provides a kind of data transmission method, including：
First data of the first data bit width that bit wide matching module receiving sensor is sent；
The bit wide matching module by first data conversion at the second data of the second data bit width, and by described
Two data are sent to first in first out cache module；
Second data are sent to first memory by the first in first out cache module with preset data transmission rate,
The preset data transmission rate is that the data for making the bit wide matching module keep clock synchronous with the first memory pass
Defeated rate, the first in first out cache module logic-based storage unit.
In a first aspect, the embodiment of the present invention provides a kind of data transmission device, including：
Bit wide matching module, the first data for the first data bit width that receiving sensor is sent；
The bit wide matching module is additionally operable to the second data at the second data bit width by first data conversion, and
Second data are sent to first in first out cache module；
The first in first out cache module is deposited for second data to be sent to first with preset data transmission rate
Reservoir, the preset data transmission rate are the number for keeping the bit wide matching module synchronous with first memory holding clock
According to transmission rate, the first in first out cache module logic-based storage unit.
As can be seen that in the technical solution that the embodiment of the present invention is provided, what bit wide matching module receiving sensor was sent
First data of the first data bit width；Then bit wide matching module is again by first data conversion at the second of the second data bit width
Data, and second data are sent to first in first out cache module；Then first in first out cache module by the second data with pre-
If message transmission rate is sent to first memory, the preset data transmission rate be make the bit wide matching module with it is described
First memory keeps the message transmission rate that clock synchronizes, the first in first out cache module logic-based storage unit.It is logical
It crosses bit wide matching module and realizes the second data that the first data of the first data bit width are converted to the second data bit width, Yi Jitong
It crosses and is used for transmission the second data to first memory in first in first out cache module setting preset data transmission rate, so that
The processing chip need not occupy block storage when carrying out data transmission, and save block storage resource, improve data-handling efficiency.
Description of the drawings
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Obtain other attached drawings according to these attached drawings.
Fig. 1 is a kind of first embodiment flow diagram of data transmission method provided in an embodiment of the present invention；
Fig. 2 is a kind of data flow schematic diagram based on FPGA of data transmission method provided in an embodiment of the present invention；
Fig. 3 is a kind of second embodiment flow diagram of data transmission method provided in an embodiment of the present invention；
Fig. 4 is a kind of structural schematic diagram of the first embodiment of data transmission device provided in an embodiment of the present invention；
Fig. 5 is a kind of structural schematic diagram of the second embodiment of data transmission device provided in an embodiment of the present invention.
Specific implementation mode
An embodiment of the present invention provides a kind of data transmission method and devices, to utilize the logical resource on FPGA
The fifo cachings for realizing image, save BRAM resources, improve data-handling efficiency.
In order to enable those skilled in the art to better understand the solution of the present invention, below in conjunction in the embodiment of the present invention
Attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is only
The embodiment of a part of the invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill people
The every other embodiment that member is obtained without making creative work should all belong to the model that the present invention protects
It encloses.
Term " first ", " second " and " third " in description and claims of this specification and above-mentioned attached drawing etc. is
For distinguishing different objects, not for description particular order.In addition, term " comprising " and their any deformations, it is intended that
Non-exclusive include in covering.Such as process, method, system, product or the equipment for containing series of steps or unit do not have
It is defined in the step of having listed or unit, but further includes the steps that optionally not listing or unit, or further include optionally
For the intrinsic other steps of these processes, method, product or equipment or unit.
The embodiment of the present invention provides a kind of data transmission method, including：
First data of the first data bit width that bit wide matching module receiving sensor is sent；
The bit wide matching module by first data conversion at the second data of the second data bit width, and by described
Two data are sent to first in first out cache module；
It is same that second data are sent to Double Data Rate by the first in first out cache module with preset data transmission rate
Dynamic RAM DDR is walked, the preset data transmission rate is that the bit wide matching module is made to keep clock with the DDR
Synchronous message transmission rate.
Hereinafter, the part term in the application is explained, in order to those skilled in the art understand that.It needs
It is bright, in the embodiment referred in full herein, the term for FPGA is used, but the present invention is not limited to be based on FPGA
It is realized.
The embodiment of the present invention carry be related to based on FPGA be a kind of embeded processor can be used for Computer Vision,
When carrying out embedded video processing exploitation using FPGA, the video data stream of camera output will often be realized such as inside FPGA
Under several flows：Sampling, pretreatment, caching and output etc..In certain application scenarios, since image processing algorithm is complex,
The pile line operation that pixel-by-pixel can not be carried out to image data, therefore, it is necessary to rattle to full frame image data
Caching, i.e., first cache the first frame data, when first frame data transmission is completed, the first frame data of start to process, together
When, start to cache the second frame data.Ensure before the second frame data are transmitted, handled the first frame data, so repeats
Operation.However, the cache resources of FPGA on pieces are generally very limited, as block RAM (Block RAM, abbreviation BRAM, FPGA on piece
A kind of integrated data storage cell) it is difficult to meet while caching the image of two frame VGA sizes, therefore, traditional way is：
First by image buffer storage to external memory, such as Double Data Rate synchronous DRAM (Double Data Rate, letter
Claim DDR) memory, it opens up two block diagram image spaces in DDR and carries out ping-pong buffer, secondly, then the frame image data on DDR is led to
It crosses dma mode and is transmitted on piece BRAM processing.For example, there is 3 frame consecutive images：First image, the second image and third figure
Picture has two piece of first memory space and the second memory space, BRAM to have a block diagram image storage space on DDR：Third memory space.
When the first image arrives, first by the first image buffer storage to the first memory space, when the first memory space receives complete
After one image, the first image is exported from the first memory space to third memory space and is handled.And in this process, the
Two images arrive, at this point, due in the first memory space data may not yet be completely transferred in third memory space, because
This, by the second image buffer storage to the second memory space.When receiving complete image data in the second memory space, third image is
It will arrive, now it is necessary to ensure that the image procossing in third memory space has had been processed, otherwise will carry out frame losing behaviour
Make.Then, the data of the second memory space import third memory space, and third image is so recycled into the first memory space.
During this, we have used DDR controller twice.And DDR controller in local side and bus end due to using different frequencies
The clock of rate, phase needs to carry out cross clock domain processing, and improves efficiency of transmission using DMA, and common practices is to utilize herein
BRAM opens up a spatial cache, for solving the problems such as cross clock domain and DMA transfer bit wide match.DMA transfer bit wide matches
Be due to sensor seneor output data formats be 8bit, and the input bit wide of DMA minimum be 32bit, 8bit will be inputted
Data are merged into 32bit in fifo, and simplest method is realized using BRAM.Certainly, the fifo realized using BRAM
At least to occupy a BRAM resource, i.e. 18kb.If input and output are all realized using BRAM, at least to use
The BRAM resources of 36kb.For this purpose, the present invention proposes a kind of new method, the distributed RAM on FPGA is utilized
(Distribute RAM), i.e. distribution RAM and shift unit realize the function of BRAM FIFO, at the same solve cross clock domain and
The problem of bit wide matches.
In embodiments of the present invention, since Distribute RAM are by the minimum logic unit SLICE groups on FPGA
Logic storage unit made of conjunction.For BRAM, maximum advantage is exactly that how many spatial cache needed, and just how much is occupancy
Logical resource, rather than BRAM, a minimum storage unit is exactly 18kb.Therefore, it is saved by occupying some logical resources
Valuable BRAM resources are saved, are the starting points of the present invention.
Embodiments herein is described below in conjunction with the accompanying drawings, method provided in an embodiment of the present invention is based on FPGA cores
What piece was realized, which can be programmed by user in the processing chip.It is this hair referring first to Fig. 1, Fig. 1
A kind of first embodiment flow diagram for data transmission method that bright embodiment provides.As shown in Figure 1, the embodiment of the present invention carries
The data transmission method of confession includes the following steps：
First data of the first data bit width that S101, bit wide matching module receiving sensor are sent.
Wherein, bit wide matching module refers to that can be modified to the data bit width for inputting data therein, so that output
Data meet need data bit width.
Wherein, data bit width refers to memory or the primary data volume that can be transmitted of video memory, in embodiments of the present invention, the data
Bit wide can be 8bit, 16bit, 32bit or 64bit etc..
Wherein, sensor refers to for getting the first data from the external world and the first data transmission to bit wide being matched mould
The device of block.
Optionally, in some possible embodiments of the present invention, bit wide matching module can pass through shift LD
Device is realized, can also be to be realized by other hardware circuit modules.
Optionally, in some possible embodiments of the present invention, which can be CCD image sensor
(Charge-coupled Device), CMOS etc., which are used to be transmitted to bit wide to the image data that video camera is taken, matches mould
Block.
Optionally, in other possible embodiments of the present invention, which may be photoelectric sensor, use
It is transmitted to bit wide matching module in the collected optical signal of the sensor is converted to electrical signal data.
It is appreciated that the type of the first data is related to the sensor, can be image data, or other numbers
According to.
Preferably, in embodiments of the present invention, which is fpga chip, then the bit wide matching module is that displacement is posted
Storage.
Preferably, which is ccd image sensor, then first data are image data.
S102, the bit wide matching module by first data conversion at the second data of the second data bit width, and will
Second data are sent to first in first out cache module.
Wherein, the second data refer to that but data bit width identical as the data type of the first data and data content is different
Data.
Wherein, first in first out cache module refers to fifo cache modules, refers in bit wide matching module and second memory
Between a transmission channel, will be from the data transmission that bit wide matching module inputs to second memory.
Optionally, in some possible embodiments of the present invention, which can be carried out by RAM
It realizes.
Preferably, if the processing chip is FPGA, which is Distribute RAM.
For example, in the example of the present invention, if the first data bit width is 8bit, the second data bit width is
The data conversion of 8bit can be then forwarded to Distribute RAM by 16bit, shift register at the data of 16bit.
Second data are sent to first with preset data transmission rate and deposited by S103, the first in first out cache module
Reservoir, the preset data transmission rate are the number for keeping the bit wide matching module synchronous with first memory holding clock
According to transmission rate.
Wherein, first memory refers to the memory for the second data to be further processed.
Preferably, in some possible embodiments of the present invention, if the processing chip is FPGA, which is
Double Data Rate synchronous DRAM DDR.
Specifically, the second data can pass through direct memory access (Direct Memory from Distribute RAM
Access, abbreviation DMA) it is transmitted to DDR.
Preferably, if the first data are vedio data, the second data are also vedio data.
In embodiments of the present invention, since processing chip needs the first data received from sensor to be sent to first
Memory is further processed, and the data bit width of the first data by being received from sensor and first memory institute
The data bit width that can be handled is inconsistent, so needing the first data conversion to first data bit width at the second data bit width
Second data can ensure the correct of data transmission procedure；On the other hand, due to giving first in first out cache module input data
Bit wide matching module and the first memory of first in first out cache module output data work schedule needs be consistent, and
Since bit wide matching module is controlled from first memory by different work schedules, so the first data cache mould in first in first out
Block when transmitting needs that certain message transmission rate is arranged, so that being passed in the data of first in first out cache module in the first data
The defeated time meets so that bit wide matching module is consistent with the clock of first memory.
Preferably, in some possible embodiments of the present invention, Distribute RAM are by the second image data with pre-
If transmission rate is by DMA transfer to DDR, so that Distribute RAM and DDR is protected when handling the second image data
Clock is demonstrate,proved to synchronize.
As can be seen that in the scheme of the present embodiment, the first data bit width of bit wide matching module receiving sensor transmission
First data；Then bit wide matching module is again by first data conversion at the second data of the second data bit width, and by this
Two data are sent to first in first out cache module；Then first in first out cache module by the second data with preset data transmission rate
It is sent to first memory, the preset data transmission rate is that the bit wide matching module is made to be kept with the first memory
The message transmission rate that clock synchronizes, the first in first out cache module logic-based storage unit.Pass through bit wide matching module
Realize the second data that the first data of the first data bit width are converted to the second data bit width, and by slow in first in first out
Storing module setting preset data transmission rate be used for transmission the second data to first memory so that the processing chip into
Block storage need not be occupied when row data transmission, saves block storage resource, improve data-handling efficiency.
Optionally, in some possible embodiments of the present invention, the first in first out cache module is by described second
After image data is sent to first memory with preset data transmission rate, the method further includes：
Second image data is transmitted to second memory by the first memory, so that second memory is to described
Second image data is handled.
Preferably, in some possible embodiments of the present invention, if the processing chip is FPGA, the first memory
It is Double Data Rate synchronous DRAM DDR, DDR after receiving image data, which is transmitted to BRAM
In, so that BRAM carries out the image data processing of image algorithm.
Optionally, in some possible embodiments of the present invention, the bit wide matching module is shift register, institute
The wide matching module of rheme by described first image data conversion at the second image data of the second data bit width, including：
If first data bit width be less than second data bit width, the shift register by first data into
Row logical shift is simultaneously combined to be converted into second image data；
If first data bit width be more than second data bit width, the shift register by first data into
Row is split and logical shift is to be converted into second image data.
Preferably, when deserving the first data bit width less than the second data bit width, which is the first data bit
Wide multiple.
Preferably, when deserving the second data bit width less than the first data bit width, which is the second data bit
Wide multiple.
For example, in the example of the present invention, if using shift register by 8 data conversion positions 16
When, first 8 data are subjected to displacement first with shift register and are placed in the most-significant bytes of 16 data, then again will under
One 8 data are placed in the least-significant byte of 16 data, to realize 28 data conversions into 1 16 data.
For example, in another example of the present invention, if using shift register by 16 data conversions at 8
When, the most-significant byte data of 16 data can be set to one 8 data, then the least-significant byte of 16 data is placed in one again
A data.
It is appreciated that since shift register can shift data, so as to pass through the data bit in input
When width is less than the data bit width of output, it two continuous data shifted and are combined can be realized data bit width from low level
Width is converted to high-bit width；And when the data bit width of input is more than the data bit width of output, the data of the input are torn open
It after point, then shifts again, can be achieved high-bit width being converted to low-bit width.
For example, in the example of the present invention, by taking zynq Series FPGAs an example, zynq is the collection that xilinx is released
The embedded soc products that FPGA and ARM is integrated, high, the small embedded development field especially suitable for integrated level.zynq
Logical resource part is referred to as PL, and ARM is known as PS.Data are carried out between the modules inside PL or between PL and PS
Exchange is completed by built-in AXI buses.It is a kind of data transmission method provided in an embodiment of the present invention referring to Fig. 2, Fig. 2
The data flow schematic diagram based on FPGA.
In this embodiment, bit wide matching module is shift register, and first in first out cache module is Distribute
RAM, first memory are Double Data Rate synchronous DRAM DDR, and the second memory is block random access memory
Device BRAM.Sensor is ccd image sensor.
In implementation column of the present invention, shift register obtains the first image data from ccd image sensor first, then again
By the image data by DMA transfer to DDR, which is transmitted to BRAM and carries out image procossing by last DDR.
In embodiments of the present invention, since ccd image sensor institute the image collected data are generally 8bit, and DMA
Transmission bit wide when transmission is generally 64bit, and the frequency dividing of pixel clocks 8 of ccd image sensor obtains, and DMA is system
The AXI work clocks of setting are 100MHz in the design.So the image data firstly the need of the 8bit is converted into 64bit's
Image data, then the image data of the 64bit is transmitted to by Distribute RAM with certain rate, then pass through DMA transfer
To DDR so that CCD clocks are consistent with DMA work clocks.
Further, the depth depth of the Distribute RAM should ensure that minimum energy two row data of cache image.It is false
If piece image resolution ratio is 640x480, i.e., picture traverse is 640.For the data that output format is yuv422, a line
Data are just 640x2=1280 8bit data, and therefore, 64bit depth needed for data line is 1280/8=160.Two rows are
It is 320.For convenience of calculating, it is assumed that 64bit fifo depth is 512.
Further, when the data in 64bit fifo are more than or equal to the data of a line, we just initiate a DMA
Transmission.Data line is transmitted to DDR by the transmission.When picture altitude is 480, need to initiate 480 DMA transfers, DDR altogether
In can receive the complete image of a width.
So far, in the case where no BRAM is participated in, we are realized by shift register, Distribute RAM, DMA
One-frame video data to realize makes full use of distribution RAM resources on FPGA from the process for being carried to DDR is received,
The purpose of BRAM resources is saved, image processing efficiency is improved.
Optionally, in another example of the present invention, when the only data that image data is carried to BRAM from DDR again
Inverted running process, implementation method is consistent, to realize the normal communication in FPGA of image data.
For the ease of more fully understanding and implementing the said program of the embodiment of the present invention, it will illustrate several specifically answer below
It is illustrated with scene.
It is a kind of second embodiment flow signal of data transmission method provided in an embodiment of the present invention referring to Fig. 3, Fig. 3
Figure.It, can be with the detailed description in reference chart 2, herein with the same or similar content of method shown in Fig. 2 in method shown in Fig. 3
It repeats no more.As shown in figure 3, data transmission method provided in an embodiment of the present invention includes the following steps：
First image data of the first data bit width that S301, shift register receiving sensor are sent.
In embodiments of the present invention, which can be 8bit, 16bit, 32bit or 64bit etc..
Preferably, which is ccd image sensor.
S302, shift register by described first image data conversion at the second image data of the second data bit width, and
Second image data is sent to distributed RAM.
Second image data is sent to DDR by S303, distribution RAM with preset data transmission rate by DMA, this is default
Message transmission rate is the message transmission rate for keeping shift register synchronous with DMA holding clocks.
Second image data is transmitted to BRAM by S304, DDR, so that BRAM pairs of the second image data is handled.
As can be seen that in the scheme of the present embodiment, the first data bit width of bit wide matching module receiving sensor transmission
First data；Then bit wide matching module is again by first data conversion at the second data of the second data bit width, and by this
Two data are sent to first in first out cache module；Then first in first out cache module by the second data with preset data transmission rate
It is sent to first memory, the preset data transmission rate is that the bit wide matching module is made to be kept with the first memory
The message transmission rate that clock synchronizes, the first in first out cache module logic-based storage unit.Pass through bit wide matching module
Realize the second data that the first data of the first data bit width are converted to the second data bit width, and by slow in first in first out
Storing module setting preset data transmission rate be used for transmission the second data to first memory so that the processing chip into
Block storage need not be occupied when row data transmission, saves block storage resource, improve data-handling efficiency.
The embodiment of the present invention also provides a kind of data transmission device, including：
Bit wide matching module, the first data for the first data bit width that receiving sensor is sent；
The bit wide matching module is additionally operable to the second data at the second data bit width by first data conversion, and
Second data are sent to first in first out cache module；
The first in first out cache module is deposited for second data to be sent to first with preset data transmission rate
Reservoir, the preset data transmission rate are the number for keeping the bit wide matching module synchronous with first memory holding clock
According to transmission rate, the first in first out cache module logic-based storage unit.
Specifically, Fig. 4 is referred to, Fig. 4 is a kind of first embodiment of data transmission device provided in an embodiment of the present invention
Structural schematic diagram, for realizing data transmission method disclosed by the embodiments of the present invention.Wherein, as shown in figure 3, the present invention is implemented
Example provide a kind of data transmission device 400 may include：
Bit wide matching module 410 and first in first out cache module 420.
Wherein, bit wide matching module 410, the first data for the first data bit width that receiving sensor is sent.
Wherein, bit wide matching module 410 refers to that can be modified to the data bit width for inputting data therein, so that defeated
The data gone out meet the data bit width needed.
Wherein, data bit width refers to memory or the primary data volume that can be transmitted of video memory, in embodiments of the present invention, the data
Bit wide can be 8bit, 16bit, 32bit or 64bit etc..
Wherein, sensor refers to for getting the first data from the external world and the first data transmission to bit wide being matched mould
The device of block.
Optionally, in some possible embodiments of the present invention, bit wide matching module can pass through shift LD
Device is realized, can also be to be realized by other hardware circuit modules.
Optionally, in some possible embodiments of the present invention, which can be CCD image sensor
(Charge-coupled Device), for being transmitted to bit wide matching module to the image data that video camera is taken.
Optionally, in other possible embodiments of the present invention, which may be photoelectric sensor, use
It is transmitted to bit wide matching module in the collected optical signal of the sensor is converted to electrical signal data.
It is appreciated that the type of the first data is related to the sensor, can be image data, or other numbers
According to.
Preferably, in embodiments of the present invention, which is fpga chip, then the bit wide matching module is that displacement is posted
Storage.
Preferably, which is ccd image sensor, then first data are image data.
The bit wide matching module 410 is additionally operable to the second data at the second data bit width by first data conversion,
And second data are sent to first in first out cache module.
Wherein, the second data refer to that but data bit width identical as the data type of the first data and data content is different
Data.
Wherein, first in first out cache module refers to fifo cache modules, refers in bit wide matching module and second memory
Between a transmission channel, will be from the data transmission that bit wide matching module inputs to second memory.
Optionally, in some possible embodiments of the present invention, which can be carried out by RAM
It realizes.
Preferably, if the processing chip is FPGA, which is Distribute RAM.
For example, in the example of the present invention, if the first data bit width is 8bit, the second data bit width is
The data conversion of 8bit can be then forwarded to Distribute RAM by 16bit, shift register at the data of 16bit.
The first in first out cache module 420, for second data to be sent to preset data transmission rate
One memory, the preset data transmission rate are that the bit wide matching module is made to keep clock synchronous with the first memory
Message transmission rate, the first in first out cache module logic-based storage unit.
Wherein, first memory refers to the memory for the second data to be further processed.
Preferably, in some possible embodiments of the present invention, if the processing chip is FPGA, which is
Double Data Rate synchronous DRAM DDR.
Specifically, the second data can pass through direct memory access (Direct Memory from Distribute RAM
Access, abbreviation DMA) it is transmitted to DDR.
Preferably, if the first data are vedio data, the second data are also vedio data.
In embodiments of the present invention, since processing chip needs the first data received from sensor to be sent to first
Memory is further processed, and the data bit width of the first data by being received from sensor and first memory institute
The data bit width that can be handled is inconsistent, so needing the first data conversion to first data bit width at the second data bit width
Second data can ensure the correct of data transmission procedure；On the other hand, due to giving first in first out cache module input data
Bit wide matching module and the first memory of first in first out cache module output data work schedule needs be consistent, and
Since bit wide matching module is controlled from first memory by different work schedules, so the first data cache mould in first in first out
Block when transmitting needs that certain message transmission rate is arranged, so that being passed in the data of first in first out cache module in the first data
The defeated time meets so that bit wide matching module is consistent with the clock of first memory.
Preferably, in some possible embodiments of the present invention, Distribute RAM are by the second image data with pre-
If transmission rate is by DMA transfer to DDR, so that Distribute RAM and DDR is protected when handling the second image data
Clock is demonstrate,proved to synchronize.
As can be seen that in the scheme of the present embodiment, the first data bit width of bit wide matching module receiving sensor transmission
First data；Then bit wide matching module is again by first data conversion at the second data of the second data bit width, and by this
Two data are sent to first in first out cache module；Then first in first out cache module by the second data with preset data transmission rate
It is sent to first memory, the preset data transmission rate is that the bit wide matching module is made to be kept with the first memory
The message transmission rate that clock synchronizes, the first in first out cache module logic-based storage unit.Pass through bit wide matching module
Realize the second data that the first data of the first data bit width are converted to the second data bit width, and by slow in first in first out
Storing module setting preset data transmission rate be used for transmission the second data to first memory so that the processing chip into
Block storage need not be occupied when row data transmission, saves block storage resource, improve data-handling efficiency.
In the present embodiment, data transmission device 400 is presented in the form of unit.Here " unit " can refer to spy
Determine application integrated circuit (application-specific integrated circuit, ASIC), executes one or more soft
The processor and memory of part or firmware program, integrated logic circuit and/or other the device of above-mentioned function can be provided.
It is understood that the function of each functional unit of the data transmission device 400 of the present embodiment can be according to above-mentioned side
Method specific implementation in method embodiment, specific implementation process are referred to the associated description of above method embodiment, herein
It repeats no more.
It is a kind of structural representation of the second embodiment of data transmission device provided in an embodiment of the present invention referring to Fig. 5, Fig. 5
Figure, for realizing data transmission method disclosed by the embodiments of the present invention.Wherein, data transmission device as shown in Figure 5 is by Fig. 4
Shown in data transmission device optimize.Data transmission device shown in fig. 5 is in addition to including that data shown in Fig. 4 pass
Except the module of defeated device, also following extension：
Optionally, in some possible embodiments of the present invention, described device further includes：
Transmission module 530, for second image data to be transmitted to first memory, so that the first memory
Second image data is handled.
Preferably, in some possible embodiments of the present invention, if the processing chip is FPGA, the first memory
It is Double Data Rate synchronous DRAM DDR, DDR after receiving image data, which is transmitted to BRAM
In, so that BRAM carries out the image data processing of image algorithm.
Optionally, in some possible embodiments of the present invention, the bit wide matching module is shift register, if
First data bit width is less than second data bit width, and the shift register is additionally operable to：First data are carried out
Logical shift is simultaneously combined to be converted into second data；
If first data bit width is more than second data bit width, the shift register is additionally operable to：By described
One data split and logical shift is to be converted into second data.
Preferably, when deserving the first data bit width less than the second data bit width, which is the first data bit
Wide multiple.
Preferably, when deserving the second data bit width less than the first data bit width, which is the second data bit
Wide multiple.
For example, in the example of the present invention, if using shift register by 8 data conversion positions 16
When, first 8 data are subjected to displacement first with shift register and are placed in the most-significant bytes of 16 data, then again will under
One 8 data are placed in the least-significant byte of 16 data, to realize 28 data conversions into 1 16 data.
For example, in another example of the present invention, if using shift register by 16 data conversions at 8
When, the most-significant byte data of 16 data can be set to one 8 data, then the least-significant byte of 16 data is placed in one again
A data.
It is appreciated that since shift register can shift data, so as to pass through the data bit in input
When width is less than the data bit width of output, it two continuous data shifted and are combined can be realized data bit width from low level
Width is converted to high-bit width；And when the data bit width of input is more than the data bit width of output, the data of the input are torn open
It after point, then shifts again, can be achieved high-bit width being converted to low-bit width.
As can be seen that in the scheme of the present embodiment, the first data bit width of bit wide matching module receiving sensor transmission
First data；Then bit wide matching module is again by first data conversion at the second data of the second data bit width, and by this
Two data are sent to first in first out cache module；Then first in first out cache module by the second data with preset data transmission rate
It is sent to first memory, the preset data transmission rate is that the bit wide matching module is made to be kept with the first memory
The message transmission rate that clock synchronizes, the first in first out cache module logic-based storage unit.Pass through bit wide matching module
Realize the second data that the first data of the first data bit width are converted to the second data bit width, and by slow in first in first out
Storing module setting preset data transmission rate be used for transmission the second data to first memory so that the processing chip into
Block storage need not be occupied when row data transmission, saves block storage resource, improve data-handling efficiency.
In the present embodiment, data transmission device 500 is presented in the form of unit.Here " unit " can refer to spy
Determine application integrated circuit (application-specific integrated circuit, ASIC), executes one or more soft
The processor and memory of part or firmware program, integrated logic circuit and/or other the device of above-mentioned function can be provided.
It is understood that the function of each functional unit of the data transmission device 500 of the present embodiment can be according to above-mentioned side
Method specific implementation in method embodiment, specific implementation process are referred to the associated description of above method embodiment, herein
It repeats no more.
The embodiment of the present invention also provides a kind of computer storage media, wherein the computer storage media can be stored with journey
Sequence, the program include some or all of any data transmission method described in above method embodiment step when executing.
It should be noted that for each method embodiment above-mentioned, for simple description, therefore it is all expressed as a series of
Combination of actions, but those skilled in the art should understand that, the present invention is not limited by the described action sequence because
According to the present invention, certain steps can be performed in other orders or simultaneously.Secondly, those skilled in the art should also know
It knows, embodiment described in this description belongs to preferred embodiment, and involved action and module are not necessarily of the invention
It is necessary.
In the above-described embodiments, it all emphasizes particularly on different fields to the description of each embodiment, there is no the portion being described in detail in some embodiment
Point, it may refer to the associated description of other embodiment.
In several embodiments provided herein, it should be understood that disclosed device, it can be by another way
It realizes.For example, the apparatus embodiments described above are merely exemplary, for example, the unit division, it is only a kind of
Division of logic function, formula that in actual implementation, there may be another division manner, such as multiple units or component can combine or can
To be integrated into another system, or some features can be ignored or not executed.Another point, shown or discussed is mutual
Coupling, direct-coupling or communication connection can be by some interfaces, the INDIRECT COUPLING or communication connection of device or unit,
Can be electrical or other forms.
The unit illustrated as separating component may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, you can be located at a place, or may be distributed over multiple
In network element.Some or all of unit therein can be selected according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each functional unit in various embodiments of the present invention can be integrated in a processing unit, also may be used
It, can also be during two or more units be integrated in one unit to be that each unit physically exists alone.It is above-mentioned integrated
The form that hardware had both may be used in unit is realized, can also be realized in the form of SFU software functional unit.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can be stored in a computer read/write memory medium.Based on this understanding, technical scheme of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
Equipment (can be personal computer, server or network equipment etc.) execute each embodiment the method for the present invention whole or
Part steps.And storage medium above-mentioned includes：USB flash disk, read-only memory (ROM, Read-Only Memory), arbitrary access are deposited
Reservoir (RAM, Random Access Memory), mobile hard disk, magnetic disc or CD etc. are various can to store program code
Medium.
The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although with reference to before
Stating embodiment, invention is explained in detail, it will be understood by those of ordinary skill in the art that：It still can be to preceding
The technical solution recorded in each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
Modification or replacement, the range for various embodiments of the present invention technical solution that it does not separate the essence of the corresponding technical solution.
Claims (2)
1. a kind of data transmission method, which is characterized in that it is applied to fpga chip, the method includes：
First data of the first data bit width that bit wide matching module receiving sensor is sent, the bit wide matching module are displacement
Register, the sensor are ccd image sensor, and the shift register obtains described the from the ccd image sensor
One data；
The bit wide matching module counts first data conversion at the second data of the second data bit width, and by described second
According to first in first out cache module is sent to, second data are identical as the data type of first data and data content,
But data bit width is different；
Second data are sent to first memory by the first in first out cache module with preset data transmission rate, described
Preset data transmission rate is the data transmission speed for keeping the bit wide matching module synchronous with first memory holding clock
Rate, the first in first out cache module logic-based storage unit；
Wherein, the first in first out cache module is the distributed RAM based on on-site programmable gate array FPGA
RAM, the first memory are Double Data Rate synchronous DRAM DDR, extremely by DMA transfer by second data
DDR, the DDR are after receiving image data, by second data transmission to BRAM, so that the BRAM is to described
Two data carry out the processing of image algorithm；
Wherein, the bit wide matching module by first data conversion at the second data of the second data bit width, including：
If first data bit width is less than second data bit width, the shift register patrols first data
It collects and shifts and combine to be converted into second data；
If first data bit width is more than second data bit width, the shift register tears first data open
Divide and logical shift is to be converted into second data；
Wherein, when first data bit width is less than second data bit width, second data bit width is described first
The multiple of data bit width；When second data bit width is less than first data bit width, first data bit width is institute
State the multiple of the second data bit width.
2. a kind of data transmission device, which is characterized in that be applied to fpga chip, described device includes：
Bit wide matching module, for the first data of the first data bit width that receiving sensor is sent, the bit wide matching module
For shift register, the sensor is ccd image sensor, and the shift register is obtained from the ccd image sensor
First data；
The bit wide matching module, is additionally operable to the second data at the second data bit width by first data conversion, and by institute
State the second data and be sent to first in first out cache module, second data in the data type and data of first data
Hold identical, but data bit width is different, and first data are vedio data, and second data are vedio data；
The first in first out cache module, for second data to be sent to the first storage with preset data transmission rate
Device, the preset data transmission rate are the data for keeping the bit wide matching module synchronous with first memory holding clock
Transmission rate, the first in first out cache module logic-based storage unit；
Wherein, the first in first out cache module is the distributed RAM based on on-site programmable gate array FPGA
RAM, the first memory be Double Data Rate synchronous DRAM DDR, second data by DMA transfer extremely
DDR, the DDR are after receiving image data, by second data transmission to BRAM, so that the BRAM is to described
Two data carry out the processing of image algorithm；
Wherein, if first data bit width is less than second data bit width, the shift register is additionally operable to：By described
One data carry out logical shift and combine to be converted into second data；
If first data bit width is more than second data bit width, the shift register is additionally operable to：Described first is counted
According to carry out split and logical shift to be converted into second data；
Wherein, when first data bit width is less than second data bit width, second data bit width is described first
The multiple of data bit width；When second data bit width is less than first data bit width, first data bit width is institute
State the multiple of the second data bit width.
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| CN108230537B (en) * | 2017-12-29 | 2020-08-18 | 深圳怡化电脑股份有限公司 | Image data processing method, device, equipment and storage medium |
| CN108418587A (en) * | 2018-01-16 | 2018-08-17 | 四川安迪科技实业有限公司 | One kind being based on FPGA data bit width conversion method |
| CN110554852B (en) * | 2018-05-31 | 2021-11-12 | 赛灵思公司 | Data splicing structure and method and on-chip implementation thereof |
| CN109815181B (en) * | 2019-01-24 | 2020-10-13 | 武汉精立电子技术有限公司 | Method and device for converting any bit width based on AXI protocol interface |
| CN110336928A (en) * | 2019-03-15 | 2019-10-15 | 浙江工业大学 | A kind of OCT spectroscopic acquisition and Transmission system based on ZYNQ |
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| CN113094309A (en) * | 2019-12-23 | 2021-07-09 | 深圳市中兴微电子技术有限公司 | Data bit width conversion method and device |
| CN111176725B (en) * | 2019-12-27 | 2022-05-06 | 北京市商汤科技开发有限公司 | Data processing method, device, equipment and storage medium |
| CN112118407A (en) * | 2020-08-11 | 2020-12-22 | 深圳市科思科技股份有限公司 | Device and method for realizing dual-link DVI (digital video interactive) based on FPGA (field programmable Gate array) |
| CN114765628B (en) * | 2020-12-31 | 2024-08-27 | 深圳市中兴微电子技术有限公司 | Data conversion method and device, storage medium and electronic device |
| CN113703840B (en) * | 2021-08-31 | 2024-06-07 | 上海阵量智能科技有限公司 | Data processing device, method, chip, computer device and storage medium |
| CN113821463A (en) * | 2021-09-23 | 2021-12-21 | 深圳忆联信息系统有限公司 | PCIE controller verification method and device based on FPGA and computer equipment |
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