CN112153355B

CN112153355B - Digital image pixel conversion system and method based on FPGA

Info

Publication number: CN112153355B
Application number: CN202010920519.7A
Authority: CN
Inventors: 葛化敏; 艾华; 叶子依; 冯宇彤; 祝天培; 梁静迎
Original assignee: Nanjing University of Information Science and Technology
Current assignee: Nanjing University of Information Science and Technology
Priority date: 2020-09-04
Filing date: 2020-09-04
Publication date: 2022-10-14
Anticipated expiration: 2040-09-04
Also published as: CN112153355A

Abstract

The invention discloses a digital image pixel conversion system and method based on FPGA, comprising a host unit, a cache unit and an FPGA image transcoding unit; the host unit is used for outputting the digital image with the initial format to the FPGA image transcoding unit and receiving the image data after conversion; the FPGA image transcoding unit is arranged in the FPGA chip and used for completing the conversion of the image pixel format; the buffer unit is used for buffering the image data. The invention provides a system capable of completing the function of converting an RGB data format image into a YCbCr data format image, which can effectively reduce the capacity occupied by a digital image and improve the transmission efficiency and the processing efficiency of the digital image on the premise of keeping the image quality.

Description

Digital image pixel conversion system and method based on FPGA

Technical Field

The invention relates to a digital image pixel conversion system and method based on an FPGA (field programmable gate array), belonging to the field of FPGA embedded system design.

Background

The digital image technology is widely applied by virtue of the advantages of high precision and stable transmission. Data in an RGB pixel format is often obtained after data image acquisition or decoding, but in the RGB data format, the data volume is large, the occupied memory space is large, and a lot of resources are consumed in the storage and transmission processes. Compared with digital images in the digital image YCbCr data format in the RGB data format, the digital images in the YCbCr data format in the RGB data format have different data formats, and the YCbCr occupies smaller memory on the premise of retaining image information. Therefore, in order to save resources consumed in the digital image processing process, the conversion of the RGB data format into the YCbCr data format is a necessary process.

Many conventional implementations of image processing algorithms, including RGB to YCbCr pixel formats, are programmed serially. Therefore, the process of substituting an RGB data into an algorithm program to obtain a YCbCr data is also serial. While the amount of digital image data in the future is showing an increasing amount of fly-speed, more and more image data needs to be processed. The image processing is performed in a serial mode, and the requirement of larger and larger data volume on processing performance cannot be met more and more. Therefore, how to invent an image processing mode capable of replacing serial processing has higher efficiency and speed, and has important significance for the development of image processing.

Disclosure of Invention

The purpose of the invention is as follows: the invention aims to provide a digital image pixel conversion system and method based on an FPGA, which are efficient, rapid, wide in applicability and strong in stability.

The technical scheme is as follows: the digital image pixel conversion system based on the FPGA comprises a host unit, a cache unit and an FPGA image transcoding unit; the host unit is used for outputting the digital image in the initial format to the FPGA image transcoding unit and receiving the converted image data; the FPGA image transcoding unit is arranged in the FPGA chip and used for completing the conversion of the image pixel format; the buffer unit is used for buffering the image data.

The cache unit comprises an FIFO controller module arranged in the FPGA chip and an RAM cache unit arranged outside the FPGA chip; the FIFO controller module comprises an asynchronous reading FIFO unit and an asynchronous writing FIFO unit, and is used for reading data and writing the data into the RAM unit or the host.

And an RAM controller module is arranged in the FPGA chip and is used for controlling the read-write state of the RAM cache unit.

An image transcoding algorithm is arranged in the FPGA image transcoding unit, and an RGB pixel format image can be converted into a YCbCr pixel format.

The FPGA chip is also provided with a PLL clock module arranged in the FPGA chip and used for providing clocks for all modules of the system.

The RAM cache unit is DDR3 SDRAM.

The digital image pixel conversion method based on the FPGA adopts the system and comprises the following steps:

(1) The host stores an initial digital image to be transcoded, and after receiving a sending request, a sending port of the host sends the initial image to the FPGA image transcoding unit for image transcoding;

(2) The initial image processed by the FPGA image transcoding unit can be changed into a required pixel format;

(3) The FPGA image transcoding unit sends the processed image data to the write FIFO unit and writes the processed image data into the RAM cache unit under the control of the RAM controller module;

(4) The processed image data is read out from the RAM buffer unit through the reading FIFO unit;

(5) The receiving port of the host receives the processed image data from the read FIFO unit.

The initial image pixels are in RGB format, and the required pixel format is YCbCr.

The conversion mode from the RGB format to the YCbCr format is as follows:

the data of each pixel point of the RGB image corresponds to an RGB matrix, R, G and B values correspond to parameters in the matrix, the data of each pixel point of the YCbCr image corresponds to a YCbCr matrix, and Y, cb and Cr values correspond to parameters in the matrix; the matrix [ S ] is a parameter matrix for converting RGB into YCbCr.

Has the beneficial effects that: compared with the prior art, the invention has the following remarkable advantages:

(1) The invention provides a system capable of completing the function of converting an RGB data format image into a YCbCr data format image, which can effectively reduce the capacity occupied by a digital image and improve the transmission efficiency and the processing efficiency of the digital image on the premise of keeping the image quality.

(2) The invention carries out RGB to YCbCr parallel computation on RGB image data through the FPGA, can utilize the advantage of FPGA parallel processing to carry out parallel acceleration on the RGB to YCbCr algorithm, improves the speed and performance of image processing, effectively improves the realization efficiency of the RGB to YCbCr algorithm and reduces the development period and cost.

Drawings

FIG. 1 is a schematic structural view of the present invention;

fig. 2 is a schematic diagram of the operation of the system of the present invention.

Detailed Description

The technical scheme of the invention is further explained by combining the attached drawings.

The working module of the system of the invention is shown in figure 2, and the system mainly comprises: the system comprises an FPGA image transcoding unit, an FIFO controller module, an RAM controller module, a PLL (phase locked loop) clock module, an RAM cache unit and 6 host modules.

The host includes two ports: the 1 st is an output port which is responsible for outputting digital images in RGB pixel format to an FPGA image transcoding unit; the 2 nd is an input port responsible for receiving from the buffer unit the digital image in YCbCr pixel format after the conversion has been completed.

The FPGA image transcoding unit is a core function module of the invention. The module is based on the mathematical principle of digital image RGB to YcbCr:

The mathematical principle is implemented into an algorithm by using software programming and finally implemented in an FPGA. The module has the functions of converting an RGB pixel format image into a YCbCr pixel format, namely reducing the length of image data, keeping image information and simultaneously occupying smaller capacity, being more beneficial to storage, transmission and processing, combining the advantage of FPGA parallel processing with image processing, improving the image processing performance to a great extent and improving the working efficiency.

The buffer unit comprises an FIFO controller module and an RAM controller module which are arranged in the FPGA chip, and preferably comprises an RAM buffer unit which is arranged outside the FPGA chip.

The FIFO controller module comprises two asynchronous FIFOs which are respectively used as a read FIFO and a write FIFO. Because the clock frequency of the DDR3SDRAM module of the system under work is different from the clock of an FPGA onboard system, the video data is easily lost in the transmission process due to direct transmission, and two asynchronous FIFOs are used. The asynchronous FIFO is configured by a Block RAM inside an FPGA and can work under the condition that the speeds of an input port and an output port are not matched. The main function is to prevent data loss during data transmission between different clock domains.

And the RAM cache unit is used for temporarily caching the digital image and adopts DDR3 SDRAM. The DDR3SDRAM has the advantages of high speed, high working efficiency, low cost, large capacity and strong performance when being used as a cache device.

And the RAM controller module is mainly used for controlling the read-write state of the DDR3SDRAM, and when a write request comes, the transcoded image data is written into the DDR3SDRAM through the write FIFO and is cached. When a reading request comes, the data cached in the DDR3SDRAM is read out through the reading FIFO, and the caching work of the transcoded image data is completed.

The system also comprises a PLL clock module arranged in the FPGA chip and used for providing clocks for the system, wherein the onboard clock is 50MHz, and the DDR3SDRAM working clock is 200MHz. The PLL takes 50MHz as input, outputs 200MHz clock to DDR3 SDRAM.

The working principle of the system of the invention is as follows:

(1) The host stores the RGB digital image to be transcoded, and after receiving the sending request, the sending port of the host sends the RGB image to the FPGA for image transcoding.

(2) The image algorithm of converting RGB into YCbCr is realized in the FPGA, the received digital image data can be processed by the FPGA, the RGB pixel format image processed by the FPGA can be changed into YCbCr pixel format, and then the image is sent to the buffer for buffering.

(3) The buffer is composed of 3 parts of write FIFO, DDR3SDRAM and read FIFO, and the image is written into the DDR3SDRAM through the write FIFO and is buffered.

(4) The YCbCr image is read from the DDR3SDRAM through a read FIFO.

(5) The receiving port at the host side is ready to receive the image buffered by the DDR3 SDRAM. And finally, the YcbC pixel format image is read out through the read FIFO and is sent to a receiving end of the host by the FPGA.

Claims

1. A digital image pixel conversion system based on FPGA is characterized by comprising a host, a cache unit and an FPGA image transcoding unit; the host is used for outputting the digital image in the initial format to the FPGA image transcoding unit and receiving the converted image data; the FPGA image transcoding unit is arranged in the FPGA chip and used for completing the conversion of the image pixel format; the cache unit is used for caching the image data;

the cache unit comprises an FIFO controller module arranged in the FPGA chip and an RAM cache unit arranged outside the FPGA chip; the FIFO controller module comprises an asynchronous FIFO reading unit and an asynchronous FIFO writing unit, and is used for reading data and writing the data into the RAM unit or the host; an image transcoding algorithm is arranged in the FPGA image transcoding unit, and RGB pixel format images are converted into YCbCr pixel format images; the RAM cache unit is DDR3 SDRAM; the asynchronous read FIFO element and the asynchronous write FIFO element function to prevent data loss asynchronization during data transmission between different clock domains.

2. The FPGA-based digital image pixel conversion system of claim 1, wherein a RAM controller module is disposed in the FPGA chip and is configured to control a read/write state of a RAM cache unit.

3. The FPGA-based digital image pixel conversion system of claim 1, further comprising a PLL clock module disposed within the FPGA chip for clocking the various modules of the system.

4. An FPGA-based digital image pixel conversion method, which adopts the system of any one of claims 1 to 3, and is characterized by comprising the following steps:

5. The FPGA-based digital image pixel conversion method of claim 4, wherein the initial image pixel is in RGB format and the desired pixel format is YCbCr.

6. The FPGA-based digital image pixel conversion method of claim 5, wherein the conversion from the RGB format to the YCbCr format is performed by:

the data of each pixel point of the YCbCr image corresponds to a YCbCr matrix, and the values of Y, cb and Cr correspond to the parameters in the matrix; the matrix [ S ] is a parameter matrix for converting RGB into YCbCr.