WO2023185094A1 - Video compression system and method, computer readable storage medium, and server - Google Patents

Abstract

The present application discloses a video compression system and method, a computer readable storage medium, and a server. The video compression system comprises a color space conversion module, a memory, a FIFO array module, a read-write control module, and a video compression control module; the memory comprises a cache space and a compressed data storage space; the FIFO array module comprises a plurality of FIFOs; the FIFOs are used for storing Y component or V component or U component data; the FIFO array module is configured to correspondingly set the bit widths of the FIFOs on the basis of the number of the FIFOs, such that the FIFOs store the Y component or U component or V component data of two adjacent rows at the same time; and the read-write control module is configured to sequentially read the Y component or U component or V component data at corresponding positions of two adjacent rows from the corresponding FIFOs in each clock period and send the data to the video compression control module.

Description

A video compression system, method, computer-readable storage medium and server

Cross-references to related applications

This application requires the priority of the Chinese patent application submitted to the China Patent Office on April 2, 2022, with the application number 202210340428.5, and the application name is "A video compression system, method, computer-readable storage medium and server", all of which The contents are incorporated into this application by reference.

Technical field

This application relates to a video compression system, method, computer-readable storage medium and server.

Background technique

The video compression system in traditional baseboard management control chips has the following two solutions:

Option 1: After the video data on the host side is transmitted to the baseboard management control chip through PCIe (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard), RGB (Red Green Blue, red, green and blue) original video information is generated and written to Off-chip DDR (Double Data Rate, double rate synchronous dynamic random access memory) is cached, and the original RGB format video data is converted into YUV (color encoding method, Y represents brightness (Luminance) through the color space conversion module (RGB2YUV) , Luma), U and V are data in the format of chrominance, concentration (Chrominance, Chroma), and then the Y, U, and V data are stored in the DDR space (Y_addr, U_addr, V_addr) at different off-chip starting addresses. ), and at the same time configure the starting addresses of Y, U, and V to the video compression IP through the CPU. The CMP (video compression control module) generates the address of the off-chip DDR in the order of BLOCK data according to the requirements of the video compression IP, and then inputs it to the video compression control module in the order of BLOCK data. After the compression is completed, the data Write to DDR, EMAC (Ethernet Media Access Control, Ethernet Media Access Control) network card driver reads the compressed data, and transmits the video data to the remote through the network for remote display.

Option 2: After the video data on the host side is transferred to the substrate management control chip through PCIe, the original RGB video information is generated and written to the off-chip DDR for caching. The original RGB format video data is converted to the original RGB format video data through the color space conversion module (RGB2YUV). Convert to YUV format data, and then cache the Y, U, and V data using on-chip storage resources (FIFO). According to the BLOCK format conversion requirements (supports YUV444/YUV422/YUV420 compression format), 16 Y_FIFOs are required, 16 U_FIFO, 16 V_FIFO. At the same time, according to project practical experience, for the maximum resolution (1920*1200), the depth of FIFO ((First in First out, first in first out)) is 16384, and the width is 8bits. The required The total storage capacity of FIFO is 768KB, so that the FIFO will not be full and data will not be lost.

The disadvantage of traditional solution 1 is that the baseboard management control chip needs to access the off-chip DDR very frequently, resulting in a high memory bandwidth occupied by the video function, which greatly affects other software running on the CPU (Central Processing Unit, central processing unit). Memory access affects the overall performance of the baseboard management control chip.

The disadvantage of traditional solution 2 is that it requires a large amount of on-chip resources. For chip projects, on-chip storage resources (FIFO) are very precious. A large number of FIFOs will increase the area of the chip. At the same time, the large number and capacity of FIFOs poses great problems to the chip timing constraints, back-end design, packaging and manufacturing processes.

Contents of the invention

According to various embodiments disclosed in this application, this application proposes a video compression system, method, computer-readable storage medium and server.

A video compression system for substrate management control chip. The video compression system specifically includes:

Color space conversion module, memory, FIFO array module, read and write control module, video compression control module. The memory includes cache space and compressed data storage space. The FIFO array module includes multiple FIFOs. The FIFO is used to store the Y component or V component or U component data;

The baseboard management control chip is configured to write the received RGB video data into the cache space in a row;

The color space conversion module is configured to read each line of RGB video data from the cache space in sequence, and convert the RGB video data into Y component, U component and V component data;

The FIFO array module is configured to set the bit width of the FIFO based on the number of FIFOs so that the FIFO can store the Y component, U component, or V component data of two adjacent rows at the same time;

The read-write control module is configured to read the Y component, U component and V component data at the corresponding position in each clock cycle, and write them in parallel to the corresponding FIFO for caching;

The read-write control module is also configured to read the corresponding positions of two adjacent rows from the corresponding FIFO in each clock cycle according to the arrangement order of each FIFO in the FIFO array after receiving the read data request from the video compression control module. The Y component or U component or V component data constitutes BLOCK data and is sent to the video compression control module; and

The video compression control module is configured to compress the received BLOCK data and write the compressed data into the compressed data storage space.

A video compression method for substrate management control chip, executed based on the above video compression system, includes the following steps:

The baseboard management control chip writes the received RGB video data into the buffer space in rows;

The color space conversion module reads each line of RGB video data from the cache space in turn, and converts the RGB video data into Y component, U component and V component data;

The FIFO array module sets the bit width of the FIFO based on the number of FIFOs so that the FIFO can store the Y component, U component, or V component data of two adjacent rows at the same time;

The read-write control module reads the Y component, U component and V component data at the corresponding position of each row in each clock cycle, and writes them in parallel to the corresponding FIFO for caching;

After receiving the read data request from the video compression control module, the read-write control module reads the Y components of the corresponding positions of two adjacent rows from the corresponding FIFO in each clock cycle according to the arrangement order of each FIFO in the FIFO array. Or the U component or V component data is composed of BLOCK data and sent to the video compression control module; and

The video compression control module compresses the received BLOCK data and writes the compressed data into the compressed data storage space.

A non-transitory computer-readable storage medium stores computer-readable instructions that implement the above method steps when executed by a processor.

A server includes the above video compression system.

Description of drawings

In order to explain the embodiments of the present application or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are only These are some embodiments of the present application. For those of ordinary skill in the art, other embodiments can be obtained based on these drawings without exerting creative efforts.

Figure 1 is a schematic diagram of a traditional video compression system;

Figure 2 is a schematic diagram of the BLOCK data composition required by different YUV compression formats;

Figure 3 is a schematic diagram of a video compression system for a substrate management control chip provided by an embodiment of the present application;

Figure 4 is a schematic diagram comparing the storage of Y component data in the video compression system provided by the embodiment of the present application and the storage of Y component data in the traditional video compression system;

Figure 5 is a schematic diagram comparing the storage of U component data in the video compression system provided by the embodiment of the present application and the storage of U component data in the traditional video compression system;

Figure 6 is a schematic diagram comparing the storage of V component data in the video compression system provided by the embodiment of the present application and the storage of V component data in the traditional video compression system;

Figure 7 is a block diagram of a video compression method for a baseboard management control chip provided by an embodiment of the present application;

Figure 8 is a schematic structural diagram of a non-transitory computer-readable storage medium provided by an embodiment of the present application;

Figure 9 is a schematic structural diagram of a server provided by an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail below with reference to specific embodiments and the accompanying drawings.

It should be noted that all expressions using “first” and “second” in the embodiments of this application are intended to distinguish two entities or parameters with the same name but not the same. It can be seen that “first” and “second” It is only for the convenience of description and should not be understood as a limitation on the embodiments of the present application, and subsequent embodiments will not describe this one by one.

As shown in Figure 1, it is a schematic diagram of the video compression system of traditional solution 2.

As shown in Figure 2, it shows the BLOCK data composition required by different YUV compression formats.

In Figure 2, Cb represents the U component, and Cr represents the V component. The left side of Figure 2 is the source image picture (Source Image Picture) of the video data in YUV format. After discrete cosine transform (Discrete Cosine Transform, referred to as DCT), Form BLOCK format data for storage. On the right side of Figure 2, height represents the height of the box, and width represents the width of the box. Each small box represents the 8*8 pixels on the left side of Figure 2, and the large box represents 16*16 Pixels, the rectangular box is 8*16 pixels. Taking YUV420 as an example, the Y block represents the Y component of four 8*8 pixels, the Cb block represents the U component of one 8*8 block, and the Cr block represents the V component of one 8*8 block.

In other words, if the current compression format is YUV420, Video CMP (Video Compression Control Module) must generate an address sequence for reading the 16*16 Y component, an address sequence for the 8*8 U component, and an 8*8 V component. Address sequence, and then loop in sequence; if the current compression format is YUV422, Video CMP should generate the address sequence of reading the Y component of 16*16, the address sequence of the U component of 8*16, and the address sequence of the V component of 8*16. Then it loops in sequence; if the current compression format is YUV444, Video CMP should generate the address sequence of reading the Y component of 8*8, the address sequence of the U component of 8*8, the address sequence of the V component of 8*8, and then loop in sequence. .

As shown in the video compression system shown in Figure 1, the video data on the host side (HOST) is in RGB format. After being transmitted to the substrate management control chip through PCIe, the RGB original video information is generated and written to the off-chip DDR for caching. The color space The conversion module (RGB2YUV) reads RGB format video data from off-chip DDR, converts the original RGB format video data into YUV format data, and then the read and write control module (FIFO_CTRL) reads the video data in RGB format according to the compression format (supports YUV444/YUV422/YUV420 Compression format) reads the converted YUV format data, caches the Y, U, and V data using the on-chip FIFO array (FIFO_ARRAY), and reads it from the FIFO array according to the requirements of the BLOCK format and sends it to the video compression control module (Video CMP), under the traditional solution, in order to meet the conversion requirements of the BLOCK format, 16 Y_FIFOs, 16 U_FIFOs, and 16 V_FIFOs are needed to form a FIFO array.

During the video data compression process, FIFO_CTRL (FIFO read-write control module) does not care about the read address issued by Video CMP, and FIFO_CTRL itself generates read-write control logic to read the corresponding FIFO.

The YUV data writing control logic through FIFO_CTRL is as follows:

In YUV420 format, retain all Y data and retain U/V data of even rows and even columns, as follows:

Write the Y data of row 0/16/32/48... into Y_RAM_0;

Write the Y data of row 1/17/33/49... into Y_RAM_1;

Write the Y data of row 2/18/34/50... into Y_RAM_2;

…

Write the Y data of row 15/31/47/63... into Y_RAM_15;

Write the even column U data of row 0/16/32/48... into U_RAM_0;

Write the even column U data of row 2/18/34/50... into U_RAM_1;

…

Write the even column U data of row 14/30/46/62... into U_RAM_7;

Write the even column U data of row 0/16/32/48... into V_RAM_0;

Write the even column U data of row 2/18/34/50... into V_RAM_1;

…

Write the even column U data of row 14/30/46/62... into V_RAM_7.

In YUV422 format, retain all Y data and retain the U/V data of even columns, as follows:

Write the Y data of row 0/16/32/48... into Y_RAM_0;

Write the Y data of row 1/17/33/49... into Y_RAM_1;

Write the Y data of row 2/18/34/50... into Y_RAM_2;

…

Write the Y data of row 15/31/47/63... into Y_RAM_15;

Write the even column U data of row 0/16/32/48... into U_RAM_0;

Write the even column U data of row 1/17/33/49... into U_RAM_1;

Write the even column U data of row 2/18/34/50... into U_RAM_2;

…

Write the U data of the 15/31/47/63... rows and even columns into U_RAM_15;

Write the even column V data of row 0/16/32/48... into V_RAM_0;

Write the even column V data of row 1/17/33/49... into V_RAM_1;

Write the even column V data of row 2/18/34/50... into V_RAM_2;

…

Write the V data of the 15/31/47/63... rows and even columns into V_RAM_15.

In YUV444 format, retain the Y/U/V data of all rows and all columns, as follows:

Write the Y data of row 0/8/16/24... into Y_RAM_0;

Write the Y data of row 1/9/17/25... into Y_RAM_1;

Write the Y data of row 2/10/18/26... into Y_RAM_2;

…

Write the Y data of row 7/15/23/31... into Y_RAM_7;

Write the U data of line 0/8/16/24... into U_RAM_0;

Write the U data of lines 1/9/17/25... into U_RAM_1;

Write the U data in line 2/10/18/26... into U_RAM_2;

…

Write the U data in line 7/15/23/31... into U_RAM_7;

Write the V data in line 0/8/16/24... into V_RAM_0;

Write the V data of rows 1/9/17/25... into V_RAM_1;

Write the V data of row 2/10/18/26... into V_RAM_2;

…

Write the V data of line 7/15/23/31... into V_RAM_7.

The YUV data read control logic through FIFO_WR_CTRL is as follows:

In the YUV420 format, RAM_RD_CTRL does not care about the read address issued by Video CMP IP, but only cares about the read enable issued by Video CMP. It reads 16 times Y_FIFO_0, 16 times Y_FIFO_1,..., 16 times Y_FIFO_15, 8 times U_FIFO_0, 8 U_FIFO_1 times,..., U_FIFO_7 8 times, V_FIFO_0 8 times, V_FIFO_1 8 times,..., V_FIFO_7 8 times, and then cycle in sequence.

In the YUV422 format, RAM_RD_CTRL does not care about the read address issued by Video CMP, but only cares about the read enable issued by Video CMP IP. It reads 16 times Y_FIFO_0, 16 times Y_FIFO_1,..., 16 times Y_FIFO_15, 8 times U_FIFO_0, 8 times. U_FIFO_1,..., 8 times U_FIFO_15, 8 times V_FIFO_0, 8 times V_FIFO_1,..., 8 times V_FIFO_15, and then loop in sequence.

In YUV444 format, RAM_RD_CTRL does not care about the read address issued by Video CMP IP, but only cares about the read enable issued by Video CMP. It reads Y_FIFO_0 8 times, Y_FIFO_1 8 times,..., Y_FIFO_7 8 times, U_FIFO_0 8 times, 8 times in sequence. U_FIFO_1,..., 8 times U_FIFO_7, 8 times V_FIFO_0, 8 times V_FIFO_1,..., 8 times V_FIFO_7, and then loop in sequence.

The above-mentioned traditional video compression system has the following shortcomings: it takes up a lot of on-chip resources, and a large number of FIFOs will cause the following problems: increasing the manufacturing area of the chip, making packaging and manufacturing difficult, causing timing constraints, and reducing video compression efficiency. For example, the data bus interface of Video CMP is 32bits or 64bits. The reading logic of the traditional solution is to read 8bits each time. It needs to cache 4 or 8 entries before transmitting them to Video CMP for compression, which lengthens the compression time and reduces the compression efficiency.

Based on the above purpose, the first aspect of the embodiment of the present application proposes a video compression system for a substrate management control chip. As shown in Figure 3, the video compression system specifically includes: a color space conversion module 110, a memory 120, FIFO array module 130, read and write control module 140, video compression control module 150, memory 120 includes cache space 121 and compressed data storage space 122, FIFO array module 130 includes multiple FIFOs;

The baseboard management control chip is configured to write the received RGB video data into the cache space 121 in a line manner;

The color space conversion module 110 is configured to read the RGB video data of each row from the cache space 121 in sequence, and convert the RGB video data into Y component, U component and V component data;

The FIFO array module 130 is configured to correspondingly set the bit width of the FIFO based on the number of FIFOs so that the FIFO simultaneously stores the Y component or U component or V component data of two adjacent rows;

Set the 1st to 8th FIFOs to store Y component data, the 9th to 16th FIFOs to store U component data, the 17th to 24th FIFOs to store V component data, and set the bit width of each FIFO to 16 bits to simultaneously store the Y component, U component, or V component data of two adjacent rows;

The read-write control module 140 is configured to read the Y component, U component, and V component data at the corresponding position in each clock cycle, and write the corresponding FIFOs in parallel for caching;

The read and write control module 140 is also configured to, after receiving a read data request from the video compression control module, read two adjacent rows of data from the corresponding FIFO in sequence in each clock cycle according to the arrangement order of each FIFO in the FIFO array. The Y component, U component, or V component data of the position constitutes BLOCK data and is sent to the video compression control module 150;

The video compression control module 150 is configured to compress the received BLOCK data and write the compressed data into the compressed data storage space.

Specifically, the memory can be any one of SRAM (Static Random-Access Memory, static random access memory), SDRAM (synchronous dynamic random-access memory, synchronous dynamic random access memory), and DDR. In this embodiment, Choose DDR.

In this embodiment, the FIFO array module includes 24 FIFOs, and the bit width of each FIFO is set to 16 bits to simultaneously store the Y component, U component, or V component data of two adjacent rows. It should be noted that the FIFO array module can also include other numbers of FIFOs, but the purpose of this application is to simultaneously store the Y component or U component or V component data of two adjacent rows to improve the video data (Y component or U component or V component data). Therefore, preferably, the FIFO array module includes 24 FIFOs, and the bit width of each FIFO is set to 16 bits to ensure that the video The writing speed of data will not be slowed down.

The baseboard management control chip is configured to perform the following steps:

Receive the original RGB video data sent by the host, and write the received RGB video data into the cache space (SOURCE_DATA) in rows. For example, if the resolution of the original RGB video data is 1024*768, 768 lines of RGB data are written each time, and the number of RGB data written in each line is 1024. Writing RGB data into the cache space in rows is beneficial to subsequent conversion of RGB data to YUV data.

The color space conversion module is configured to perform the following steps:

Read each row of RGB video data from the cache space in turn, and convert the R component, G component and B component data of the RGB video data into YUV data, that is, Y component data, U component data and V component data, where, RGB video The data is 24 bits, and the R component, G component and B component each occupy 8 bits.

The FIFO array module is configured to perform the following steps:

Set the first 8 FIFOs to store Y component data, the middle 8 FIFOs to store U component data, the last 8 FIFOs to store V component data, and set the bit width of each FIFO to 16 bits to store adjacent Two rows of Y component, U component, or V component data are shown in Figures 4 to 6. The left side of Figures 4 to 6 shows the traditional FIFO array storing Y component data, U component data, and V component data respectively. The right side is a diagram of the FIFO array of this application scheme storing Y component data, U component data, and V component data. It can be seen that setting the bit width of each FIFO to 16 bits reduces the number of FIFOs in the FIFO array, so The required overall cache area is reduced, saving manufacturing costs.

The read-write control module includes write control logic and read control logic. The write control logic is configured to perform the following steps:

Discard the YUV data after format conversion according to the compression format (YUV444 or YUV422 or YUV420) issued by the CPU. For example: YUV422 compression format, all Y data and U/V data of even columns need to be retained. ; The YUV420 compression format needs to retain all Y data and the U/V data of even rows and even columns; the YUV444 compression format needs to retain the Y/U/V data of all rows and all columns, and the corresponding data is discarded according to the requirements of each compression format. , write the retained YUV data into the FIFO array. The specific writing process is: read the Y component, U component and V component data of the corresponding row and column at the same time in each clock cycle, and write the Y component, U component and U component data that are simultaneously read. The component and V component data are written to their corresponding FIFOs for caching at the same time. For example: within one clock cycle, the Y component, U component and V component data of row 0 and column 0 are read at the same time, and Y_FIFO_0, U_FIFO_0, V_FIFO_0.

Furthermore, the read-write control module can also read and write the data that needs to be retained according to the compression format issued by the CPU during the writing process, and then discard the remaining data.

Combined with Figures 4 to 6, the writing process of the write control logic of the read-write control module is explained. The specific writing process is as follows:

1)YUV420 format

a) Y component

Write the Y data of rows 0/16/32/48... into the first 8 bits space of Y_FIFO_NEW_0 in sequence, write the Y data of rows 1/17/33/49... into the last 8 bits space of Y_FIFO_NEW_0 in sequence, and write the Y data of rows 1/17/33/49... into the last 8 bits space of Y_FIFO_NEW_0 in sequence. The Y data of rows 2/18/34/50... are written into the first 8 bits space of Y_FIFO_NEW_1 in sequence, the Y data of rows 3/19/35/51... are written into the last 8 bits space of Y_FIFO_NEW_1 in sequence, and the Y data of rows 3/19/35/51... are written into the last 8 bits space of Y_FIFO_NEW_1 in sequence. The Y data of rows 20/36/52... are written into the first 8 bits space of Y_FIFO_NEW_2 in sequence, the Y data of rows 5/21/37/53... are written into the last 8 bits space of Y_FIFO_NEW_2 in sequence, and the Y data of rows 5/21/37/53... are written into the last 8 bits space of Y_FIFO_NEW_2 in sequence. The Y data of rows 38/54... are written into the first 8 bits space of Y_FIFO_NEW_3 in turn, and the Y data of rows 7/23/39/55... are written into the last 8 bits space of Y_FIFO_NEW_3 in sequence,..., the Y data of rows 7/23/39/55... are written into the last 8 bits space of Y_FIFO_NEW_3,... The Y data of rows /46/62... are written into the first 8 bits space of Y_FIFO_NEW_7 in sequence, and the Y data of rows 15/31/47/63... are written into the last 8 bits space of Y_FIFO_NEW_7 in sequence.

b)U component

Write the even-numbered column U data of row 0/16/32/48... into the first 8bits space of U_FIFO_NEW_0, and write the even-numbered column U data of row 2/18/34/50... into the last 8bits space of U_FIFO_NEW_0,... , write the even-numbered column U data in row 12/28/44/60... into the first 8bits space of U_FIFO_NEW_3, and write the even-numbered column U data in row 14/30/46/62... into the last 8bits space of U_FIFO_NEW_3.

c)V component

Write the even column V data of row 0/16/32/48... into the first 8 bits space of V_FIFO_NEW_0, and write the even column V data of row 2/18/34/50... into the last 8 bits space of V_FIFO_NEW_0,... , write the even column V data in the 12/28/44/60... row into the first 8 bits space of V_FIFO_NEW_3, and write the even column V data in the 14/30/46/62... row into the last 8 bits space of V_FIFO_NEW_3.

2)YUV422 compression format

a) Y component

Write the Y data of rows 0/16/32/48... into the first 8 bits space of Y_FIFO_NEW_0 in sequence, write the Y data of rows 1/17/33/49... into the last 8 bits space of Y_FIFO_NEW_0 in sequence, and write the Y data of rows 1/17/33/49... into the last 8 bits space of Y_FIFO_NEW_0 in sequence. The Y data of rows 2/18/34/50... are written into the first 8 bits space of Y_FIFO_NEW_1 in sequence, the Y data of rows 3/19/35/51... are written into the last 8 bits space of Y_FIFO_NEW_1 in sequence, and the Y data of rows 3/19/35/51... are written into the last 8 bits space of Y_FIFO_NEW_1 in sequence. The Y data of rows 20/36/52... are written into the first 8 bits space of Y_FIFO_NEW_2 in sequence, the Y data of rows 5/21/37/53... are written into the last 8 bits space of Y_FIFO_NEW_2 in sequence, and the Y data of rows 5/21/37/53... are written into the last 8 bits space of Y_FIFO_NEW_2 in sequence. The Y data of rows 38/54... are written into the first 8 bits space of Y_FIFO_NEW_3 in sequence, and the Y data of rows 7/23/39/55... are written into the last 8 bits space of Y_FIFO_NEW_3 in sequence, ..., and the Y data of rows 7/23/39/55... are written into the last 8 bits space of Y_FIFO_NEW_3. The Y data of rows /46/62... are written into the first 8 bits space of Y_FIFO_NEW_7 in sequence, and the Y data of rows 15/31/47/63... are written into the last 8 bits space of Y_FIFO_NEW_7 in sequence.

b)U component

Write the even column U data of row 0/16/32/48... into the first 8 bits space of U_FIFO_NEW_0, write the even column U data of row 1/17/33/49... into the last 8 bits space of U_FIFO_NEW_0, Write the even column U data of row 2/18/34/50... into the first 8 bits space of U_FIFO_NEW_1, write the even column U data of row 3/19/35/51... into the last 8 bits space of U_FIFO_NEW_1,..., The U data in the even-numbered columns of rows 14/30/46/62... is written into the first 8bits space of U_FIFO_NEW_7, and the U data in the even-numbered columns of rows 15/31/47/63... is written into the last 8bits space of U_FIFO_NEW_7.

c)V component

Write the even-numbered column V data of row 0/16/32/48... into the first 8 bits space of V_FIFO_NEW_0, write the even-numbered column V data of row 1/17/33/49... into the last 8 bits space of V_FIFO_NEW_0, Write the even column V data of row 2/18/34/50... into the first 8 bits space of V_FIFO_NEW_1, write the even column V data of row 3/19/35/51... into the last 8 bits space of V_FIFO_NEW_1,..., The V data in the even-numbered columns of rows 14/30/46/62... is written into the first 8bits space of V_FIFO_NEW_7, and the V data in the even-numbered columns of rows 15/31/47/63... is written into the last 8bits space of V_FIFO_NEW_7.

3)YUV444 format

a) Y component

Write the Y data of row 0/8/16/24... into the first 8 bits storage space of Y_FIFO_NEW_0, write the Y data of row 1/9/17/25... into the last 8 bits storage space of Y_FIFO_NEW_0, and write the Y data of row 1/9/17/25... into the last 8 bits storage space of Y_FIFO_NEW_0. Write the Y data of row 10/18/26... into the first 8bits storage space of Y_FIFO_NEW_1, write the Y data of row 6/14/22/30... into the first 8bits storage space of Y_FIFO_NEW_3, and write the Y data of row 6/14/22/30... into the first 8bits storage space of Y_FIFO_NEW_3. The Y data of rows 31... is written into the last 8bits storage space of Y_FIFO_NEW_3.

b)U component

Write the U data of the 0/8/16/24... line into the first 8 bits storage space of U_FIFO_NEW_0, write the U data of the 1/9/17/25... line into the last 8 bits storage space of U_FIFO_NEW_0, and write the 2/ The U data of row 10/18/26... is written into the first 8 bits storage space of U_FIFO_NEW_1,..., and the U data of row 6/14/22/30... is written into the first 8 bits storage space of U_FIFO_NEW_3, and the U data of row 7/15 is written into the first 8 bits storage space of U_FIFO_NEW_3. The U data of line /23/31... is written into the last 8bits storage space of U_FIFO_NEW_3.

c)V component

Write the V data in the 0/8/16/24... line into the first 8 bits storage space of V_FIFO_NEW_0, write the V data in the 1/9/17/25... line into the last 8 bits storage space in V_FIFO_NEW_0, and write the 2/ The V data of row 10/18/26... is written into the first 8bits storage space of V_FIFO_NEW_1,..., the V data of row 6/14/22/30... is written into the first 8bits storage space of V_FIFO_NEW_3, and the V data of row 7/15 is written into the first 8bits storage space of V_FIFO_NEW_3. The V data of lines /23/31... is written into the last 8bits storage space of V_FIFO_NEW_3.

The above scheme realizes the writing of YUV data when the bit width of each FIFO is set to 16bit.

The read control logic is configured to perform the following steps:

After receiving the read data request from the video compression control module, in each clock cycle, the Y component or U component or The V component data constitutes BLOCK data and is sent to the video compression control module.

First, taking the YUV420 format to read the Y component data of the corresponding positions of two adjacent lines to form the first BLOCK data as an example, the readout process will be explained.

The first BLOCK composed of Y data consists of the first 16 Y component data of row 0, row 1,..., and row 15. Y_FIFO_NEW_0 is read 16 times, 16bits are read once, and a total of 16*16 is read. =256bits data, use the data in the first 8bits space of Y_FIFO_NEW_0 (total 16*8=128bits) to form the first row of BLOCK data, and use the data in the last 8bits space of Y_FIFO_NEW_0 (total 16*8=128bits) to form the second line of BLOCK data Row, read Y_FIFO_NEW_1 16 times, use the data in the first 8bits of Y_FIFO_NEW_1 (a total of 16*8=64bits) to form the third line of BLOCK data, and use the data in the last 8bits of Y_FIFO_NEW_1 (a total of 16*8=64bits) to form the BLOCK data The 4th line,..., read Y_FIFO_NEW_7 16 times, use the data in the first 8bits space of Y_FIFO_NEW_7 (a total of 16*8=64bits) to form the 14th line of BLOCK data, and use the data in the last 8bits space of Y_FIFO_NEW_7 (a total of 16*8 =64bits) constitutes the 15th line of BLOCK data.

It can be seen from this that in the traditional solution to read out all the data of a BLOCK, it is necessary to read 16*16=256 times of FIFO, that is, it takes 256 clocks to read out all the data of a BLOCK. The readout composition of the embodiment of this application A BLOCK data requires 16*8=128 FIFO times, that is, it only takes 128 clock cycles to read out a BLOCK data. Therefore, when the writing speed on the writing side is consistent with the traditional solution, the read speed of the embodiment of the present application is doubled compared with the traditional solution, greatly improving the video compression efficiency.

Continue to explain the process of reading other component data in YUV420 format, reading Y, U, and V component data in YUV422 format, and reading Y, U, and V component data to form BLOCK data in YUV444 format.

The U component reading process in YUV420 format is:

Read U_FIFO_NEW_0 8 times to form the 0th and 1st lines of BLOCK. Read U_FIFO_NEW_1 8 times to form the 2nd and 3rd lines of BLOCK. Read U_FIFO_NEW_2 8 times to form the 4th and 5th lines of BLOCK. Read U_FIFO_NEW_3 8 times to form the BLOCK. Lines 6 and 7. Under the traditional solution, U_FIFO needs to be read 64 times, but in the embodiment of this application, it only needs to be read 32 times.

The V component reading process in YUV420 format is:

Read V_FIFO_NEW_0 8 times to form lines 0 and 1 of BLOCK. Read V_FIFO_NEW_1 8 times to form lines 2 and 3 of BLOCK. Read V_FIFO_NEW_2 8 times to form lines 4 and 5 of BLOCK. Read V_FIFO_NEW_3 8 times to form lines 4 and 5 of BLOCK. In lines 6 and 7, under the traditional scheme, V_FIFO needs to be read 64 times, but in the embodiment of this application, it only needs to be read 32 times.

Then it loops in sequence to read the Y, U, and V component data at the next position in the corresponding FIFO in the array to form the next BLOCK data.

The Y component reading process in YUV422 format is:

Read Y_FIFO_NEW_0 16 times to get rows 0 and 1 of Y_BLOCK data, read Y_FIFO_NEW_1 16 times to get rows 2 and 3 of Y_BLOCK data, ..., read Y_FIFO_NEW_7 16 times to get rows 14 and 15 of Y_BLOCK data, traditional solution Next, Y_FIFO needs to be read, 16*16=256 times, and the embodiment of this application reads 16*8=128 times.

The U component reading process in YUV422 format is:

Read U_FIFO_NEW_0 8 times to get rows 0 and 1 of U_BLOCK data, read U_FIFO_NEW_1 8 times to get rows 2 and 3 of U_BLOCK data, ..., read U_FIFO_NEW_7 8 times to get rows 14 and 15 of U_BLOCK data, traditional solution Next, U_FIFO needs to be read 16*8=128 times. In the embodiment of this application, it only needs to be read 8*8=64 times.

The V component reading process in YUV422 format is:

Read V_FIFO_NEW_0 8 times to get rows 0 and 1 of V_BLOCK data, read V_FIFO_NEW_1 8 times to get rows 2 and 3 of V_BLOCK data,..., read V_FIFO_NEW_7 8 times to get rows 14 and 15 of V_BLOCK data, traditional solution Next, V_FIFO needs to be read 16*8=128 times. In the embodiment of this application, it only needs to be read 8*8=64 times.

The Y component reading process in YUV444 format is:

Read Y_FIFO_NEW_0 8 times to get rows 0 and 1 of Y_BLOCK data, read Y_FIFO_NEW_1 8 times to get rows 2 and 3 of Y_BLOCK data,..., read Y_FIFO_NEW_3 8 times to get rows 6 and 7 of Y_BLOCK data, traditional solution Next, Y_FIFO needs to be read 8*8=64 times. In the embodiment of this application, it only needs to read 8*4=32 times.

The U component reading process in YUV444 format is:

Read U_FIFO_NEW_0 8 times to get rows 0 and 1 of U_BLOCK data, read U_FIFO_NEW_1 8 times to get rows 2 and 3 of U_BLOCK data, ..., read U_FIFO_NEW_3 8 times to get rows 6 and 7 of U_BLOCK data, traditional solution Under this design, U_FIFO needs to be read 8*8=64 times. In this design, only 8*4=32 times needs to be read.

The V component reading process in YUV444 format is:

Read V_FIFO_NEW_0 8 times to get rows 0 and 1 of V_BLOCK data, read V_FIFO_NEW_1 8 times to get rows 2 and 3 of V_BLOCK data, ..., read V_FIFO_NEW_3 8 times to get rows 6 and 7 of V_BLOCK data, traditional solution Next, V_FIFO needs to be read 8*8=64 times. In the embodiment of this application, it only needs to read 8*4=32 times.

Then it loops in sequence to read the Y, U, and V component data at the next position in the corresponding FIFO in the array to form the next BLOCK data.

It can be seen that the video data readout speed of the read-write control module is greatly improved, and the video compression efficiency is greatly improved.

The read-write control module sends the read data to the video compression control module, which compresses the received BLOCK data and writes the compressed data into the compressed data storage space (CMP_DATA).

In this embodiment, the YUV data in the FIFO array is read out faster, resulting in a shorter buffering time of the YUV data in the FIFO array. Therefore, the required FIFO capacity will be smaller than that of the traditional video compression system. According to project experience, the highest resolution At the rate of 1920*1200, the required FIFO depth is 4096, and the total required FIFO storage capacity is 192KB, which is much less than the traditional 768KB, thus greatly saving project costs and reducing the FIFO cost in traditional video compression systems. Issues such as timing constraints and packaging and manufacturing difficulties caused by excessive quantities.

This embodiment reduces the storage capacity required by the FIFO and saves FIFO by reducing the number of FIFOs in the traditional video compression system and increasing the bit width of each FIFO, as well as optimizing the readout process of the read control logic of the read and write control module. The occupied space on the chip reduces the project cost, reduces the timing constraints and packaging and manufacturing difficulties caused by the excessive number of FIFOs in traditional video compression systems, and improves the readout speed of video data and the speed of video compression.

In some implementations, the FIFO array module includes 24 FIFOs, and the FIFO array module is configured to set the 1st to 8th FIFOs to store Y component data, the 9th to 16th FIFOs to store U component data, and the 17th to 24th FIFOs. Each FIFO is set to store V component data, and the bit width of each FIFO is set to 16 bits to simultaneously store Y component or U component or V component data of two adjacent rows.

In the embodiment of this application, the FIFO array module includes 24 FIFOs, and the bit width of each FIFO is set to 16 bits, so as to ensure that the writing speed of video data will not be slowed down while increasing the video data reading speed.

In some embodiments, the read-write control module is specifically configured to discard the converted Y component, U component, and V component data according to the compressed format, and after completing the data discarding, read the retained Y component in each clock cycle , U component and V component data are written to their corresponding FIFOs in parallel for caching.

The read-write control module converts the format-converted YUV data according to the compression format (YUV444 or YUV422 or YUV420) issued by the CPU, discards the corresponding YUV data, and writes the retained YUV data into the FIFO array. For example: YUV422 compression format needs to retain all Y data and U/V data of even columns; YUV420 compression format needs to retain all Y data and U/V data of even rows and even columns; YUV444 compression format needs to retain all rows and all columns Y/U/V data. The specific writing process is: read the Y component, U component and V component data of the corresponding row and column at the same time in each clock cycle, and write the Y component, U component and V component data read at the same time into their respective corresponding The FIFO is cached. For example: within one clock cycle, the Y component, U component and V component data of the 1st row and 2nd column are simultaneously read, and correspondingly written to Y_FIFO_0, U_FIFO_0, V_FIFO_0.

In some implementations, the cache space adopts a ping-pong cache structure, including a first cache space and a second cache space;

The substrate management control chip is also configured to write the received RGB video data into the first cache space and the second cache space sequentially in a line manner;

The color space conversion module is also configured to sequentially read two adjacent rows of RGB video data from the first cache space and the second cache space, and convert the two adjacent rows of RGB video data into Y components, U components and V components in parallel. component data;

The read-write control module is also configured to discard the converted Y component, U component and V component data according to the compressed format, and after completing the data discarding, read two adjacent rows with the same column number in parallel in each clock cycle to retain The Y component, U component and V component data are written in parallel to their corresponding FIFOs for caching.

This embodiment will be described with reference to Figure 3. Most of the processes of this embodiment have been explained in detail in the previous embodiment and will not be described again. In this embodiment, only the differences will be explained.

In order to further speed up video data processing, the cache space adopts a ping-pong cache structure, including a first cache space (SOURCE_DATA_0) and a second cache space (SOURCE_DATA_1).

The baseboard management control chip writes the received RGB video data into the first cache space and the second cache space sequentially in rows. For example, writes the RGB video data in rows 0/2/4/6... into the SOURCE_DATA_0 address space. , write the RGB video data of lines 1/3/5/7... into the SPURCE_DATA_1 address space. After all the stored RGB video data is read out, the first cache space and the second cache space clear their respective cache spaces. to continue storing the next row of RGB video data.

The color space conversion module sequentially reads two adjacent rows of RGB video data from the first cache space and the second cache space, and converts the two adjacent rows of RGB video data into Y component, U component and V component data in parallel, For example, the color space conversion module reads the RGB video data of rows 0 and 1 from SOURCE_DATA_0 and SOURCE_DATA_1 in sequence, and converts the RGB video data of rows 0 and 1 into Y component, U component and V component data in parallel. This Because the RGB video data that needs to be converted increases from the previous 1 line to 2 lines, the number of adders and multipliers in the color space conversion module is correspondingly increased to meet the needs of parallel conversion.

The read-write control module discards the converted Y component, U component and V component data according to the compressed format, and after completing the data discarding, reads the reserved Y components of two adjacent rows with the same column number in parallel in each clock cycle , U component and V component data are written in parallel to their corresponding FIFOs for caching, that is, the Y component, U component and V component data reserved in two adjacent rows with the same column number are read simultaneously in each clock cycle and written simultaneously. The respective corresponding FIFOs are cached. For example, in the same clock cycle, write the 0th Y component of row 0 and the 0th Y component of row 1 together into Y_FIFO_NEW_0.

In this embodiment, on the premise that the video data readout speed of the read-write control module is accelerated, the read-write control module uses a double buffer space with a ping-pong structure and optimizes the conversion operation logic of the color space conversion module to enable the read-write control module to write updates in one clock cycle. More YUV video data improves the writing speed of video data, so that the subsequent video compression module can compress data faster and improve the video compression efficiency.

The accelerated writing speed of the read-write control module shortens the cache time of the original RGB data in the memory, thus reducing the cache space required. The SoC (System on Chip, system on chip) can use more memory storage space Assigned to the operating system and/or other modules to further improve the performance of the SoC system.

In some embodiments, the read-write control module is further specifically configured to, after receiving a read data request from the video compression control module, sequentially start from the corresponding FIFO in each clock cycle according to the compression format and the arrangement order of each FIFO in the FIFO array. The Y component or U component or V component data of the corresponding positions of two adjacent rows are read from the FIFO to form BLOCK data that meets the compression format requirements and sent to the video compression control module.

In some implementations, RGB video data is converted into Y component, U component and V component data according to the following formula:

Y＝0.257*R+0.504*G+0.098*B+16

U＝-0.148*R-0.291*G+0.439*B+128

V＝0.439*R-0.368*G-0.071*B+128,

Among them, R represents the R component in the RGB video data, G represents the G component in the RGB video data, and B represents the B component in the RGB video data.

Specifically, the traditional video compression system requires 9 multipliers and 9 adders. After the double buffer space of the ping-pong structure is adopted in this application, the number of multipliers and adders is correspondingly modified to 18.

In some implementations, the video compression system further includes a network card, and the network card is configured to read the compressed data from the compressed data storage space and send it to the remote end for remote display.

Based on the same inventive concept, according to another aspect of the present application, as shown in Figure 7, an embodiment of the present application also provides a video compression method for a substrate management control chip. Based on the above video compression system, the following steps are performed:

Step S101: The substrate management control chip writes the received RGB video data into the cache space in a line-by-line manner;

Step S103: The color space conversion module reads the RGB video data of each row from the cache space in sequence, and converts the RGB video data into Y component, U component and V component data;

Step S105: The FIFO array module sets the bit width of the FIFO based on the number of FIFOs so that the FIFO stores the Y component, U component, or V component data of two adjacent rows at the same time;

Step S107: The read-write control module reads the Y component, U component, and V component data at the corresponding position of each row in each clock cycle, and writes them in parallel to the corresponding FIFO for caching;

Step S109: After receiving the read data request from the video compression control module, the read-write control module reads the corresponding positions of two adjacent rows from the corresponding FIFO in each clock cycle according to the arrangement order of each FIFO in the FIFO array. The Y component or U component or V component data constitutes BLOCK data and is sent to the video compression control module;

Step S111: The video compression control module compresses the received BLOCK data and writes the compressed data into the compressed data storage space.

The embodiments of the present application at least have the following beneficial technical effects: by reducing the number of FIFOs in traditional video compression systems and increasing the bit width of each FIFO, and optimizing the readout process of the read control logic of the read-write control module, the FIFO The required storage capacity saves the space occupied by FIFO on the chip, reduces project costs, reduces timing constraints and packaging and manufacturing difficulties caused by the excessive number of FIFOs in traditional video compression systems, and improves the quality of video data. Readout speed and video compression speed; on the premise that the video data readout speed of the read-write control module is accelerated, the read-write control module uses a double buffer space with a ping-pong structure and optimizes the conversion operation logic of the color space conversion module to enable the read-write control module to pass in one The clock cycle writes more YUV video data, which improves the writing speed of video data, so that the subsequent video compression module can compress data faster and improve the video compression efficiency.

Another aspect of the embodiments of the present application also provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores computer-readable instructions that implement the above method steps when executed by a processor.

Based on the same inventive concept, according to another aspect of the present application, as shown in FIG. 8, an embodiment of the present application also provides a non-transitory computer-readable storage medium 40. The non-transitory computer-readable storage medium 40 stores Computer readable instructions 410 that when executed by a processor perform the above method.

Based on the same inventive concept, according to another aspect of the present application, as shown in Figure 9, an embodiment of the present application also provides a server 90, including the above video compression system 910.

The embodiments of this application may also include corresponding computer equipment. The computer device includes a memory, at least one processor, and computer-readable instructions stored in the memory and executable on the processor. When the processor executes the program, any one of the above methods is performed.

The memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as the program corresponding to the video compression method in the embodiment of the present application. directive/module. The processor executes various functional applications and data processing of the device by running non-volatile software programs, instructions and modules stored in the memory, that is, implementing the video compression method of the above method embodiment.

The memory may include a program storage area and a data storage area, where the program storage area may store an operating system and an application program required for at least one function; the storage data area may store data created according to use of the device, etc. In addition, the memory may include high-speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory optionally includes memory located remotely from the processor, and these remote memories may be connected to the local module through a network. Examples of the above-mentioned networks include but are not limited to the Internet, intranets, local area networks, mobile communication networks and combinations thereof.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits and steps have been described generally in terms of their functionality. Whether this functionality is implemented as software or hardware depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the functions in various ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments disclosed in the present application.

The above are exemplary embodiments disclosed in the present application, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed in the present application as defined in the claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. The embodiment numbers disclosed in the above embodiments of the present application are only for description and do not represent the advantages or disadvantages of the embodiments. In addition, although the elements disclosed in the embodiments of the present application may be described or claimed in individual form, they may also be understood as plural unless explicitly limited to the singular.

It will be understood that, as used herein, the singular form "a" and "an" are intended to include the plural form as well, unless the context clearly supports an exception. It will also be understood that as used herein, "and/or" is meant to include any and all possible combinations of one or more of the associated listed items.

Those of ordinary skill in the art should understand that the above discussion of any embodiments is only illustrative, and is not intended to imply that the scope of the disclosure of the embodiments of the present application (including the claims) is limited to these examples; under the ideas of the embodiments of the present application , the above embodiments or technical features in different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present application, which are not provided in details for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims (20)

1. A video compression system for substrate management control chip, which is characterized in that it includes a color space conversion module, a memory, a FIFO array module, a read-write control module, and a video compression control module. The memory includes a cache space and a compressed data storage space. , the FIFO array module includes multiple FIFOs, the FIFOs are used to store Y component or V component or U component data;

   The baseboard management control chip is configured to write the received RGB video data into the cache space in a line manner;

   The color space conversion module is configured to read each line of RGB video data from the cache space in sequence, and convert the RGB video data into Y component, U component and V component data;

   The FIFO array module is configured to correspondingly set the bit width of the FIFO based on the number of the FIFO so that the FIFO simultaneously stores Y component or U component or V component data of two adjacent rows;

   The read-write control module is configured to read the Y component, U component and V component data at the corresponding position in each clock cycle, and write them in parallel to the corresponding FIFO for caching;

   The read-write control module is also configured to, after receiving a read data request from the video compression control module, sequentially read adjacent FIFOs from the corresponding FIFO in each clock cycle according to the arrangement order of each FIFO in the FIFO array. The Y component, U component or V component data at the corresponding positions of the two rows form BLOCK data and send it to the video compression control module; and

   The video compression control module is configured to compress the received BLOCK data and write the compressed data into the compressed data storage space.
2. The system according to claim 1, characterized in that the FIFO array module includes 24 FIFOs, and the FIFO array module is configured to set the 1st to 8th FIFOs to store Y component data, the 9th to 16th FIFOs Set to store U component data, the 17th to 24th FIFOs are set to store V component data, and the bit width of each FIFO is set to 16 bits to simultaneously store Y component or U component or V component data of two adjacent rows.
3. The system according to claim 1, wherein the memory is a static random access memory, a synchronous dynamic random access memory or a double rate synchronous dynamic random access memory.
4. The system according to claim 2, characterized in that the read-write control module is specifically configured to discard the converted Y component, U component and V component data according to the compression format, and after completing the data discarding, in each Read the reserved Y component, U component and V component data in one clock cycle, and write them in parallel to their corresponding FIFOs for caching.
5. The system according to claim 2, characterized in that the read-write control module is specifically configured to read the converted Y component, U component and V component data that need to be retained according to the compressed format, and write the respective corresponding data in parallel. After the FIFO is cached, the unwritten Y component, U component and V component data are discarded.
6. The system according to claim 4, wherein the compression format includes at least one of YUV420 compression format, YUV422 compression format and YUV444 format.
7. The system according to claim 6, wherein the compression format is YUV422 compression format, and the read-write control module is specifically configured to retain all Y data and U data or V data of even columns.
8. The system according to claim 6, wherein the compression format is YUV420 compression format, and the read-write control module is specifically configured to retain all Y data and U data or V data of even rows and even columns.
9. The system according to claim 6, wherein the compression format is YUV444 compression format, and the read-write control module is specifically configured to retain Y data, U data or V data of all rows and all columns.
10. The system according to claim 2, characterized in that the cache space adopts a ping-pong cache structure and includes a first cache space and a second cache space;

    The substrate management control chip is further configured to write the received RGB video data into the first cache space and the second cache space sequentially in a line manner;

    The color space conversion module is also configured to sequentially read two adjacent rows of RGB video data from the first cache space and the second cache space, and convert the two adjacent rows of RGB video data into Y components in parallel. U component and V component data; and

    The read-write control module is also configured to discard the converted Y component, U component and V component data according to the compressed format, and after completing the data discarding, read two adjacent rows of the same column in parallel in each clock cycle. The Y component, U component and V component data retained by the number are written to their respective corresponding FIFOs in parallel for caching.
11. The system according to claim 2, wherein the read-write control module is further specifically configured to, after receiving a read data request from the video compression control module, read data according to the compression format and the FIFO array in each clock cycle. The arrangement sequence of each FIFO in the FIFO sequentially reads the Y component or U component or V component data of two adjacent rows at corresponding positions to form BLOCK data that meets the requirements of the compression format and sends it to the video compression control module.
12. The system according to claim 2, characterized in that the RGB video data is converted into Y component, U component and V component data according to the following formula:

    Y＝0.257*R+0.504*G+0.098*B+16

    U＝-0.148*R-0.291*G+0.439*B+128

    V＝0.439*R-0.368*G-0.071*B+128,

    Among them, R represents the R component in the RGB video data, G represents the G component in the RGB video data, and B represents the B component in the RGB video data.
13. The system according to claim 2, further comprising a network card configured to read compressed data from the compressed data storage space and send it to a remote end for remote display.
14. A video compression method for a substrate management control chip, characterized in that it is executed based on the video compression system according to any one of claims 1 to 7, including:

    The baseboard management control chip writes the received RGB video data into the buffer space in rows;

    The color space conversion module sequentially reads the RGB video data of each row from the cache space, and converts the RGB video data into Y component, U component and V component data;

    The FIFO array module sets the bit width of the FIFO correspondingly based on the number of FIFOs so that the FIFO stores the Y component or U component or V component data of two adjacent rows at the same time;

    The read-write control module reads the Y component, U component and V component data at the corresponding position of each row in each clock cycle, and writes them in parallel to the corresponding FIFO for caching;

    After receiving the read data request from the video compression control module, the read-write control module reads two adjacent rows from the corresponding FIFO in each clock cycle according to the arrangement order of each FIFO in the FIFO array. The Y component or U component or V component data of the position constitutes BLOCK data and is sent to the video compression control module; and

    The video compression control module compresses the received BLOCK data and writes the compressed data into the compressed data storage space.
15. The method according to claim 14, characterized in that the FIFO array module includes 24 FIFOs, and the FIFO array module sets the bit width of the FIFO correspondingly based on the number of FIFOs so that the FIFO stores two adjacent FIFOs at the same time. The Y component, U component, or V component data of the row, including:

    Set the 1st to 8th FIFOs to store Y component data, the 9th to 16th FIFOs to store U component data, the 17th to 24th FIFOs to store V component data, and set the bit width of each FIFO to 16 bits to simultaneously store the Y component or U component or V component data of two adjacent rows.
16. A non-transitory computer-readable storage medium, the non-transitory computer-readable storage medium stores computer-readable instructions, wherein the computer-readable instructions are implemented when executed by a processor:

    The baseboard management control chip writes the received RGB video data into the buffer space in rows;

    The color space conversion module sequentially reads the RGB video data of each row from the cache space, and converts the RGB video data into Y component, U component and V component data;

    The FIFO array module sets the bit width of the FIFO correspondingly based on the number of FIFOs so that the FIFO stores the Y component or U component or V component data of two adjacent rows at the same time;

    The read-write control module reads the Y component, U component and V component data at the corresponding position of each row in each clock cycle, and writes them in parallel to the corresponding FIFO for caching;

    After receiving the read data request from the video compression control module, the read-write control module reads two adjacent rows from the corresponding FIFO in each clock cycle according to the arrangement order of each FIFO in the FIFO array. The Y component or U component or V component data of the position constitutes BLOCK data and is sent to the video compression control module; and

    The video compression control module compresses the received BLOCK data and writes the compressed data into the compressed data storage space.
17. The non-transitory computer-readable storage medium according to claim 16, characterized in that the FIFO array module sets the bit width of the FIFO correspondingly based on the number of FIFOs so that the FIFO stores the Y of two adjacent rows at the same time. Component or U component or V component data, including:

    Set the 1st to 8th FIFOs to store Y component data, the 9th to 16th FIFOs to store U component data, the 17th to 24th FIFOs to store V component data, and set the bit width of each FIFO to 16 bits to simultaneously store the Y component or U component or V component data of two adjacent rows.
18. A server, characterized in that the server is used in a video compression system of a substrate management control chip. The system includes a color space conversion module, a memory, a FIFO array module, a read-write control module, and a video compression control module. The memory Including cache space and compressed data storage space, the FIFO array module includes multiple FIFOs, the FIFOs are used to store Y component or V component or U component data;

    The baseboard management control chip is configured to write the received RGB video data into the cache space in a line manner;

    The color space conversion module is configured to read each line of RGB video data from the cache space in sequence, and convert the RGB video data into Y component, U component and V component data;

    The FIFO array module is configured to correspondingly set the bit width of the FIFO based on the number of the FIFO so that the FIFO simultaneously stores Y component or U component or V component data of two adjacent rows;

    The read-write control module is configured to read the Y component, U component and V component data at the corresponding position in each clock cycle, and write them in parallel to the corresponding FIFO for caching;

    The read-write control module is also configured to, after receiving a read data request from the video compression control module, sequentially read adjacent FIFOs from the corresponding FIFO in each clock cycle according to the arrangement order of each FIFO in the FIFO array. The Y component, U component or V component data at the corresponding positions of the two rows form BLOCK data and send it to the video compression control module; and

    The video compression control module is configured to compress the received BLOCK data and write the compressed data into the compressed data storage space.
19. The server according to claim 18, characterized in that the FIFO array module includes 24 FIFOs, and the FIFO array module is configured to set the 1st to 8th FIFOs to store Y component data, the 9th to 16th FIFOs Set to store U component data, the 17th to 24th FIFOs are set to store V component data, and the bit width of each FIFO is set to 16 bits to simultaneously store Y component or U component or V component data of two adjacent rows.
20. The server according to claim 18, characterized in that the read-write control module is specifically configured to discard the converted Y component, U component and V component data according to the compression format, and after completing the data discarding, in each Read the reserved Y component, U component and V component data in one clock cycle, and write them in parallel to their corresponding FIFOs for caching.

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