CN114428595A

CN114428595A - Image processing method, image processing device, computer equipment and storage medium

Info

Publication number: CN114428595A
Application number: CN202210108381.XA
Authority: CN
Inventors: 朱道林; 夏群兵; 孙雪强
Original assignee: Shenzhen Aixiesheng Technology Co Ltd
Current assignee: Shenzhen Aixiesheng Technology Co Ltd
Priority date: 2022-01-28
Filing date: 2022-01-28
Publication date: 2022-05-03
Anticipated expiration: 2042-01-28
Also published as: CN114428595B

Abstract

The application relates to an image processing method, an image processing device, a computer device and a storage medium. The method comprises the following steps: reading row compression data of a plurality of image block compression data from a plurality of storage chips based on a plurality of queue serial peripheral interfaces in response to an image display control instruction sent by a main control chip; writing the read line compressed data into a memory according to a preset writing frequency, and reading the line compressed data of the plurality of image block compressed data from the memory according to the preset reading frequency; the reading frequency is greater than the writing frequency; respectively caching the line compression data read from the memory into a plurality of buffers, and decompressing the line compression data in the buffers to obtain a plurality of decompressed partial image line data; splicing partial image line data corresponding to the same line of the target image to obtain image line data of each line of the target image; and outputting the image line data of each line to an industrial screen to display the target image. The method can reduce the cost.

Description

Image processing method, image processing device, computer equipment and storage medium

Technical Field

The present application relates to the field of image processing technologies, and in particular, to an image processing method and apparatus, a computer device, and a storage medium.

Background

With the rapid development of science and technology, the liquid crystal display brings great convenience to daily life and work, and besides a common display used in daily office work or life, the liquid crystal display also has a liquid crystal display screen suitable for industry, namely an industrial screen.

In order to ensure the image display effect, a main control chip of the industrial screen is generally modified to integrate a memory in the main control chip to store an image to be displayed. However, the modification of the main control chip to integrate the memory results in higher cost.

Disclosure of Invention

In view of the above, it is necessary to provide an image processing method, an apparatus, a computer device, a computer readable storage medium, and a computer program product capable of reducing cost in view of the above technical problems.

In a first aspect, the present application provides an image processing method. The method comprises the following steps:

reading row compression data of a plurality of image block compression data from a plurality of storage chips based on a plurality of queue serial peripheral interfaces in response to an image display control instruction sent by a main control chip; the compressed data of the plurality of image blocks is the compressed data of the plurality of image blocks obtained by partitioning the target image; each image block compressed data comprises a plurality of lines of compressed data;

writing the read line compression data into a memory according to a preset writing frequency, and reading the line compression data of the image block compression data from the memory according to the preset reading frequency; the read frequency is greater than the write frequency;

respectively caching the line compression data read from the memory into a plurality of buffers, and decompressing the line compression data in the buffers to obtain a plurality of decompressed partial image line data;

splicing the partial image line data corresponding to the same line of the target image to obtain image line data of each line of the target image;

and outputting the image line data of each line to an industrial screen to display the target image.

In one embodiment, the memory chip is a flash memory chip; the method also comprises an image compression data burning step; the burning step of the image compressed data comprises the following steps:

partitioning a target image to obtain a plurality of image blocks;

respectively compressing the data of the plurality of image blocks according to a preset compression mode to obtain a plurality of image block compressed data;

and respectively burning the plurality of image block compressed data to a plurality of flash memory chips.

In one embodiment, the plurality of memory chips includes a first memory chip and a second memory chip; the plurality of queue serial peripheral interfaces comprises a first queue serial peripheral interface and a second queue serial peripheral interface; the reading of the row compression data of the plurality of image block compression data from the plurality of memory chips based on the plurality of queue serial peripheral interfaces in response to the image display control instruction sent by the main control chip comprises:

reading the current row compressed data of the first image block compressed data from the first storage chip through a first queue serial peripheral interface in response to an image display control instruction sent by a main control chip; the current line compressed data of the first image block compressed data is the line compressed data to be read currently in the first image block compressed data;

after the reading of the compressed data of the current line of the compressed data of the first image block is finished, reading the compressed data of the current line of the compressed data of the second image block from the second storage chip through a second queue serial peripheral interface;

after the reading of the current line compressed data of the second image block compressed data is finished, taking the next line compressed data of the first image block compressed data as the current line compressed data of the first image block compressed data, and taking the next line compressed data of the second image block compressed data as the current line compressed data of the second image block compressed data, so as to return to read the current line compressed data of the first image block compressed data from the first storage chip through the first queue serial peripheral interface for continuous execution until the line compressed data in the first image block compressed data and the line compressed data in the second image block compressed data are all read.

In one embodiment, the plurality of memory chips includes a first memory chip and a second memory chip; the buffers include a first buffer and a second buffer; the method for reading the line compression data of the compressed data of the plurality of image blocks from the memory according to the preset reading frequency comprises the following steps:

alternately reading the line compression data from the first memory chip and the line compression data from the second memory chip from the memory according to a preset reading frequency;

the caching the line compression data read from the memory into a plurality of buffers, respectively, and decompressing the line compression data in the buffers to obtain a plurality of decompressed partial image line data includes:

in the process of alternately reading the line compression data of different memory chips from the memory, alternately caching the line compression data read from the memory from a first memory chip into a first buffer in sequence, and caching the line compression data read from the memory from a second memory chip into a second buffer in sequence;

when the newly added cache line compression data exists in the first buffer and the second buffer, decompressing the newly added cache line compression data to obtain decompressed partial image line data corresponding to each line compression data in the first memory chip and the second memory chip respectively;

the splicing the partial image line data corresponding to the same line of the target image to obtain the image line data of each line of the target image comprises:

and splicing the decompressed partial image line data which correspond to the first storage chip and the second storage chip and belong to the same line to obtain the image line data of each line of the target image.

In one embodiment, the caching the line compression data read from the memory into a plurality of buffers respectively comprises:

acquiring a compression mode identifier corresponding to the line compression data;

determining a target cache size corresponding to the compression mode identification;

allocating a plurality of buffers according with the target buffer size, and respectively buffering the line compression data read from the memory into the allocated plurality of buffers.

In one embodiment, the method is performed by an acceleration engine apparatus; the acceleration engine device comprises a universal asynchronous receiving and transmitting interface used for being in butt joint with the main control chip and a queue serial peripheral interface used for being in butt joint with the storage chip; the reading of the row compression data of the plurality of image block compression data from the plurality of memory chips based on the plurality of queue serial peripheral interfaces in response to the image display control instruction sent by the main control chip comprises:

the acceleration engine device receives an image display control instruction sent by a main control chip based on a universal asynchronous receiving and transmitting interface, and reads row compression data of a plurality of image block compression data from a plurality of storage chips based on a plurality of queue serial peripheral interfaces in response to the image display control instruction.

In a second aspect, the present application further provides an image processing apparatus. The device comprises:

the response module is used for responding to an image display control instruction sent by the main control chip and reading row compressed data of the plurality of image block compressed data from the plurality of storage chips on the basis of the plurality of queue serial peripheral interfaces; the compressed data of the plurality of image blocks is the compressed data of the plurality of image blocks obtained by partitioning the target image; each image block compressed data comprises a plurality of lines of compressed data;

the decompression module is used for writing the read line compressed data into a memory according to a preset writing frequency and reading the line compressed data of the plurality of image block compressed data from the memory according to a preset reading frequency; the read frequency is greater than the write frequency; respectively caching the line compression data read from the memory into a plurality of buffers, and decompressing the line compression data in the buffers to obtain a plurality of decompressed partial image line data;

the splicing module is used for splicing the partial image line data corresponding to the same line of the target image to obtain image line data of each line of the target image; and outputting the image line data of each line to an industrial screen to display the target image.

In a third aspect, the present application also provides a computer device. The computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor realizes the steps of the method of the embodiments of the application when executing the computer program.

In a fourth aspect, the present application further provides a computer-readable storage medium. The computer readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps of the method according to embodiments of the present application.

In a fifth aspect, the present application further provides a computer program product. The computer program product comprises a computer program which, when executed by a processor, performs the steps of the method according to embodiments of the present application.

According to the image processing method, the device, the computer equipment and the storage medium, in response to an image display control instruction sent by the main control chip, the row compressed data of the plurality of image block compressed data are read from the plurality of storage chips based on the plurality of queue serial peripheral interfaces, the image compressed data in the plurality of storage chips are read based on the plurality of interfaces, the transmission speed of the image compressed data can be improved, the requirements of the image block compressed data obtained after blocking on the capacity and the transmission bandwidth of the storage chips are smaller than those of uncompressed data, and the storage and transmission costs of the storage chips can be reduced. Writing the read line compressed data into a memory according to a preset writing frequency, and reading the line compressed data of the plurality of image block compressed data from the memory according to the preset reading frequency; the reading frequency is greater than the writing frequency, so that the problem of data overflow caused by overhigh writing clock frequency can be avoided, and the stability of image compression data transmission is ensured. The line compression data read from the memory are respectively cached in a plurality of buffers, and the line compression data in the buffers are decompressed to obtain a plurality of decompressed partial image line data, and the line compression data are cached in the buffers, so that the speed of decompression processing can be ensured. Splicing partial image line data corresponding to the same line of the target image to obtain image line data of each line of the target image; and outputting the image line data of each line to an industrial screen to display a target image. The data transmission stability and the data processing speed can be ensured by storing the image to be displayed by the industrial screen through the external storage chip, so that the effect of the industrial screen is ensured, and compared with the traditional method of integrating the memory in the main control chip, the cost is greatly reduced.

Drawings

FIG. 1 is a diagram of an exemplary embodiment of an image processing method;

FIG. 2 is a flow diagram illustrating a method for image processing according to one embodiment;

FIG. 3 is a schematic diagram of a memory in one embodiment;

FIG. 4 is a diagram of decompressing compressed line data in one embodiment;

FIG. 5 is an architecture diagram of an image processing method in one embodiment;

FIG. 6 is a block diagram showing the configuration of an image processing apparatus according to an embodiment;

FIG. 7 is a diagram illustrating an internal structure of a computer device according to an embodiment;

FIG. 8 is a diagram illustrating an internal structure of a computer device according to an embodiment.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of and not restrictive on the broad application.

The image processing method provided by the embodiment of the application can be applied to the application environment shown in fig. 1. The acceleration engine device 102 may read the row compression data of the plurality of image block compression data from the plurality of memory chips 106 based on the plurality of queued serial peripheral interfaces in response to the image display control instruction sent by the master chip 104. The acceleration engine device 102 may write the read line compressed data into the memory at a preset write frequency, and read the line compressed data of the plurality of tile compressed data from the memory at a preset read frequency. The acceleration engine device 102 may buffer the line compression data read from the memory into a plurality of buffers, and decompress the line compression data in the buffers to obtain a plurality of decompressed partial image line data. The acceleration engine device 102 may splice the partial image line data corresponding to the same line of the target image to obtain image line data of each line of the target image; the acceleration engine device can output the image line data of the rows into the industrial screen to display the target image.

In one embodiment, as shown in fig. 2, an image processing method is provided, which is described by taking the method as an example applied to the acceleration engine device in fig. 1, and includes the following steps:

step 202, in response to the image display control instruction sent by the main control chip, reading the row compressed data of the plurality of image block compressed data from the plurality of memory chips based on the plurality of queue serial peripheral interfaces.

The plurality of image block compressed data are compressed data of a plurality of image blocks obtained by partitioning the target image. Each of the image block compressed data includes a plurality of lines of compressed data. The main control chip is a core component of a mainboard or a hard disk of the industrial screen control system, is a bridge for connecting all devices and is a brain for controlling the industrial screen to operate. The image display control instruction is for instructing the acceleration engine apparatus to execute the image processing method. It can be understood that the image display control instruction is used for instructing the acceleration engine device to read the image block compressed data from the storage chip and output the image line data of each line of the target image obtained by decompression to the industrial screen. The queue serial peripheral interface (QSPI, Queued SPI) is used for realizing queue transmission, and the queue serial peripheral interface can be used for transmitting a transmission queue containing 16 or 8-bit data at a time, so that once transmission is started, and the transmission is finished without the intervention of a central processing unit, thereby greatly improving the transmission efficiency. The memory chip is a chip having a memory function for storing image block compressed data.

Specifically, the main control chip may generate an image display control instruction and transmit the image display control instruction to the acceleration engine device. The acceleration engine device may read line compression data of the plurality of image block compression data from the plurality of memory chips through the plurality of queue serial peripheral interfaces, respectively, in response to the image display control instruction. The queue serial peripheral interfaces correspond to the memory chips one by one.

In one embodiment, the acceleration engine device may read row compression data of the plurality of image block compression data in parallel from the plurality of memory chips based on the plurality of queue serial peripheral interfaces in response to an image display control instruction transmitted by the main control chip.

Step 204, writing the read row compressed data into a memory according to a preset writing frequency, and reading the row compressed data of the plurality of image block compressed data from the memory according to the preset reading frequency; and respectively caching the line compression data read from the memory into a plurality of buffers, decompressing the line compression data in the buffers to obtain a plurality of decompressed partial image line data.

Wherein the reading frequency is greater than the writing frequency. The write frequency is the frequency at which the read line compression data is written to the memory. The read frequency is a frequency of reading line compressed data of the plurality of image block compressed data from the memory. The memory is a storage unit for storing programs and various data information. The buffer is used to temporarily store the compressed data. The partial image line data is partial data of the image line data. It is understood that when the image is divided into blocks, one entire image line data may be divided into a plurality of partial image line data.

Specifically, the acceleration engine apparatus may write the read line compressed data into the memory at a preset write frequency, and read the line compressed data of the plurality of image block compressed data from the memory at a preset read frequency. The memory may be an asynchronous first-in first-out memory for implementing a clock domain crossing. It will be appreciated that the order in which the line compressed data is written to the memory is the same as the order in which the line compressed data is read from the memory, i.e. first in first out. The acceleration engine device may buffer the line compression data read from the memory into a plurality of buffers, and decompress the line compression data in the buffers to obtain a plurality of decompressed partial image line data.

In one embodiment, a schematic diagram of a memory as shown in FIG. 3. The memory may be an asynchronous first-in first-out memory. The acceleration engine device can respectively write the image block compressed data into the asynchronous first-in first-out memory by using the preset write frequency and read the image block compressed data from the asynchronous memory by using the larger preset read frequency, thereby realizing the switching across clock domains and avoiding the problem of data overflow caused by the large write frequency. The fifo is a data buffer that implements fifo. The FIFO memory has no external read-write address, and a user can design write enable and read enable according to full and empty signals to write/read the FIFO memory, and the FIFO memory cannot be written into the FIFO memory when the FIFO memory is full and cannot read data when the FIFO memory is empty. Asynchronous fifo memories are used to implement transfer across clock domains.

In one embodiment, the buffer may be a line buffer. The acceleration engine device may buffer the line compression data read from the memory into a plurality of line buffers, respectively. The line buffer is used for buffering each line of compressed data in the image block compressed data. It is understood that one line buffer may completely buffer one line of compressed data.

Step 206, splicing partial image line data corresponding to the same line of the target image to obtain image line data of each line of the target image; and outputting the image line data of each line to an industrial screen to display a target image.

The target image is an image corresponding to the image block compressed data. An industrial screen is a display screen applied to an industrial control process or device. It will be appreciated that most industrial environments are those surrounded by glare, and industrial screens are required to support clear and accurate visual effects from multiple angles in a glare environment. The operating temperature of the industrial screen is higher than that of the common display screen. The image line data is line data of the target image. It will be appreciated that the data for an image may be identified in the form of a matrix, with the rows in the matrix being the image row data.

Specifically, the acceleration engine device may stitch partial image line data corresponding to the same line of the target image to obtain image line data of each line of the target image. The acceleration engine device can output the image line data of each line to the driving chip so as to trigger the driving chip to drive the industrial screen to display the target image. The driving chip is used for driving the industrial screen to display images.

The image processing method is used for responding to an image display control instruction sent by a main control chip, and reading row compressed data of a plurality of image block compressed data from a plurality of storage chips based on a plurality of queue serial peripheral interfaces, wherein the plurality of image block compressed data are compressed data of a plurality of image blocks obtained after a target image is partitioned; each image block compressed data comprises a plurality of lines of compressed data; writing the read line compressed data into a memory according to a preset writing frequency, and reading the line compressed data of the plurality of image block compressed data from the memory according to the preset reading frequency; the reading frequency is greater than the writing frequency; respectively caching the line compression data read from the memory into a plurality of buffers, and decompressing the line compression data in the buffers to obtain a plurality of decompressed partial image line data; splicing partial image line data corresponding to the same line of the target image to obtain image line data of each line of the target image; and outputting the image line data of each line to an industrial screen to display a target image. The method has the advantages that the transmission speed of the image compressed data can be improved by reading the image compressed data in the plurality of memory chips based on the plurality of interfaces, the requirements of the image block compressed data obtained after blocking on the capacity and the transmission bandwidth of the memory chips are smaller than those of uncompressed data, the storage and transmission costs of the memory chips can be reduced, the compressed data are cached by the plurality of buffers, the data processing speed can be further improved, the operation speed of the industrial screen control system is not influenced, meanwhile, the low-cost and small-capacity memory chips are adopted, and the cost of the industrial screen control system is reduced.

In one embodiment, the memory chip is a flash memory chip; the method also comprises a step of burning the image compression data; the burning step of the image compressed data comprises the following steps: partitioning a target image to obtain a plurality of image blocks; respectively compressing the data of the plurality of image blocks according to a preset compression mode to obtain a plurality of image block compressed data; and respectively burning the compressed data of the plurality of image blocks to a plurality of flash memory chips.

The FLASH memory chip (FLASH) is a mobile storage product, and can be used for storing data files in any format.

Specifically, a user may block a target image through a computer device to obtain a plurality of image blocks. A user can respectively compress the data of the image blocks through computer equipment according to a preset compression mode to obtain the compressed data of the image blocks, and the compressed data of the image blocks are respectively burned into the flash memory chips. It can be understood that the image block compressed data of the target image is in one-to-one correspondence with the flash memory chips.

In one embodiment, the compression mode may be one of a half-image compression mode, a two-thirds image compression mode, and a one-third image compression mode. For example, the image half compression method may be YUV 420; the two-thirds compression mode of the image can be YUV 422; the image one third compression may be RGB 332. Where YUV420 is a set of four luminance components in common. YUV422 is a set of luminance components shared by every two luminance components. RGB332 is 3 bits for the red component, 2 bits for the green component, and 2 bits for the blue component. The one-half image compression method is a method in which the compressed image data size after compression is one-half of the image data before compression. The one-third compression method of an image is a method in which the compressed data size of the image after compression is one third of the image data before compression. The two-thirds compression method of an image is a method in which the compressed data size of the image after compression is two thirds of the image data before compression.

In one embodiment, a user may convert the color format of the data of the image block from a base color format to a target format via a computer device. The target format includes a luminance component and a chrominance component. The chroma components in the target format may be an orange degree component (Co) and a green degree component (Cg). It is to be understood that the target format may be a YCoCg format. Where Y is the luminance, Co is the orange level, and Cg is the green level. A user can compress the data of the image block in the target format according to a display stream compression mode (DSC) by computer equipment in a preset compression ratio to obtain image block compressed data, and the image block compressed data is burned into the flash memory chip. The acceleration engine device can decompress the line compression data by adopting a display stream decompression mode to obtain partial image line data in a decompressed base color format. The preset compression ratio may be one third, and the display stream compression mode may be a display stream one third compression mode.

Wherein the base color format comprises a red component, a green component and a blue component. Display Stream Compression (DSC) is an industry-level video Stream Compression standard that can compress and decompress data at extremely fast speeds and transmit to a single Display screen without significant loss of viewing screen quality.

In one embodiment, the acceleration engine device may decompress the image block compressed data by a display stream compression encoder.

In one embodiment, a user may divide a target image equally into two image blocks via a computer device. For example, the computer device may equally split each image line data of the target image, equally divide the target image into two image blocks, each image block including one-half of the image line data.

In one embodiment, a user may mark the compression mode identification for the image block compressed data through a computer device. It can be understood that the user can set the compression mode of the image block by himself, and the acceleration engine device can determine the compression mode of the compressed data of the image block according to the compression mode identification.

In one embodiment, the compression mode corresponding to the compressed data of each image block may be different. The acceleration engine apparatus may determine a compression manner of the compressed data of each image block to perform the decompression processing.

In the embodiment, a target image is partitioned to obtain a plurality of image blocks; respectively compressing the data of the plurality of image blocks according to a preset compression mode to obtain a plurality of image block compressed data; the compressed data of the image blocks of the target image are respectively burned into the flash memory chips, so that the requirement on the memory capacity of the flash memory chips is smaller, and the cost can be reduced.

In one embodiment, the plurality of memory chips includes a first memory chip and a second memory chip; the plurality of queue serial peripheral interfaces comprise a first queue serial peripheral interface and a second queue serial peripheral interface; in response to an image display control instruction sent by the main control chip, reading row compression data of a plurality of image block compression data from a plurality of storage chips based on a plurality of queue serial peripheral interfaces comprises: reading the current row compressed data of the first image block compressed data from the first storage chip through the first queue serial peripheral interface in response to an image display control instruction sent by the main control chip; the current line compressed data of the first image block compressed data is the line compressed data to be read currently in the first image block compressed data; after the reading of the compressed data of the current line of the compressed data of the first image block is finished, reading the compressed data of the current line of the compressed data of the second image block from the second storage chip through the second queue serial peripheral interface; after the reading of the current line compressed data of the second image block is finished, taking the next line compressed data of the first image block as the current line compressed data of the first image block, taking the next line compressed data of the second image block as the current line compressed data of the second image block, and returning to the step of reading the current line compressed data of the first image block from the first storage chip through the first queue serial peripheral interface to continue to execute until the line compressed data in the compressed data of the first image block and the line compressed data in the compressed data of the second image block are completely read.

And the current line compressed data of the second image block compressed data is the line compressed data to be read currently in the second image block compressed data. The first queue serial peripheral interface corresponds to a first memory chip. The second queue serial peripheral interface corresponds to a second memory chip.

Specifically, the acceleration engine device may generate a timing sequence for reading the first memory chip and the second memory chip in response to an image display control instruction sent by the main control chip, and read the current row compressed data of the first image block compressed data from the first memory chip through the first queue serial peripheral interface. The acceleration engine device may read the current row compressed data of the second image block compressed data from the second memory chip through the second queue serial peripheral interface after the current row compressed data of the first image block compressed data is completely read. The acceleration engine device may, after the reading of the current line compressed data of the second image block compressed data is completed, use the next line compressed data of the first image block compressed data as the current line compressed data of the first image block compressed data, and use the next line compressed data of the second image block compressed data as the current line compressed data of the second image block compressed data, so as to return to read the current line compressed data of the first image block compressed data from the first memory chip through the first queue serial peripheral interface for continuing execution until the line compressed data in the first image block compressed data and the line compressed data in the second image block compressed data are all read.

In this embodiment, the acceleration engine device may alternately read the line compressed data of the first image block compressed data and the line compressed data of the second image block compressed data from the first memory chip and the second memory chip, respectively, and ensure the reading speed of the line compressed data.

In one embodiment, the plurality of memory chips includes a first memory chip and a second memory chip; the buffers comprise a first buffer and a second buffer; the method for reading the line compression data of the plurality of image block compression data from the memory according to the preset reading frequency comprises the following steps: alternately reading the line compression data from the first memory chip and the line compression data from the second memory chip from the memory according to a preset reading frequency; respectively caching the line compression data read from the memory into a plurality of buffers, decompressing the line compression data in the buffers to obtain a plurality of decompressed partial image line data, including: in the process of alternately reading the line compression data of different memory chips from the memory, alternately caching the line compression data read from the memory from a first memory chip into a first buffer in sequence, and caching the line compression data read from the memory from a second memory chip into a second buffer in sequence; when the line compression data of the newly added buffer memory exists in the first buffer and the second buffer, decompressing the line compression data of the newly added buffer memory to obtain decompressed partial image line data corresponding to each line compression data in the first memory chip and the second memory chip respectively; splicing partial image line data of the same line corresponding to the target image to obtain image line data of each line of the target image comprises the following steps: and splicing the decompressed partial image line data which correspond to the first storage chip and the second storage chip and belong to the same line to obtain the image line data of each line of the target image.

Specifically, the acceleration engine apparatus may alternately read the line compression data from the first memory chip and the line compression data from the second memory chip from the memory by determining whether the first buffer and the second buffer are in a readable state. The acceleration engine device may alternately buffer the line compression data read from the memory from the first memory chip into the first buffer and the line compression data read from the memory from the second memory chip into the second buffer by determining whether the first buffer and the second buffer are in a writable state during alternately reading the line compression data of different memory chips from the memory. The acceleration engine device may read the line compression data of the newly added buffer and decompress the line compression data of the newly added buffer each time when the line compression data of the newly added buffer exists in the first buffer and the second buffer, so as to obtain decompressed partial image line data corresponding to each line compression data in the first memory chip and the second memory chip, respectively. The acceleration engine device may splice the decompressed partial image line data corresponding to the first memory chip and the second memory chip and belonging to the same line to obtain image line data of each line of the target image.

In one embodiment, if the first buffer is in a readable state and the second buffer is in a writable state, the acceleration engine device may sequentially buffer the line compressed data from the second memory chip read from the memory into the second buffer and read the line compressed data from the first memory chip from the first buffer. If the second buffer is in a readable state and the first buffer is in a writable state, the acceleration engine device may buffer the line compression data read from the memory from the first memory chip into the first buffer in order and read the line compression data from the second memory chip from the second buffer.

In one embodiment, a schematic diagram of decompressing line compressed data is shown in FIG. 4. The buffer may be a line buffer. The plurality of buffers are a first line buffer and a second line buffer. The acceleration engine device may write the row compressed data read from the first memory chip and the second memory chip into the asynchronous first-in first-out memory through a first queue serial peripheral interface interfacing with the first memory chip and a second queue serial peripheral interface interfacing with the second memory chip. The acceleration engine device may buffer the line compression data read from the asynchronous fifo memory into the first line buffer and the second line buffer, respectively, and decompress the line compression data newly buffered in the first line buffer and the second line buffer by the display stream compression encoder to obtain decompressed image data.

In this embodiment, the line compressed data is alternately cached by two buffers, the line compressed data newly cached in the buffer is decompressed, and the high-speed data stream is processed by the low-speed buffer, so that the speed of data transmission and processing is ensured and the cost is reduced.

In one embodiment, respectively buffering the line compressed data read from the memory into a plurality of buffers comprises: acquiring a compression mode identifier corresponding to the line compression data; determining the size of a target cache corresponding to the compression mode identifier; a plurality of buffers conforming to the target buffer size are allocated, and the line compression data read from the memory are buffered in the allocated buffers, respectively.

And the compression identifier is used for indicating a compression mode corresponding to the compressed data of the image block. It can be understood that, a user may compress the image block at a fixed compression ratio in a compression manner through the computer device, and the size of the compressed data of the image block after compression is consistent with the compression ratio corresponding to the image compression manner.

Specifically, the acceleration engine device may obtain a compression mode identifier corresponding to the line compression data. The acceleration engine device may determine a target cache size corresponding to the compression mode identifier, allocate a plurality of buffers that meet the target cache size, and cache the line compression data read from the memory into the allocated plurality of buffers, respectively. It will be appreciated that the acceleration engine device may buffer a line of compressed data into a buffer. The target buffer size is equal to the size of each line of compressed data. If the compression mode identifier carried by each image block compressed data is different, that is, the line compressed data of each image block compressed data is different, the acceleration engine device may allocate buffers of different sizes for the line compressed data of each image block compressed data.

In one embodiment, the acceleration engine device may identify in a compressed manner, determine the size of each line of display compressed data, i.e., the target cache size. The acceleration engine device may decompress the image compression data in a decompression manner corresponding to the image compression manner indicated by the compression manner identification.

In one embodiment, the maximum memory capacity of the plurality of buffers may be the same. The accelerator engine device may divide the plurality of buffers into memories having the same size as the target cache size according to the target cache size to cache the line compression data.

In one embodiment, the maximum memory capacity of the plurality of buffers may be different, and the acceleration engine device may directly match the maximum memory capacity of the buffers to the target cache size. If a buffer with the maximum memory capacity equal to the target cache size exists, the acceleration engine device may adopt the buffer corresponding to the maximum memory capacity; if there is no buffer with the maximum memory size equal to the target cache size, the accelerator engine device may use a buffer with a larger maximum memory size and divide the memory with the size equal to the target cache size for the buffer to cache the line compression data. It can be understood that, if the target image has two image block compressed data, and the compression mode corresponding to the image block compressed data is one-third of the image compression mode, the accelerator engine device may allocate a buffer with a maximum memory capacity of one-sixth of the size of the image line data.

In this embodiment, a compression mode identifier corresponding to row compression data is obtained; determining the size of a target cache corresponding to the compression mode identifier; the method comprises the steps of allocating a plurality of buffers which accord with the target buffer size, caching the line compression data read from the memory into the allocated buffers respectively, and adaptively allocating the buffers according to the target buffer size corresponding to the compression mode identification.

In one embodiment, the method is performed by an acceleration engine device; the acceleration engine device comprises a universal asynchronous receiving and transmitting interface used for being in butt joint with the main control chip and a queue serial peripheral interface used for being in butt joint with the storage chip; in response to an image display control instruction sent by the main control chip, reading row compression data of a plurality of image block compression data from a plurality of storage chips based on a plurality of queue serial peripheral interfaces comprises: the acceleration engine device receives an image display control instruction sent by the main control chip based on the universal asynchronous receiving and transmitting interface, and reads row compression data of a plurality of image block compression data from a plurality of storage chips based on a plurality of queue serial peripheral interfaces in response to the image display control instruction.

The universal asynchronous receiving and transmitting transmission (UART interface) is used for realizing asynchronous serial communication, characters are used as transmission units, one bit is transmitted in sequence, the time interval between two characters in communication is not fixed, and the time interval between two adjacent bits in the same character is fixed.

Specifically, the acceleration engine device may receive an image display control instruction sent by the main control chip through the uart interface, generate a timing sequence for reading the memory chip in response to the image display control instruction, and read row compression data of the plurality of image block compression data from the plurality of memory chips through the plurality of queue serial peripheral interfaces.

In one embodiment, the architecture diagram of the image processing method is shown in FIG. 5. The acceleration engine device can receive an image reading instruction sent by the main control chip through the first interface, respond to the image reading instruction, respectively read image block compressed data from the first flash memory chip and the second flash memory chip through the first queue serial peripheral interface and the second queue serial peripheral interface, decompress the image block compressed data to obtain a plurality of decompressed partial image line data in a primary color format, and splice the partial image line data corresponding to the same line of the target image to obtain the image line data of each line of the target image. The accelerating engine equipment can output the image line data of each line to the driving chip and trigger the driving chip to drive the industrial screen to display the target image.

In one embodiment, clock synchronization of processing data in an acceleration engine device. It will be appreciated that the read frequency of the line compressed data from the memory, the clock frequency of the buffer to which the line compressed data is buffered, and the clock frequency of the line compressed data from the buffer are consistent. The synchronous clock in the acceleration engine equipment processes the image compression data, and the data is processed on the premise of synchronization, so that the data processing efficiency is improved.

In this embodiment, the acceleration engine device receives, based on the uart interface, the image display control instruction sent by the main control chip, and in response to the image display control instruction, reads, based on the plurality of queue serial peripheral interfaces, the row compression data of the plurality of image block compression data from the plurality of memory chips, and can ensure, by the acceleration engine device, communication to the external memory chip and a speed of transmission and processing of the image compression data.

It should be understood that, although the steps in the flowcharts related to the embodiments as described above are sequentially displayed as indicated by arrows, the steps are not necessarily performed sequentially as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least a part of the steps in the flowcharts related to the embodiments described above may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, and the execution order of the steps or stages is not necessarily sequential, but may be rotated or alternated with other steps or at least a part of the steps or stages in other steps.

Based on the same inventive concept, the embodiment of the present application further provides an image processing apparatus for implementing the image processing method. The implementation scheme for solving the problem provided by the apparatus is similar to the implementation scheme described in the above method, so specific limitations in one or more embodiments of the image processing apparatus provided below can be referred to the limitations of the image processing method in the foregoing, and details are not described here.

In one embodiment, as shown in fig. 6, there is provided an image processing apparatus 600 including: a response module 602, a decompression module 604, and a concatenation module 606, wherein:

a response module 602, configured to, in response to an image display control instruction sent by the main control chip, read row compressed data of the plurality of image block compressed data from the plurality of memory chips based on the plurality of queue serial peripheral interfaces; the plurality of image block compressed data are compressed data of a plurality of image blocks obtained by partitioning the target image; each of the image block compressed data includes a plurality of lines of compressed data.

A decompression module 604, configured to write the read line compressed data into the memory according to a preset write frequency, and read the line compressed data of the plurality of image block compressed data from the memory according to a preset read frequency; the reading frequency is greater than the writing frequency; and respectively caching the line compression data read from the memory into a plurality of buffers, decompressing the line compression data in the buffers to obtain a plurality of decompressed partial image line data.

A splicing module 606, configured to splice partial image line data corresponding to the same line of the target image to obtain image line data of each line of the target image; and outputting the image line data of each line to an industrial screen to display a target image.

In one embodiment, the memory chip is a flash memory chip; the device still includes: the burning module is used for partitioning the target image to obtain a plurality of image blocks; respectively compressing the data of the plurality of image blocks according to a preset compression mode to obtain a plurality of image block compressed data; and respectively burning the compressed data of the plurality of image blocks to a plurality of flash memory chips.

In one embodiment, the plurality of memory chips includes a first memory chip and a second memory chip; the plurality of queue serial peripheral interfaces comprise a first queue serial peripheral interface and a second queue serial peripheral interface; the response module 602 is further configured to, in response to an image display control instruction sent by the main control chip, read the current row compressed data of the first image block compressed data from the first memory chip through the first queue serial peripheral interface; the current line compressed data of the first image block compressed data is the line compressed data to be read currently in the first image block compressed data; after the reading of the compressed data of the current line of the compressed data of the first image block is finished, reading the compressed data of the current line of the compressed data of the second image block from the second storage chip through the second queue serial peripheral interface; after the reading of the current line compressed data of the second image block is finished, taking the next line compressed data of the first image block as the current line compressed data of the first image block, taking the next line compressed data of the second image block as the current line compressed data of the second image block, and returning to the step of reading the current line compressed data of the first image block from the first storage chip through the first queue serial peripheral interface to continue to execute until the line compressed data in the compressed data of the first image block and the line compressed data in the compressed data of the second image block are completely read.

In one embodiment, the plurality of memory chips includes a first memory chip and a second memory chip; the buffer comprises a first buffer and a second buffer; the decompression module 604 is further configured to alternately read the line compressed data from the first memory chip and the line compressed data from the second memory chip from the memory according to a preset reading frequency; in the process of alternately reading the line compression data of different memory chips from the memory, alternately caching the line compression data read from the memory from a first memory chip into a first buffer in sequence, and caching the line compression data read from the memory from a second memory chip into a second buffer in sequence; when the line compression data of the newly added buffer memory exists in the first buffer and the second buffer, decompressing the line compression data of the newly added buffer memory to obtain decompressed partial image line data corresponding to each line compression data in the first memory chip and the second memory chip respectively; the splicing module 606 is further configured to splice the decompressed partial image line data that correspond to the first memory chip and the second memory chip and belong to the same line, so as to obtain image line data of each line of the target image.

In one embodiment, the decompressing module 604 is further configured to obtain a compression mode identifier corresponding to the line compression data; determining the size of a target cache corresponding to the compression mode identifier; a plurality of buffers conforming to the target buffer size are allocated, and the line compression data read from the memory are buffered in the allocated buffers, respectively.

The respective modules in the image processing apparatus described above may be wholly or partially implemented by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, a computer device is provided, which may be a server, and the internal structure thereof may be as shown in fig. 7. The computer device includes a processor, a memory, an Input/Output interface (I/O for short), and a communication interface. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface is connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing image block compressed data. The input/output interface of the computer device is used for exchanging information between the processor and an external device. The communication interface of the computer device is used for connecting and communicating with an external terminal through a network. The computer program is executed by a processor to implement an image processing method.

In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in fig. 8. The computer apparatus includes a processor, a memory, an input/output interface, a communication interface, a display unit, and an input device. The processor, the memory and the input/output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input/output interface. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The input/output interface of the computer device is used for exchanging information between the processor and an external device. The communication interface of the computer device is used for carrying out wired or wireless communication with an external terminal, and the wireless communication can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. The computer program is executed by a processor to implement an image processing method. The display unit of the computer equipment is used for forming a visual and visible picture, and can be a display screen, a projection device or a virtual reality imaging device, the display screen can be a liquid crystal display screen or an electronic ink display screen, the input device of the computer equipment can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.

It will be appreciated by those skilled in the art that the configurations shown in fig. 7 and 8 are only block diagrams of some configurations relevant to the present disclosure, and do not constitute a limitation on the computer apparatus to which the present disclosure may be applied, and a particular computer apparatus may include more or less components than those shown in the figures, or may combine certain components, or have a different arrangement of components.

In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the above-described method embodiments when executing the computer program.

In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

In an embodiment, a computer program product is provided, comprising a computer program which, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.

It should be noted that, the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) referred to in the present application are information and data authorized by the user or sufficiently authorized by each party, and the collection, use and processing of the related data need to comply with the relevant laws and regulations and standards of the relevant country and region.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, databases, or other media used in the embodiments provided herein can include at least one of non-volatile and volatile memory. The nonvolatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical Memory, high-density embedded nonvolatile Memory, resistive Random Access Memory (ReRAM), Magnetic Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), graphene Memory, and the like. Volatile Memory can include Random Access Memory (RAM), external cache Memory, and the like. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others. The databases referred to in various embodiments provided herein may include at least one of relational and non-relational databases. The non-relational database may include, but is not limited to, a block chain based distributed database, and the like. The processors referred to in the embodiments provided herein may be general purpose processors, central processing units, graphics processors, digital signal processors, programmable logic devices, quantum computing based data processing logic devices, etc., without limitation.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present application. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An image processing method, characterized in that the method comprises:

writing the read line compressed data into a memory according to a preset writing frequency, and reading the line compressed data of the plurality of image block compressed data from the memory according to the preset reading frequency; the read frequency is greater than the write frequency;

2. The method of claim 1, wherein the memory chip is a flash memory chip; the method also comprises an image compression data burning step; the burning step of the image compressed data comprises the following steps:

partitioning a target image to obtain a plurality of image blocks;

3. The method of claim 1, wherein the plurality of memory chips comprises a first memory chip and a second memory chip; the plurality of queue serial peripheral interfaces comprises a first queue serial peripheral interface and a second queue serial peripheral interface; the reading of the row compression data of the plurality of image block compression data from the plurality of memory chips based on the plurality of queue serial peripheral interfaces in response to the image display control instruction sent by the main control chip comprises:

and after the reading of the current row compressed data of the second image block compressed data is finished, taking the next row compressed data of the first image block compressed data as the current row compressed data of the first image block compressed data, and taking the next row compressed data of the second image block compressed data as the current row compressed data of the second image block compressed data, so as to return to the reading of the current row compressed data of the first image block compressed data from the first storage chip through the first queue serial peripheral interface for continuous execution until the reading of all the row compressed data in the first image block compressed data and the row compressed data in the second image block compressed data is finished.

4. The method of claim 1, wherein the plurality of memory chips comprises a first memory chip and a second memory chip; the buffers include a first buffer and a second buffer; the method for reading the line compression data of the compressed data of the plurality of image blocks from the memory according to the preset reading frequency comprises the following steps:

the caching the line compressed data read from the memory into a plurality of buffers, and decompressing the line compressed data in the buffers to obtain a plurality of decompressed partial image line data includes:

5. The method of claim 1, wherein the separately buffering the line compressed data read from the memory into a plurality of buffers comprises:

determining a target cache size corresponding to the compression mode identifier;

6. The method of any of claims 1 to 5, wherein the method is performed by an acceleration engine device; the acceleration engine device comprises a universal asynchronous receiving and transmitting interface used for being in butt joint with the main control chip and a queue serial peripheral interface used for being in butt joint with the storage chip; the reading of the row compression data of the plurality of image block compression data from the plurality of memory chips based on the plurality of queue serial peripheral interfaces in response to the image display control instruction sent by the main control chip comprises:

7. An image processing apparatus, characterized in that the apparatus comprises:

the response module is used for reading row compression data of the image block compression data from the plurality of storage chips based on the plurality of queue serial peripheral interfaces in response to an image display control instruction sent by the main control chip; the compressed data of the plurality of image blocks is the compressed data of the plurality of image blocks obtained by partitioning the target image; each image block compressed data comprises a plurality of lines of compressed data;

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 6.

9. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that the computer program realizes the steps of the method of any one of claims 1 to 6 when executed by a processor.