JP2002368996A - Image reader and image forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the scale of a data generation means for shading correction (SH) to thereby suppress the rise of cost when an SH data generating function is incorporated into small-scaled IC. SOLUTION: The scale of storage capacity is reduced by compressing data preserved in a base part storage part 400. A D's compression part 500 divides pixel string data showing fluctuation in a prescribed range in SH data generated in an SH operation part 200 into a base part and a fluctuation part. Data on the base part is compressed. Conventional storage data quantity where complete data is preserved at every pixel can be reduced. The SH calculation part calculates SH data of a present line based on present reading data on a reference white board and SH data of the previous line, which is restored based on data which is read from the fluctuation part/base part storage parts in a Ds extension part 600.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image reading apparatus for reading an image from a document using an image sensor, and an image forming apparatus such as a copying machine for forming an image based on image data output from the image reading apparatus. More specifically, the present invention relates to the image reading apparatus and the image forming apparatus in which a storage unit used for generating shading correction data for correcting read image data output is downsized.

[0002]

2. Description of the Related Art In an image reading apparatus provided in a digital copying machine, a scanner, or the like, which is now widely used, a CCD line sensor (or a document image received by the sensor) is scanned by a main scanning line for a document illuminated by a lamp. , And a two-dimensional scan is performed to read the entire surface of the document. When reading a document by such a method, the illumination conditions and the like fluctuate over time, and thus the output of the line sensor includes an error due to the fluctuation. This error is usually
Before reading a document, a reference body (reference white plate) installed at a predetermined place is read by the same operation as that of the document, and a correction value for each pixel is determined based on detected white data (reference white plate read data). Is generated, and the output of appropriate image data is secured using this data.

Here, a description will be given of a conventional technique adopted for generating such shading data. FIG. 17 shows an example of a conventional shading data generation circuit. In the example shown in FIG. 17, the shading data generation operation is performed by a quarter addition, that is, the data of the current line is added to the data of the previous line with a weight of 1/4. Output it according to the formula. Reference white board first line: Ds = 3 × D0 / 4 Reference white board second line: Ds = (3 × Ds ′ + Dn) / 4 where Dn: corresponding pixel data of the (n + 1) th line Ds: generated shading data Ds ': Shading data generated in the previous line In order to perform the above-mentioned quarter-addition operation, as shown in FIG. 17, two selectors SEL (1) 1, SEL (2) 2, multiplier 3, An adder 4 and a FIFO 5 are provided in a shading data generation circuit, and the inputs thereof are as follows.
h together with the 8-bit image data Din corrected to
Pixel clocks SCLK and FIF for latching Din
XRRST for initializing the address of the read data of O5
A signal, an XWRST signal for initializing an address for writing data to the FIFO 5, and an XSH1ST signal indicating the first line of the shading data generation area are input.

FIGS. 18A and 18B are time charts of signals related to the operation. FIG. 18A shows an SHGT signal indicating a shading data generation area and the above-described input signals, and FIG. 18B shows an XRRST signal and an enlarged time chart. XWRST signal, S
4 shows a time chart of read data Dr and write data Dw for accessing CLK, Din, and FIFO5. As shown in FIG. 18, XRRST is active (“L”) in a region excluding valid pixels in one line of image data.
XWRST is XRRS while SHGT is “H”.
Same as T, but is "L" while SHGT is "L" (ie, a signal obtained by ANDing SHGT and XRRST). XSH1ST is a signal of “L” only in the effective pixel area of the first one line where SHGT becomes “H”.

Hereinafter, the operation of the shading data generation circuit shown in FIG. 17 will be described with reference to FIG. the first,
In the area where SHGT is “L”, Din is image data other than the shading data generation area. At this time, since XRRST has been input, the data Dr of the FIFO 5 at the address corresponding to the pixel position is read from the FIFO 5 in the effective pixel area in one line (FI
The data read from the FO5 is shading data from the previous scan.) XWRST is “L”
Therefore, the output data of the adder (ADD) 4 is not written in the FIFO 5. Next, since XSH1ST is input in the first line in which the SHGT becomes “H”, the SEL a of the selectors SEL (1) 1 and SEL (2) 2 are
The terminal becomes "L", the output of SEL (1) 1 becomes Din, and the output of SEL (2) 2 becomes "00h". At this time, the output of the multiplier (MULT) 3 is Din × 03h, and the output of the adder (ADD) 4 is the upper 8 bits of the addition result.
Since a bit is output, (Din × 03h + 00h) / 4. The result is written to the corresponding address of the FIFO 5 as shading data for each pixel.

After the next line, since XSH1ST is always "H", the selector SEL (1) 1 switches the output from the first line and sets its output as Dr (shading data calculated on the previous line) of the FIFO5. , The output of the multiplier (MULT) 3 is Ds ′ × 03h, and the output is switched to the output of the selector SEL (2) on the 21st line, and the output is set to Din.
The output of D) 4 becomes (Ds' × 03h + Din) / 4, and is written to the corresponding address of FIFO 5 as shading data for each pixel as in the first line. This operation is continuously performed during the SHGT “H” period set as the shading data generation area (see FIG. 18B). Next, when SHGT becomes “L”, the calculation itself is performed in the same manner as above, but since XWRST is “L”,
Writing to the FIFO5 is not performed, and the shading data generated in the last line while the SHGT is "H" is
It is read from the FO5 and used for shading correction processing. As described above, in this conventional example, since the shading data of each pixel is stored in the FIFO 5, a word length of the FIFO corresponding to the total number of effective pixels is required. For example, when a 12-inch width is read at 8 bits per pixel at 600 dpi, the number of effective pixels is 7200 pixels, and 7200 bytes (= 7200 × 8 bits = 5
7600 bits).

[0007]

By the way, the above-mentioned shading correction function is incorporated in a large-scale image processing IC placed in the main body of a conventional digital copying machine. The cost of storage means and the like required to realize the above has not been so obvious. However, considering modularization of the digital copier unit, it is essential that the scanner unit has a shading correction function and a scanner gamma correction function, etc., so that the scanner unit has a certain output characteristic. It is required as a basic form, and when trying to realize such a function in the unit,
Up to now, large-scale I such as the image processing IC
Since these functions are not provided, these functions are added and incorporated into a small-scale IC, and the scale of the incorporated functions immediately affects the cost. The present invention has been made in view of the above-described problems in the conventional image reading apparatus, and has as its object to reduce the size of the conventional shading data generating means using a large-scale IC having a large-capacity storage means. An image reading apparatus (for example, a scanner or the like) capable of reducing the cost when the shading data generation function is incorporated into a small-scale IC by increasing the scale, and an image forming apparatus (copying machine, Facsimile, etc.).

[0008]

According to a first aspect of the present invention, a reference white board is read by a line image sensor while the line image sensor is relatively moved in a sub-scanning direction intersecting the main scanning line, and the line image sensor is read based on white data obtained. What is claimed is: 1. An image reading apparatus comprising: means for generating shading correction data for stabilizing a reading output of a sensor, wherein the shading correction data generation means includes a shading correction data generated in a pixel unit in a pixel arrangement order. Means for dividing a base portion and a variable portion of the data in a pixel row showing a variation within a predetermined range, compressing the data of the base portion, a variation storage device for storing the data of the divided variation portion, A base storage means for storing data of the base portion, and reading data from the variation storage means and the base storage means An image reading apparatus characterized by comprising a data decompression means for restoring the shading correction data.

According to a second aspect of the present invention, in the image reading apparatus according to the first aspect, the shading correction data generating means is configured to perform shading of the read white data of the current line and the previous line restored by the data decompression means. The shading correction data is generated by means for calculating the shading correction data of the current line based on the correction data.

According to a third aspect of the present invention, in the image reading apparatus according to the first or second aspect, the base storage means has a plurality of FIFOs, and the FIFOs are sequentially operated. It is characterized by having.

According to a fourth aspect of the present invention, in the image reading apparatus according to the first or second aspect, the base storage means is a one-system storage means for operating consecutive addresses in a loop. It is assumed that.

According to a fifth aspect of the present invention, in the image reading device according to any one of the first to fourth aspects, the data compression unit performs division / compression processing for each system according to the system of the read data. It is characterized by being.

According to a sixth aspect of the present invention, there is provided an image reading apparatus according to any one of the first to fifth aspects, and means for forming an image based on image data output from the image reading apparatus. Image forming apparatus.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An image reading apparatus and an image forming apparatus according to the present invention will be described with reference to the following embodiments shown in the accompanying drawings. The image reading device described below as an embodiment can be configured as a reading device such as a single image scanner, but a digital device that reproduces an image by using a read output of a document image as a write signal for forming an image. It can also be used in a reading unit of an image forming apparatus such as a copying machine and a facsimile. Therefore, first, a DPPC (Digital Plane Paper) as an image forming apparatus equipped with an image reading apparatus according to the present invention in a reading unit.
A copy-machine (a so-called digital copying machine) will be described. FIG. 1 is a schematic diagram showing a configuration of a DPPC according to an embodiment of the present invention. The structure of the DPPC of the present embodiment will be described with reference to FIG. 1. The illustrated DPPC is roughly composed of an automatic document feeder (ADF) 34 and an image reading device 35.
, An image forming unit 50, and an operation unit (not shown). The ADF 34 includes a document mounting table 30, a reversing tray 31, and an ARDF drive motor 32, and performs an operation of transporting and discharging a copy document via a reading position. The image reading device 35 includes a scanning system 63 including an exposure lamp 61 and a mirror group 62 on a carriage, a light receiving unit (including an imaging lens, an image sensor as a light receiving element, a circuit board for processing a sensor output, and the like) 60. The scanner includes a scanner drive motor 33, and performs reading corresponding to two systems, a sheet-through system that conveys an original using the ADF 34, and a scanner moving system that scans an original placed on a platen.

The image forming section 50 has an in-machine paper discharge section 36 for discharging transfer paper, a polygon motor and a mirror 37 for reflecting a laser from a laser diode 38 driven by original image data and the like, and emits a laser. A laser diode 38, a photosensitive drum 39 for forming an electrostatic latent image by laser writing, a registration roller 40, a manual feed door 41 which is opened when the transfer paper is manually fed, and a toner on the transfer paper which is transferred to the transfer paper. Fixing unit 42 for fixing
And the first and second sheet cassettes 44 and 4
5, a first paper feed cassette 44 and a second paper feed cassette 45 for storing transfer paper, and a transfer paper fed by the paper feed roller 43. , A discharge cover 47 that is opened when the discharged transfer paper is directly discharged, a switching unit 48 that switches the discharge of the transfer paper to either the discharge cover 47 or the in-machine discharge unit 36, and a transfer. A transport roller 49 for transporting the paper to the on-premise discharge unit 36 is provided, and the transfer paper is operated to form an image. The operation unit has a function of receiving an operation input of a key or the like by an operator for setting various operations of the DPPC, and performing a function of notifying the operator of an operation state of the machine.

Next, an embodiment of the image reading apparatus according to the present invention will be described. Although the embodiments described below can be configured as a single reading device such as an image scanner, as described above, the reading output of the original image is used for a writing signal for forming an image, and the image is read. It can be provided in a reading section of an image forming apparatus such as a digital copying machine and a facsimile for reproduction. FIG. 2 is a diagram schematically illustrating the configuration of the image reading apparatus according to the present embodiment.
2, reference numeral 11 denotes a document to be read, reference numeral 12 denotes a contact glass serving as a document table, reference numeral C1 denotes an integrated unit having an exposure lamp 13 and a first mirror 14, and a first carriage for reading and scanning, and reference numeral C2 denotes a second mirror 15. This is a second carriage that has an integrated third mirror 16 and guides the image of the document exposure unit from the first carriage C1 to the light receiving unit. The light receiving section includes an imaging lens 17, a line image sensor 18 as a light receiving element, a circuit board (not shown) for processing a sensor output, and the like. The circuit board has a function for generating shading data described later. Is provided. At the time of reading, the first carriage C1 is moved in the direction of arrow A shown in the figure to scan and expose the original, and the reflected light from the original exposure unit is transmitted to the light receiving unit by the first to third mirrors 14, 15, and 16. At this time, the second carriage C2 is moved in the direction of the arrow A 'shown so as to keep the optical path length constant. The scanned document exposure unit is imaged on a light receiving surface of an image sensor 18 having a light receiving element by an image forming lens 17 of the light receiving unit, is photoelectrically converted, and is output as an image signal. Further, after performing a correction such as shading correction on the image signal after the photoelectric conversion, the image signal is sent to a next image processing unit (not shown) as a predetermined original reading output, and the image forming data is created there. This is used for processing. In the shading correction, the reference white board 20 is read by a scanner operation, and shading data is generated based on the obtained output (white) image (details will be described later), and this is used for correcting the read image signal.

Next, an embodiment relating to the shading data generating circuit of the above-described image reading apparatus will be described.
According to the present invention, a shading data generation circuit is configured by adopting a method that enables generation with a smaller storage capacity than the conventional technology in which a capacity for storing all pixels of an image sensor is prepared. The scaling is based on compression of data stored in the storage unit. To compress the data,
According to the present invention, the created shading data is divided into a base portion and a variable portion, and the base portion is shared by a plurality of pixels. By doing so, it is possible to reduce the conventional data amount in which complete data is stored for each pixel. For this purpose, a new base storage unit and a variable storage unit are newly prepared as data storage means.
A circuit is configured with a data compression unit, a data decompression unit, and a control unit for controlling these units as new components.

FIG. 3 is a block diagram showing a first embodiment of a shading data generation circuit. As shown in FIG. 3, the input to the circuit is input to an image Din that reads a reference white board 20 input to an SH calculation unit 200 that calculates shading (SH) data and to a control unit 100 that controls the operation of this circuit. Timing signal, and the output is D
This is a reproduction signal Ds of the stored SH data output from the s decompression unit 600. The circuit in FIG. 3 includes a Ds ′ compression unit 500, a variation storage unit 300, and a base storage unit 400 as circuit elements under the control of the control unit 100.

The operation of the circuit will be described together with the function of each part of the circuit. The read image data Din is SH
The data is input to the arithmetic unit 200. On the other hand, the Ds decompression section 600 reproduces the SH data of the corresponding pixel of the previous line from the base data Db and the fluctuation data Dv of the SH stored in a compressed state in the processing of the previous line. Output. In the SH operation unit 200, a prescribed operation expression (for example,
The current line
The SH data Ds ′ of the current pixel is generated, and the Ds ′ compression unit 50
Output to 0. The Ds ′ compression unit 500 obtains the difference Dv between the base Db of the previous pixel of the pixels arranged in the main scanning direction and the Ds ′ of the current pixel. If Dv is within the specified range, the Dv is stored in the variation storage 300. At the same time as writing, "1" is added to the base continuous number Nb. If the difference Dv exceeds the specified range, the current Db and Nb are written in the base storage unit 400, that is, Nb is initialized at the same time as Db = Ds', and Dv is written "0". . The Ds extension unit 600
From the variation storage unit 300, the difference Dv and the base storage unit 4
00, Db / Nb is read, and SH data Ds = D
After outputting as v + Db, counting the number of pixels to which the same Db is applied, and applying Db to the number of pixels indicated by Nb, the new Db · Nb is then stored in the base storage unit 400
Read from. The operation timing of each unit of the block is controlled by the control unit 100 based on the input timing signal.

As a second embodiment, a shading data generation circuit will be described in more detail with reference to an example in which the base storage unit in the first embodiment has a two-bank configuration. FIG.
FIG. 9 is a block diagram showing a second embodiment of the shading data generation circuit. In FIG. 4, the base storage unit 400 has a two-bank configuration of bank (0) and bank (1). Here, each bank is constituted by a FIFO, and the bank is alternately accessed for each pixel with respect to the image data, so that the processing is speeded up and the odd and even pixel data are separated. However, each bank can be used for odd and even pixels. The circuit shown in FIG. 4 is basically the same as the circuit shown in FIG. 3 except that the two-bank configuration, control (timing) signals to each section, and signal terminals are shown in detail. The configuration of the main part of the circuit shown in FIG. 4 will be described in more detail with reference to FIGS. FIG. 5 shows a detailed circuit of the control unit 100 shown in FIG. The control unit 100 includes AND circuits (AND (1), (2), (3)) 101, 1 as circuit elements.
05, 109, D-flip-flop (D-FF (1),
(2), (3), (4)) 102, 103, 104, 111, counters (COUNT (1), (2)) 106, 107, and inverters (INV (1), (2)) 108, 110 And configured as shown in FIG.

FIG. 6 shows a timing chart of signals (shown in FIG. 5) related to the control unit 100. FIG.
(B) in the figure shows the time enlarged in comparison with (A).
Input signals to the control unit 100 are SHGT, LSYNC,
In the SCLK signal, these indicate SHGT: “H” indicating a valid area of the reference white board. This signal generates SH data during the period of “H”. Here, six scan lines are defined as the effective area. LSYNC: Indicates a line synchronization signal generated at the head of one line. SCLK: Indicates a pixel clock. Output signals from the control unit 100 are BEN, BENB, S
In H1ST, LGATE, and LG_D1, these indicate BEN: bank switching signal. It is toggled during the SHGT “H” period, and the state immediately before the SHGT becomes “L” is held until the next SHGT becomes “H”. BENB: Indicates an inverted signal of BEN. SH1ST: Indicates a signal which becomes “H” only in one line immediately after SHGT becomes “H”. LGATE: Indicates a signal indicating an effective pixel area in one line based on LSYNC. LG_D1: A signal obtained by delaying LGATE by one pixel.

FIG. 7 shows a detailed circuit of the Ds' compression section 500 shown in FIG. The Ds ′ compression unit 500 includes, as circuit elements, a subtractor (SUB (AB)) 501 and AND circuits (AND (1), (2), (3), (4)) 504, 505, 502,
509, NOR circuit (NOR) 503, inverter (IN)
V (1)) 506, OR circuit (OR) 507, latch (L
ATCH) 508 and a counter (COUNT) 510, and are configured as shown in FIG. Note that the example shown in FIG. 7 shows an example in which Ds', Db, and Nb are each 8 bits, and Dv is 4 bits. The input signal to the Ds ′ compression unit 500 is D
s ', SCLK, en, which indicate Ds': generated SH data. SCLK: Indicates a pixel clock. en: Indicates a compression operation permission signal (when en is "L", wen also becomes "L"). The output signal from the Ds' compression unit 500 is Dv, wen,
Db and Nb indicate Dv: fluctuation data (Ds′−Db). wen: indicates a base-level storage permission signal. Db: Indicates data of a base portion. Nb: Indicates the number of continuous Db minus 1.

The operation of the Ds' compression unit 500 is performed by a subtractor (S
UB (AB) 501 performs Ds′-Db, and determines whether the result is in the lower 4 bits by NOR 503 and AN
Judgment is made in D (1), (2) 504 and 505, and if they are in the lower 4 bits (output "L" of AND (2) 505), the counter (COUNT) 510 is advanced by one. If it is not in the lower 4 bits (output “H” of AND (2) 505),
The output wen of the OR circuit (OR) 507 is set to “H”, and writing to the base storage unit 400 is permitted. Further, the output (H) of AND (2) 505 causes the latch (LAT)
CH) 508 is enabled and Db = Ds', and at the same time, the counter (COUNT) 510 is cleared to zero. At this time, the output (L) inverter (INV (1)) 5
Dv is “0” by AND (3) 502 having 06 as input.
Is output. Nb is the number of pixels to which Db is applied−1
Is entered. FIG. 8 shows a timing chart of a signal (illustrated in FIG. 7) related to the Ds ′ compression section 500. FIG.
(A) in the figure shows that the data Db of the base part frequently changes greatly in the pixel data of the generated SH data Ds ′.
And (B) in the same figure shows a case where the variation of Ds' is small and Nb becomes 255. In the example of (B), when it becomes 255, w
en is set to “H”, and writing to the base storage unit 400 is performed. Note that the numbers attached to the data diagrams in FIG. 8 illustrate data values. Although not described in the above embodiment, image data input to the SH data generation circuit is subjected to so-called analog processing from an image sensor to AD conversion by dividing the processing into two systems of odd and even pixels. In such a case, it is possible to divide such input image data for each system and perform the above-described division of the base portion and the variable portion of the Ds' compression section 500 and compression processing of the base portion. The Ds ′ compression section 500 is configured so that In this way, the odd number, the even number,
It is possible to avoid a decrease in the compression ratio that occurs when the division processing of the even pixel system is not performed.

FIG. 9 shows a detailed circuit of the Ds decompression section 600 shown in FIG. The Ds expansion unit 600 includes, as a circuit element,
Adder (ADD) 601 and counter (COUNT) 60
2. Subtractor (SUB (AB)) 603, NOR circuit (N
OR) 604 and is configured as shown in FIG. Ds
Input signals to the expansion unit 600 are Dv, Db, Nb, SC
LK and en indicate Dv: fluctuation data (Ds′−Db). Db: Indicates data of a base portion. Nb: Indicates the number of continuous Db minus 1. SCLK: Indicates a pixel clock. en: Indicates a compression operation permission signal (when en is "L", wen also becomes "L"). The output signal from the Ds expansion unit 600 is Ds, ren,
These indicate ren: base-level read permission signal. Ds: indicates reproduced SH data. The operation of the Ds decompression unit 600 is based on Dv read from the variation storage unit 300 and Dv read from the base storage unit 400.
b is added by an adder (ADD) 601 and output as Ds. Also, the Db applied pixel number counter (COUNT) 60
2 is cleared when Db / Nb is read, and counts up for each pixel. When the output of the counter (COUNT) 602 becomes equal to Nb, the subtractor (SUB (A-
B)) NOR circuit (NOR) 604 receiving the output of 603
Is set to “H”, and the counter (CUN)
T) Clear 602 and read out new Db / Nb. FIG. 10 shows signals related to the Ds decompression unit 600 (FIG. 9).
2) shows a timing chart. Note that FIG.
The numbers attached to the respective data diagrams illustrate data values.

FIG. 11 shows the base storage unit 40 shown in FIG.
0 shows a detailed circuit. The base storage unit 400 includes selectors (SEL) 401, storage units (banks (0), (1)) 402, 403, and AND circuits (AND (1),
(2), (3)) 409, 410, 404, inverter (IN
V (1), (2)) 405,413, OR circuit (OR (1), (2),
(3)) 407, 408, 406, NAND circuit (NAND)
(1), (2)) 411 and 412, and are configured as shown in FIG. The input signal to the base storage unit 400 is xw
st, Dwb, Dwn, wck, wb, wen, rc
In k, rb, and ren, these indicate xwst: a write address reset signal. Dwb: indicates base partial write data. Dwn: Indicates the number of consecutive Db minus 1 write data. wck: indicates a write clock. wb: Indicates a write bank designation signal. wen: indicates a base-level storage permission signal. rck: indicates a read clock. rb: indicates a read bank designation signal. ren: Indicates a base-level read permission signal. Output signals from the base storage unit 400 are Drb, Dr
At n, these indicate Drb: base partial read data. Drn: the number of continuous Db minus 1 read data.

FIG. 12 is a timing chart of signals (shown in FIG. 11) related to the base storage unit 400. It should be noted that the numbers attached to the respective data diagrams in FIG. 12 illustrate data values. 11 and 1
2, the write operation of the base storage unit 400 is write data of a 2-byte (16-bit) configuration in this example, and the lower byte (Dw0 to Dw0) of the write data.
7) Allot the base (Dwb) to the upper byte (D
w8 to 15), the number of continuous Db (Dwn) is allocated. Write data can be input through connection to both input terminals Dw of the bank (0) 402 and the bank (1) 403.
The write control to the banks is performed by controlling the write clock wck of each bank. When wb is “L” (FIG. 1
2 (A) shows this case), wen “H” or xwr
At the time of st “L” (in this case, w (w) and (1) are both w
ck is entered as is), wck is stored in bank (0) 402
Is entered. In wb “H”, wck is input to the bank (1) 403. The read control from the bank is performed simultaneously with the banks (0) and (1), and xrst “L” or re
n “H” (see FIG. 12 (B);
b indicates “L”). In addition, the selector (SEL)
When the output is selected by 401 and the rb signal input to the SEL 401 is “L”, the bank (0) 402
In “H”, the bank (1) 403 stores Drb (Dr0 to Dr0).
7), and output as Drn (Dr8-15).

Here, the second embodiment (FIGS. 4 to 12)
The data generation procedure by the two-bank shading data generation circuit shown in FIG. 13 will be described with reference to the flowchart shown in FIG. This flow is executed by a controller provided in the image reading device for controlling a scanner operation. The flow starts when the power of the device is turned on.
As an initial setting, the bank (0) 4 of the base storage unit 400
02, to designate the bank (1) 403, the read bank designation signal rb = 0, the write bank designation signal wb = 1,
Alternatively, rb = 1 and wb = 0 are set (S131). The carriages C1 and C2 are moved (sub-scanning), and it is checked whether or not the carriage C1 has entered an area for reading the reference white plate 20 (S13).
2). It is confirmed that the vehicle has entered the reference white plate area (S132).
After that, it is checked whether or not the read data is image data of the effective pixel area of the reference white board 20 (S13).
5) The processing is performed on the pixel data within the effective range. Before that, the read / write banks are exchanged, that is, rb⇔wb is performed (S133), and the effective pixels in the base storage unit 400 are also processed. The counter, the read base counter, and the write base counter are initialized, that is, pix = rbc = wbc = 0 (S13)
4).

Next, with respect to image data input over a predetermined line in the effective pixel area of the line, shading (SH) correction data of each line is calculated by the SH operation unit 200, and the base Db (rb, rbc) is continuously calculated. Number: Nb (rb, rbc) is decremented by one (S136).
Assuming that the SH correction data to be calculated here is pix pixel image data: Din (pix), the first line of SH correction data: Ds is: Ds = 3 × Din (pix) / 4 SH of the second and subsequent lines Correction data: Ds is obtained by Ds = (3 × Ds ′ + Din (pix)) / 4. In the above equation, the SH correction data of the previous line: Ds' = Db (rb, rbc) + Dv (pi
x), where Db (rb, rbc): the base of the SH correction data of the previous line, Dv (pix): SH of the previous line
This is the variation of the correction data. Thereafter, it is checked whether or not the number of continuations after subtracting −1 from the number of continuations of the base Db (rb, rbc) in S136, that is, Nb (rb, rbc) = 0. Since there are no pixels using (rb, rbc), the read base counter is incremented by 1, that is, rbc = rbc + 1. If it is not 0, S138 is passed.

Next, it is checked whether or not the variation of Ds (difference from the base of the previous pixel) is within a prescribed range (S139). Here, it is within the range of -8 to 7,
That is, -8 ≦ Ds−Db (wb, wbc) <8 is determined,
If it is out of the range, to advance wbc by 1, wbc =
wbc + 1, Nb (wb, wbc) = 0 in order to initialize the continuous number of bases to 0, and Db (wb, wbc) = D in order to use the base as shading data.
s is stored in the base storage unit 400 (S14).
0). If the variation Ds−Db (wb, wbc) is within the specified range in S139, the process goes through S140 and performs the following processes (S141). In order to increase the base continuation number by 1, Nb (wb, wbc) = Nb (wb, wbc) +1
In order to calculate the variation Dv (pix), Ds−
Db (wb, wbc) is calculated and stored in the variation storage unit 300. At this time, to advance the pixel counter by 1,
pix = pix + 1. Next, in order to perform the steps from S133 for each pixel, it is checked whether or not the pixel is within the effective pixel range (S142). If there is an unprocessed effective pixel in one line (S142-YES), The process returns to S133, and the subsequent steps are performed. At this time, S133
, The read / write banks are exchanged, so that even-numbered and odd-numbered pixel groups are used for the bank (0) 402 and the bank (1).
403 will be used properly. If there is no valid pixel in one line (S142-NO), the process returns to S132 to perform the processing of the next line, and the subsequent steps are performed.

Next, a description will be given of a third embodiment relating to a shading data generating circuit. In this embodiment, a memory for operating a memory having one continuous address in a loop is stored in the base storage unit in the first embodiment having the basic elements of the present invention shown in FIG. The part is adopted. FIG. 14 illustrates a shading data generation circuit according to the present embodiment. The circuit shown in FIG.
Except that the control (timing) signals and signal terminals for each component are shown in detail, there is basically no difference from the circuit of FIG. The configuration of the base storage unit 400 shown in FIG. 14 that characterizes this embodiment will be described in detail with reference to FIGS. FIG. 15 shows a detailed circuit of the base storage unit 400 of the SH data generation circuit (FIG. 14) of this embodiment. The base storage unit 400 includes a dual port memory 421, an OR circuit (OR) 422, counters (COUNT (1), (2)) 423, 424, and a latch (L
ATCH) 425, NOR circuit (NOR) 426, inverters (INV (1), (2)) 427, 428, and AND circuit (AND) 429, and are configured as shown in FIG. Input signals to the base storage unit 400 are Dwb, D
wn, wck, wen, rck, ren, shgt, s
In h1st, lgate, and lg_d1, these indicate Dwb: base partial write data. Dwn: Indicates the number of consecutive Db minus 1 write data. wck: indicates a write clock. wen: indicates a base-level storage permission signal. rck: indicates a read clock. ren: Indicates a base-level read permission signal. shgt: Indicates a reference whiteboard effective area signal. sh1st: Signal of the first line immediately after shgt lgate: Indicates an effective pixel area signal. lg_d1: Indicates a signal obtained by delaying lgate by one pixel. Output signals from the base storage unit 400 are Drb, Dr
At n, these indicate Drb: base partial read data. Drn: the number of continuous Db minus 1 read data.

FIG. 16 is a timing chart of signals related to the base storage unit 400 (input signals to corresponding terminals are indicated by signal names or terminal names in FIG. 15).
Referring to FIGS. 15 and 16, in this example, a dual-port memory 421 having a capacity of 1024 words is used, and as in the base storage unit of the above-described embodiment (FIG. 4), data of a 2-byte (16-bit) configuration is used. The base byte is allocated to the lower byte of data and the number of continuous Db is allocated to the upper byte (that is, Dwb (base) is Dw0 to 7, Dwn (continuous number of Db) is Dw8 to 15, and Drb (base) is Dr0.
7, Drn (the number of continuous Db) is allocated to Dr8 to Dr15). Dw is related to a write port of the dual port memory 421, Dr is related to a read port, and a write address (wadr) and a read address (radr) are respectively a write address counter COUNT (2) 424,
It is set by the read address counter CNT (1) 423. CNT (2) 424 for writing is shg
It is cleared during the t “L” period (in FIG. 16, COUNT (2) C
LR), and each time wen “H” is counted up. At this time, a memory having a continuous address having a capacity of 1024 words is used as the dual port memory 421 and is operated in a loop.
(2) When the counter value reaches 1023, 424 starts counting from 0 next.

COUNT (1) 423 for reading
Is cleared at sh1st (in FIG. 16, COUNT (1)
During the shgt “H”, the count is sequentially increased every ren “H”. In addition, the latch (LATC
In H) 425, wadr (counter value of COUNT (2) 424) is used in the first pixel of lgate in shgt “H”.
(Shown as LATCH EN in FIG. 16), the latched address is set as the read start address of CNT (1) 423, and the count is incremented every ren “H”. For this reason, while shgt is “H”, the read start address is set for each line by the LATCH 425 (indicated by LATCH DO in FIG. 16; the first address of the reference white plate effective area is 0). Also, shgt
Becomes "L", the write start address of the last line is held. The read at shgt “L” is L
The last line write start address (SH data address) held by ATCH 425 is
It is loaded at T (1) 423 and counts up for each ren “H”. In the storage unit according to the present embodiment, which operates a memory having a continuous address of one system in a loop, even if data of an odd-numbered pixel and an even-numbered pixel, which may cause a level difference, are continuously input, the compression ratio is reduced. Can be avoided.

As described in the above embodiments, the generation S
H correction data (Ds'): 8 bits, base part (D
b): 8 bits, base continuous number (Nb): 8 bits, variable part (Dv): 4 bits, the effective pixel number is 745
Assuming 0 pixels, Dv: 4 bits × 7450 Db: 8 bits × 256 words Nb: 8 bits × 256 words, depending on the S / N of the image data. From this, the required memory capacity is “Example 2” 4 × 7450 + 8 × 256 × 2 × 2 = 37992 (bi
t) “Example 3” 4 × 7450 + 8 × 256 × 2 × 1 = 33896 (bi
t) Here, the change in the compression ratio for the base is expected to be about half. In the conventional example, since complete data is stored for each pixel, 8 × 7450 = 59600 (bits). Therefore, as compared with the conventional example, the memory amount of “Example 2”: 63.7% “Claim 3”: 56.9% is sufficient, and the storage unit of the shading correction data can be reduced.

[0034]

(1) Effects corresponding to the first and second aspects of the present invention The shading correction data generating means of the image reading apparatus transmits the data in the pixel row in which the generated shading correction data shows a variation within a predetermined range. Means for dividing the base part and the variable part and compressing the data of the base part,
A storage means for storing data of the divided variable portion and the compressed base portion, and a data decompression means for reading out the stored data of the variation and the base and restoring the data for shading correction, thereby providing shading correction data. This makes it possible to reduce the size of the generating means and reduce the cost, and furthermore, when the image reading device is a unit such as a digital copying machine, it is possible to incorporate a shading data generating function into a small-scale IC in the unit. Therefore, the performance of the unit can be improved. (2) Effects corresponding to the third aspect of the invention In addition to the effects of the above (1), a plurality of systems of FIFOs are sequentially operated as storage means for storing compressed base portion data (for example, alternately in a two-bank configuration). ), The processing speed can be increased. (3) Effects corresponding to the fourth aspect of the invention In addition to the effects of the above (1), as storage means for storing compressed base portion data, one system of storage means for operating consecutive addresses in a loop is used. By doing so, it is possible to further reduce the memory capacity, and to avoid a decrease in the compression ratio even when data of odd-numbered pixels and even-numbered pixels having a level difference are continuously input. become.

(4) Advantages Corresponding to the Invention of Claim 5 In addition to the advantages (1) to (3), data compression is performed by dividing and compressing data for each system according to the system of the read data. Accordingly, it is possible to avoid a decrease in the compression ratio that occurs when data compression is not performed for each system due to a level difference (for example, a level difference between an odd-numbered pixel and an even-numbered pixel) that occurs when the analog processing of the previous stage is performed in another system. Becomes possible. (5) Effects corresponding to the invention of claim 6 The effects (1) to (4) can be realized in an image forming apparatus such as a copying machine and a facsimile, and the performance of the image forming apparatus can be improved. become.

[Brief description of the drawings]

FIG. 1 is a schematic view showing a structure of a DPPC according to an embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating an image reading apparatus according to an embodiment of the present invention.

FIG. 3 is a block diagram illustrating a first embodiment of a shading data generation circuit.

FIG. 4 is a block diagram showing a second embodiment of a shading data generation circuit.

FIG. 5 shows a detailed circuit of the control unit shown in FIG.

FIG. 6 is a timing chart of signals related to the control unit (shown in FIG. 5).

FIG. 7 shows a detailed circuit of a Ds' compression unit shown in FIG.

8 shows a timing chart of a signal (shown in FIG. 7) related to the Ds ′ compression section.

9 shows a detailed circuit of a Ds decompression unit shown in FIG.

FIG. 10 is a timing chart of a signal (shown in FIG. 9) related to the Ds expansion unit.

FIG. 11 shows a detailed circuit of a base storage unit shown in FIG. 4;

FIG. 12 is a timing chart of signals (shown in FIG. 11) related to the base storage unit.

FIG. 13 shows an example flow of a data generation procedure by a shading data generation circuit having a two-bank configuration.

FIG. 14 is a block diagram showing a third embodiment relating to a shading data generation circuit.

15 shows a detailed circuit of a base storage unit shown in FIG. 14;

FIG. 16 is a timing chart of signals (shown in FIG. 15) related to the base storage unit.

FIG. 17 shows an example of a conventional shading data generation circuit.

18 shows a timing chart of signals (illustrated in FIG. 17) related to the shading data generation circuit of FIG.

[Explanation of symbols]

11: Original, 12: Contact glass, C1: First carriage, C2
... second carriage, 13 ... exposure lamp,
14, 15, 16 ... mirror, 17 ... imaging lens,
18 ... light receiving element (image sensor),
Reference numeral 20: reference white plate 35: image reading device 100: control unit 20
0: shading data calculation unit, 300: variation storage unit, 400: base storage unit, 500:
Ds' compression section, 600 ... Ds expansion section.

Claims (6)

[Claims] 1. A shading for reading a reference white plate by a line image sensor while relatively moving the line image sensor in a sub-scanning direction intersecting the main scanning line, and for stabilizing a reading output of the sensor based on obtained white data. An image reading apparatus comprising means for generating correction data, wherein the shading correction data generation means includes a pixel row in which a shading correction data generated in a pixel unit in a pixel arrangement order shows a variation within a predetermined range. Means for dividing a base portion and a variable portion of the data and compressing the data of the base portion; a variable storage device for storing the data of the divided variable portion; and a base portion storage device for storing the compressed data of the base portion. Data from the variation storage means and the base storage means and restore the shading correction data. An image reading apparatus comprising a data decompression means. 2. The image reading apparatus according to claim 1, wherein said shading correction data generating means is based on the read white data of the current line and the shading correction data of the previous line restored by said data decompression means. An image reading apparatus for generating shading correction data by means for calculating shading correction data of a current line. 3. An image reading apparatus according to claim 1, wherein said base storage means is a storage means having a plurality of systems of FIFOs and operating said FIFOs sequentially. Image reading device. 4. The image reading apparatus according to claim 1, wherein said base storage means is a single system of storage means for operating consecutive addresses in a loop. . 5. The image reading apparatus according to claim 1, wherein the data compression unit is a unit that performs division / compression processing for each system according to the system of the read data. Image reading device. 6. An image forming apparatus comprising: the image reading apparatus according to claim 1; and means for forming an image based on image data output from the image reading apparatus. .