JP3801840B2 - Image processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention provides means for reading a document line by line in the main scanning direction, cutting out invalid pixels from the obtained image data for one line using a pixel counter, and storing only an effective image area in a line memory. The present invention relates to an image processing apparatus such as a digital copier provided.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, in a digital copying machine, which is a type of image processing apparatus, image data corresponding to a document read by a CCD (Charge Coupled Device) is AD converted, stored in a memory, and image data stored in the memory Various image processes are performed on the image. The image data stored in the memory is subjected to image processing and then output as print data from the laser system unit (LSU).
[0003]
As the memory, a first-in first-out line memory is often used to save capacity. The timing of reading and writing data in the line memory is performed by the line memory read / write control unit.
[0004]
In addition, before the image data subjected to the image processing is output as print data from the LSU, it is necessary to delete (mask) an invalid image area obtained by CCD or image processing in the main scanning direction. .
[0005]
Here, the image data writing / reading process and the image data masking process in the line memory in the conventional digital copying machine will be described below with reference to FIGS.
[0006]
11 shows a block diagram of a line memory read / write control unit in the conventional image processing apparatus, and FIG. 12 shows a timing chart of various signals in the line memory read / write control unit shown in FIG. Note that the numbers surrounded by ◯ shown in FIG. 11, for example, {circle around (1)}, etc. correspond to the numbers surrounded by ◯ added to each signal of the timing chart shown in FIG. 12.
[0007]
In the line memory / write control unit, as shown in FIG. When sync is input, the counter C starts counting up and an invalid pixel counter value CNT indicating the count value. C is output to the comparator C and the comparator D in the subsequent stage.
[0008]
The comparator C includes the invalid pixel counter value CNT. In addition to C, effective pixel start information AREA output from the effective pixel start position storage unit (register) strt is input. This effective pixel start information AREA strt is the horizontal sync signal h The number of clocks from sync to the start of the valid region is used. Thereby, the comparator C outputs the effective area start signal sel1 when the count value becomes larger than the start position of the effective pixel.
[0009]
On the other hand, the comparator D receives the invalid pixel counter value CNT. In addition to C, effective pixel end position information AREA output from the effective pixel end position storage unit (register) enc is entered. This effective pixel end position information AREA enc is the horizontal sync signal h The number of clocks from sync to the end of the valid region is used. Thereby, the comparator D outputs the effective area end signal sel2 when the count value becomes larger than the end position of the effective pixel.
[0010]
The effective area start signal sel1 and the effective area end signal sel2 are obtained by negating the logical sum by a subsequent NOR gate, and this is output to the selector as an image effective area signal SEL. Here, the image effective area signal SEL becomes a control signal in the selector. The selector selects output image data OUT from a line memory described later. data and image mask data MSK from a mask processing unit (not shown) data is input, and if the image is determined to be an effective area based on the image effective area signal SEL, the output image data OUT data is the print data V output as data, and if it is determined that it is outside the effective region, it is determined as an invalid pixel, and the image mask data MSK Mask the image with data and print the masked image data as print data V Output as data.
[0011]
Horizontal sync signal h In addition to the counter C, sync is input to the reset circuit.
[0012]
The reset circuit includes memory write start information (horizontal synchronization signal h) from a memory write start storage unit (register). The number of delayed clocks from sync) is input, and the reset signal RST1 is output to the subsequent line memory address control unit (magnification control) at a timing delayed based on this memory write start information. For example, when “8” is stored as the delay clock number in the memory write start storage unit, the horizontal synchronization signal h is sent from the reset circuit to the line memory address control unit. The reset signal RST1 is input for 8 clocks from sync. In other words, the line memory address control unit performs the horizontal synchronization signal h. After the sync is input, the write address starts counting up from 9 clocks.
[0013]
Further, the reset circuit includes memory read start information (horizontal synchronization signal h) from the memory read start storage unit (register). The number of delayed clocks from sync) is input, and a reset signal RST2 is output to the subsequent line memory address control unit (magnification control) at a timing delayed based on this memory read start information.
[0014]
The line memory address control unit is a part that generates an address signal for writing and reading image data to and from the line memory based on the input reset signal RST1 and reset signal RST2. The address signal for writing (address signal WR generated here) addr) is input to the comparator A at the subsequent stage, and an address signal for reading (address signal RD) addr) is input to the comparator B at the subsequent stage.
[0015]
In the line memory address control unit, for example, when 50% scaling processing is performed, if control is performed such that 1, 3, 5 and a write signal are generated, the line memory has half the number of pixels of the input image. So that the address signal WR Generates addr.
[0016]
The reset signal RST1 from the reset circuit is output to the counter A separately from the line memory address control unit, and the reset signal RST2 is output to the counter B provided separately from the counter A.
[0017]
The counter A starts counting up when the reset signal RST1 is released, and the write control counter value CNT A is output to the comparator A. The counter B starts counting up when the reset signal RST2 is canceled, and the read control counter value CNT B is output to the comparator B.
[0018]
The comparators A and B are composed of a plurality of comparators and an OR gate.
[0019]
The comparator A has a write control counter value CNT. A and address signal WR addr and the write signal / WE are output to the line memory. That is, the comparator A is valid when the counter value is 1 and 1 and 3 are stored in a line memory storage register (not shown), and valid when the counter value is 3. It consists of a comparator and a gate for taking the logical sum of the outputs of the comparator. Thus, a circuit that outputs the write signal / WE when the counter is 1 or 3 can be configured.
[0020]
Similarly, the comparator B outputs the read control counter value CNT. B and address signal RD addr and the read signal / RE are output to the line memory.
[0021]
In the line memory, the writing start and reading start of image data are controlled independently, and the horizontal synchronization signal h Since it is necessary to make it arbitrarily variable from sync, dedicated counters (counter A and counter B) are required for writing and reading.
[0022]
Here, the comparator A has a write control counter value CNT which is a count value of the counter A. A and the address signal WR, which is a write address signal controlled by thinning, output from the line memory address control unit Compare with addr. In general, the comparison between the two is often performed by reducing the circuit scale by using only the lower bits.
[0023]
In the above comparator A, the write control counter value CNT A and address signal WR If addr is the same (the lower bits are the same), the write signal / WE is output to the line memory.
[0024]
When the line memory receives the write signal / WE, the input image data IN Store data.
[0025]
Similarly, in the comparator B, the read control counter value CNT which is the count value of the counter B Thinning-controlled address signal RD output from B and the line memory address control unit For example, if the lower bits are the same, the read signal / RE is output to the line memory.
[0026]
When the line memory receives the read signal / RE, the line memory outputs the stored image data to the output image data OUT. Read as data. The read image data is input to the selector, where it is determined whether it is a valid area or an invalid area based on the image valid area signal SEL. output as data, and if it is an invalid area, it is masked and the mask data is printed Output as data.
[0027]
[Problems to be solved by the invention]
However, since the conventional image processing apparatus uses different reset signals for the address counter and the pixel position counter used in writing / reading image data to / from the line memory, the counter circuit ( Counter A, counter B, and counter C) must be provided separately.
[0028]
In general, a plurality of line memories exist in the image processing apparatus, and each stores image data for filters and electronic scaling. For this reason, when each of the plurality of line memories has a counter circuit and performs a specific reset control, various problems such as an increase in circuit scale, a complicated circuit, and complicated control have been caused.
[0029]
The present invention has been made to solve the above-described problems, and its object is to increase the number of line memories by using a common counter circuit for the line memory address counter and the pixel position counter. An object of the present invention is to provide an image processing apparatus capable of suppressing an increase in circuit scale and simplifying a circuit and simplifying control.
[0030]
[Means for Solving the Problems]
  In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit, an invalid pixel counting unit that counts invalid pixels that are invalid image regions of image data for one line based on a horizontal synchronization signal indicating a base point of line image data, and the invalid pixel counting unit. Invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory by setting the counted invalid pixel as an invalid image area, and the image data writing / reading control means includes the invalid pixel counting means Control to control writing and reading of image data to the line memory based on the count value of Writing start information storage means for generating a signal, and the image data writing / reading control means stores the number of clocks from the horizontal synchronization signal to the start of writing of the image data to the line memory as writing start information; Subtracting means for subtracting the number of clocks stored in the writing start information storage means based on the value counted by the invalid pixel counting means, and based on the output value of the subtracting means, A control signal for controlling writing is generated from among control signals for controlling writing and reading of image data.
In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit, an invalid pixel counting unit that counts invalid pixels that are invalid image regions of image data for one line based on a horizontal synchronization signal indicating a base point of line image data, and the invalid pixel counting unit. Invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory by setting the counted invalid pixel as an invalid image area, and the image data writing / reading control means includes the invalid pixel counting means Control to control writing and reading of image data to the line memory based on the count value of Writing start information storage means for generating a signal, and the image data writing / reading control means stores the number of clocks from the horizontal synchronization signal to the start of writing of the image data to the line memory as writing start information; A reset circuit that generates a reset signal based on the horizontal synchronization signal and the number of clocks stored in the write start information storage means, and the reset signal generated by the reset circuit is input to the reset circuit Address control means for outputting an address control signal for controlling the write address of the image data to the line memory at the timing when the signal is released, and the number of clocks stored in the write start information storage means is invalidated. A subtracting means for subtracting based on the value counted by the pixel counting means, and an address output from the address control means. Control for controlling writing of control signals for controlling writing and reading of image data to and from the line memory based on the comparison result Write control signal generating means for generating a write control signal as a signal is provided.
In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit, an invalid pixel counting unit that counts invalid pixels that are invalid image regions of image data for one line based on a horizontal synchronization signal indicating a base point of line image data, and the invalid pixel counting unit. Invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory by setting the counted invalid pixel as an invalid image area, and the image data writing / reading control means includes the invalid pixel counting means Control to control writing and reading of image data to the line memory based on the count value of A read start information storage means for generating a signal, and the image data write / read control means stores the number of clocks from the horizontal synchronization signal to the start of reading of the image data from the line memory as read start information; A reset signal is generated based on the horizontal synchronization signal and the number of clocks stored in the readout start information storage means. And an address for outputting an address control signal for controlling the read address of the image data from the line memory at a timing when the reset signal generated by the reset circuit and the reset circuit is input. A control means; a subtraction means for subtracting the number of clocks stored in the readout start information storage means based on a value counted by the invalid pixel counting means; an address control signal output from the address control means; The value subtracted by the subtractor means is compared, and based on the comparison result, a read control signal is used as a control signal for controlling reading out of control signals for controlling writing and reading of image data from the line memory. And a read control signal generating means for generating.
In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit, an invalid pixel counting unit that counts invalid pixels that are invalid image regions of image data for one line based on a horizontal synchronization signal indicating a base point of line image data, and the invalid pixel counting unit. Invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory by setting the counted invalid pixel as an invalid image area, and the image data writing / reading control means includes the invalid pixel counting means Control to control writing and reading of image data to the line memory based on the count value of Writing start information storage means for generating a signal, and the image data writing / reading control means stores the number of clocks from the horizontal synchronization signal to the start of writing of the image data to the line memory as writing start information; The writing interval storage means for storing the writing interval of the image data to the line memory, the number of clocks stored in the writing start information storage means and the count value from the invalid pixel counting means are compared. The first control signal generating means for starting to output the first control signal when the number of clocks and the count value are equal are compared with the writing interval and the count value from the invalid pixel counting means. As a control signal for controlling writing among control signals for controlling writing and reading of image data to and from the line memory when the count interval is equal to the count interval Second control signal generating means for outputting two control signals, and second output from the second control signal generating means based on the output timing of the first control signal from the first control signal generating means. The control signal is output to the line memory.
In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit, an invalid pixel counting unit that counts invalid pixels that are invalid image regions of image data for one line based on a horizontal synchronization signal indicating a base point of line image data, and the invalid pixel counting unit. Invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory by setting the counted invalid pixel as an invalid image area, and the image data writing / reading control means includes the invalid pixel counting means Control to control writing and reading of image data to the line memory based on the count value of A read start information storage means for generating a signal, and the image data write / read control means stores the number of clocks from the horizontal synchronization signal to the start of reading of the image data from the line memory as read start information; Read interval storage means for storing the read interval of the image data to the line memory, the number of clocks stored in the read start information storage means and the count value from the invalid pixel count means are compared, and the number of clocks Third control signal generating means for starting to output a third control signal when the count value is equal, the readout interval and the count value from the invalid pixel counting means are compared, and the readout interval and the count value As control signals for controlling reading out of control signals for controlling writing and reading of image data to and from the line memory when Fourth control signal generating means for outputting four control signals, and a fourth output from the fourth control signal generating means based on the output timing of the third control signal from the third control signal generating means. The control signal is output to the line memory.
In order to solve the above problems, the image processing apparatus of the present invention records image data for one line. A line memory to be stored, image data writing / reading control means for controlling writing and reading of image data to and from the line memory, and a horizontal synchronization signal indicating a base point of the line image data, for one line Invalid pixel counting means that counts invalid pixels that are invalid image areas of the image data, and the invalid image area from the image data stored in the line memory with invalid pixels counted by the invalid pixel counting means as invalid image areas And the image data writing / reading control means outputs a control signal for controlling writing and reading of the image data to and from the line memory based on the count value by the invalid pixel counting means. The image data writing / reading control means generates the laser data from the horizontal synchronizing signal. Read start information storage means for storing the number of clocks until the start of reading of image data to the memory as read start information, and a value obtained by counting the number of clocks stored in the read start information storage means by the invalid pixel counting means Subtracting means for subtracting on the basis of the subtracting means, and generating a control signal for controlling reading out of control signals for controlling writing and reading of image data to and from the line memory based on an output value of the subtracting means. It is said.
In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit, an invalid pixel counting unit that counts invalid pixels that are invalid image regions of image data for one line based on a horizontal synchronization signal indicating a base point of line image data, and the invalid pixel counting unit. Invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory by setting the counted invalid pixel as an invalid image area, and the image data writing / reading control means includes the invalid pixel counting means Control to control writing and reading of image data to the line memory based on the count value of Writing start information storage means for generating a signal, and the image data writing / reading control means stores the number of clocks from the horizontal synchronization signal to the start of writing of the image data to the line memory as writing start information; The clock number stored in the write start information storage means is compared with the count value from the invalid pixel count means, and when the clock number and the count value are equal, output of the first control signal is started. First control signal generating means, and generating a control signal for controlling writing among control signals for controlling writing and reading of image data to and from the line memory based on the first control signal. Yes.
In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit, an invalid pixel counting unit that counts invalid pixels that are invalid image regions of image data for one line based on a horizontal synchronization signal indicating a base point of line image data, and the invalid pixel counting unit. Invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory by setting the counted invalid pixel as an invalid image area, and the image data writing / reading control means includes the invalid pixel counting means Control to control writing and reading of image data to the line memory based on the count value of A read start information storage means for generating a signal, and the image data write / read control means stores the number of clocks from the horizontal synchronization signal to the start of reading of the image data from the line memory as read start information; Third control for comparing the number of clocks stored in the read start information storage means with the count value from the invalid pixel counting means and starting to output a third control signal when the number of clocks is equal to the count value Signal generating means, and generating a control signal for controlling reading out of control signals for controlling writing and reading of image data to and from the line memory based on the third control signal.
In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. Based on the control means and the horizontal synchronization signal indicating the base point of the line image data, the invalid pixel that becomes the invalid image area in the image data for one line is counted. Invalid pixel counting means, and invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory with the invalid pixel counted by the invalid pixel counting means as an invalid image area. The data writing / reading control means stores write start information storage means for storing the number of clocks from the horizontal synchronization signal to the start of writing of image data to the line memory as write start information, and the write start information storage. Subtracting means for subtracting the number of clocks stored in the means based on the value counted by the invalid pixel counting means, and controlling the writing of image data to the line memory based on the output value of the subtracting means. In addition to generating a control signal, it starts reading image data from the horizontal sync signal to the line memory. Read start information storage means for storing the number of clocks as read start information, and subtracting means for subtracting the clock number stored in the read start information storage means based on the value counted by the invalid pixel count means. The control signal for controlling the reading of the image data to the line memory is generated based on the output value of the subtracting means.
In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit, an invalid pixel counting unit that counts invalid pixels that are invalid image regions of image data for one line based on a horizontal synchronization signal indicating a base point of line image data, and the invalid pixel counting unit. An invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory using the counted invalid pixels as an invalid image area, and the image data writing / reading control means receives the horizontal synchronization signal from the horizontal synchronization signal. Write start information for storing, as write start information, the number of clocks until the start of image data writing to the line memory. A storage means, a reset circuit for generating a reset signal based on the horizontal synchronization signal and the number of clocks stored in the write start information storage means, and a reset signal generated by the reset circuit are input The address control means for outputting an address control signal for controlling the write address of the image data to the line memory at the timing when the reset signal is released, and the number of clocks stored in the write start information storage means Is subtracted based on the value counted by the invalid pixel counting means, the address control signal output from the address control means is compared with the value subtracted by the subtractor means, and the comparison result is Write control signal for generating a write control signal for controlling the writing of image data to the line memory based on Read start information storage means for storing, as read start information, the number of clocks from the horizontal sync signal to the start of reading of image data from the line memory, and the horizontal sync signal and the read start. A reset circuit that generates a reset signal based on the number of clocks stored in the information storage means, and the reset signal generated by the reset circuit is input and at the timing when the reset signal is released, the line Address control means for outputting an address control signal for controlling the read address of the image data from the memory, and the number of clocks stored in the read start information storage means is reduced based on the value counted by the invalid pixel counting means. A subtraction means, an address control signal output from the address control means, and an upper A read control signal generating means for comparing the values subtracted by the subtractor means and generating a read control signal for controlling the reading of the image data from the line memory based on the comparison result. It is characterized by.
In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit, an invalid pixel counting unit that counts invalid pixels that are invalid image regions of image data for one line based on a horizontal synchronization signal indicating a base point of line image data, and the invalid pixel counting unit. An invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory using the counted invalid pixels as an invalid image area, and the image data writing / reading control means receives the horizontal synchronization signal from the horizontal synchronization signal. Write start information for storing, as write start information, the number of clocks until the start of image data writing to the line memory. Storage means, between the writing of image data into the line memory The write interval storage means for storing the interval, the number of clocks stored in the write start information storage means and the count value from the invalid pixel count means are compared, and the clock number is equal to the count value When the first control signal generating means for starting to output the first control signal is compared with the writing interval and the count value from the invalid pixel counting means, and the writing interval and the count value are equal And a second control signal generating means for outputting a second control signal for controlling the writing of the image data to the line memory, based on the output timing of the first control signal from the first control signal generating means. The second control signal output from the second control signal generating means is output to the line memory, and the clock from the horizontal synchronization signal to the start of reading image data from the line memory Read start information storage means for storing the read start information, read interval storage means for storing the read interval of the image data to the line memory, the number of clocks stored in the read start information storage means and the invalid pixel A third control signal generating means for comparing the count value from the count means and starting to output a third control signal when the number of clocks and the count value are equal; and from the readout interval and the invalid pixel count means A fourth control signal generating means for comparing the count value and outputting a fourth control signal for controlling reading from the image data to the line memory when the read interval is equal to the count value; Based on the output timing of the third control signal from the three control signal generating means, the fourth control signal output from the fourth control signal generating means is output to the line memory. It is characterized in Rukoto.
  In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit, an invalid pixel counting unit that counts invalid pixels that are invalid image regions of image data for one line based on a horizontal synchronization signal indicating a base point of line image data, and the invalid pixel counting unit. An invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory using the counted invalid pixels as an invalid image area, and the image data writing / reading control means receives the horizontal synchronization signal from the horizontal synchronization signal. Write start information for storing, as write start information, the number of clocks until the start of image data writing to the line memory. Comparing the number of clocks stored in the storage means and the write start information storage means with the count value from the invalid pixel count means, and when the number of clocks and the count value are equal, the first control signal is First control signal generating means for starting output, generating a control signal for controlling the writing of image data to the line memory based on the first control signal, and generating the control signal from the horizontal synchronization signal from the line memory. Read start information storage means for storing the number of clocks until the start of reading of image data as read start information, and compare the clock number stored in the read start information storage means with the count value from the invalid pixel count means. And third control signal generating means for starting to output a third control signal when the number of clocks and the count value are equal, It is characterized by generating a control signal for controlling the reading of image data into the line memory based on the signal.
In order to solve the above problems, an image processing apparatus of the present invention stores a line memory for storing image data for one line, and image data writing / reading for controlling writing and reading of image data to and from the line memory. A control unit; an invalid pixel counting unit that counts invalid pixels that are invalid image regions in one line of image data based on a horizontal synchronization signal that indicates a base point of the line image data; and the invalid pixel counting unit. And invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory. The image data writing / reading control means includes the invalid pixel. Based on the count value by the counting means, the writing and reading of the image data to the line memory are controlled. It is characterized by generating a control signal.
[0031]
According to the above configuration, the image data writing / reading control unit generates the control signal for controlling the writing and reading of the image data to / from the line memory based on the count value by the invalid pixel counting unit. In addition to the invalid pixel counting means, there is no need to provide the counting means (line memory address counter) which is necessary for generating control signals for controlling writing and reading of image data to and from the line memory.
[0032]
As a result, the line memory address counter and the pixel position counter (invalid pixel counting means) can be shared, so that the increase in the circuit scale accompanying the increase in the number of line memories is suppressed, the circuit is simplified and the control is simplified Can be achieved.
[0033]
Specifically, it is conceivable to use a subtracter having a circuit scale smaller than that of the counter circuit in order to count the address of the line memory. By using this subtracter, the circuit scale in the image processing apparatus can be further reduced and simplified.
[0034]
As the image data writing / reading control means using such a subtracter (subtraction means), the following can be considered.
[0035]
First, as an example of generating a write control signal for controlling the writing of image data to the line memory, the following image processing apparatus can be considered.
[0036]
  The image data writing / reading control means includes a writing start information storage means for storing, as writing start information, the number of clocks from the horizontal synchronization signal to the start of image data writing to the line memory, the horizontal synchronization signal, A reset circuit that generates a reset signal based on the number of clocks stored in the write start information storage means, and a timing at which the reset signal generated by the reset circuit is input and the reset signal is released The address control means for outputting an address control signal for controlling the write address of the image data to the line memory, and the number of clocks stored in the write start information storage means are counted by the invalid pixel counting means. Subtracting means for subtracting based on the value, address control signal output from the address control means, and the subtraction A write control signal generating means for comparing the value subtracted by the means and generating a write control signal for controlling the writing of the image data to the line memory based on the comparison result. It is done.
[0037]
Further, as an example of generating a read control signal for controlling reading of image data from the line memory, the following image processing apparatus can be considered.
[0038]
The image data writing / reading control means includes a read start information storage means for storing, as read start information, the number of clocks from the horizontal synchronization signal to the start of reading of image data from the line memory, the horizontal synchronization signal, and the read The reset circuit that generates a reset signal based on the number of clocks stored in the start information storage means, and the reset signal generated by the reset circuit is input and at the timing when the reset signal is released, Address control means for outputting an address control signal for controlling the read address of the image data from the line memory, and the number of clocks stored in the read start information storage means based on the value counted by the invalid pixel count means Subtracting means for subtracting, an address control signal output from the address control means, And a read control signal generating means for comparing a value subtracted by the subtractor means and generating a read control signal for controlling reading of the image data from the line memory based on the comparison result. Conceivable.
[0039]
As described above, the reason why the circuit scale can be reduced when the subtracting means (subtractor) is used is as follows.
[0040]
For example, an 8-bit counter as a counter circuit requires 96 gates, whereas an 8-bit subtractor requires 40 gates. Therefore, the write control counter (write address counter) and the read control counter (read address counter) are changed to subtracters, respectively, so that (96-40) × 2 = 112 gates per line memory. Will be reduced.
[0041]
In addition, since a plurality of line memories are required, a writing and reading circuit is required for one line memory. Therefore, when the line memory has 50 lines, for example, 112 × 50 = 5600 gates. Thus, the circuit can be simplified and the cost can be reduced.
[0042]
Other examples of the image data writing / reading control means include the following.
[0043]
  When image data writing control is performed, the image data writing / reading control means stores the number of clocks from the horizontal synchronization signal to the start of writing image data to the line memory as writing start information. Start information storage means, write interval storage means for storing the write interval of image data to the line memory, the number of clocks stored in the write start information storage means and the count from the invalid pixel count means A first control signal generating means for outputting a first control signal when the number of clocks and the count value are equal, and comparing the write interval and the count value from the invalid pixel count means And a second control signal generating means for outputting a second control signal for controlling the writing of image data to the line memory when the writing interval is equal to the count value. Based on the timing of the output of the first control signal from the first control signal generating means may output the second control signal outputted from said second control signal generating means to the line memory.
[0044]
  When image data read control is performed, as the image data write / read control means, the number of clocks from the horizontal synchronization signal to the start of reading image data from the line memory is stored as read start information. Start information storage means, read interval storage means for storing the read interval of image data to the line memory, the number of clocks stored in the read start information storage means, and the count value from the invalid pixel count means A third control signal generating means for starting to output a third control signal when the number of clocks and the count value are equal, and comparing the readout interval with the count value from the invalid pixel counting means, A fourth control signal for outputting a fourth control signal for controlling reading from the image data to the line memory when the reading interval is equal to the count value; And a fourth control signal output from the fourth control signal generating means based on the output timing of the third control signal from the third control signal generating means. May be.
[0045]
Each of the first to fourth control signal generating means compares the input signals and outputs a control signal based on the comparison result, and there is no need to perform a reset operation by the reset signal. In other words, the above configuration does not require a reset circuit that generates a reset signal based on the horizontal synchronization signal, so that the total circuit of the image processing apparatus can be simplified and the cost can be reduced.
[0046]
DETAILED DESCRIPTION OF THE INVENTION
One embodiment of the present invention will be described below. In this embodiment, the case where the image processing apparatus of the present invention is applied to a digital copying machine will be described.
[0047]
The digital copying machine described in this embodiment has a composite function capable of performing a copying operation and a printer operation together with a facsimile operation. FIG. 2 is a diagram showing a schematic configuration of the digital copying machine 30 according to the present embodiment.
[0048]
That is, the main body of the digital copying machine 30 is roughly composed of a scanner unit 31 and a laser recording unit 32 as shown in FIG.
[0049]
The scanner unit 31 is provided as an image input device in the digital copying machine 30 for reading a document image. In addition to the document table 35 made of transparent glass, the scanner unit 31 is a double-sided automatic document feeder (Reversing Automatic Document). Feeder (hereinafter abbreviated as RADF) 36 and scanner unit 40.
[0050]
The scanner unit 31 sequentially reads the images one by one from the document placed on the document placement table 35. The document image read by the scanner unit 31 is sent as image data to an image data input unit described later, and predetermined image processing is performed on the image data.
[0051]
The RADF 36 conveys documents set on a predetermined document tray (not shown) one by one to the document placing table 35. Then, after the document image is read by the scanner unit 40, it has a function of carrying it out to a predetermined take-out position. The RADF 36 can also turn over the original after the original image is read by the scanner unit 40 and transport it to the original placement table 35 again.
[0052]
Therefore, the RADF 36, in addition to the single-sided conveyance path used when reading only one side of a document, the double-sided conveyance path used when reading both sides, a guide for switching the conveyance path to be used, and the document in each conveyance path It has a sensor and a control unit for confirming the state. Using such a RADF 36, the scanner unit 31 can cause the scanner unit 40 to read images on both sides of a document. Since the detailed configuration of the RADF 36 is well known, the description thereof is omitted in the present embodiment.
[0053]
A scanner unit 40 constituting a scanner unit 31 for reading an image of a document on the document table 35 includes a lamp reflector assembly 41 that exposes the document surface, and a reflected light image from the document as a photoelectric conversion element (CCD). In order to guide the reflected light image from the first scanning unit 40a, which is mounted with the first reflecting mirror 42a for reflecting the reflected light from the original for guiding to the photoelectric conversion element (CCD), to the photoelectric conversion element (CCD). A second scanning unit 40b on which the second and third reflection mirrors 42b and 42c are mounted, a photoelectric conversion element (CCD) for converting a reflected light image from the original into an electrical image signal through each of the reflection mirrors described above. An optical lens 43 for forming an image on the top and the CCD element 44 described above for converting a reflected light image from an original into an electrical image signal.
[0054]
The scanner unit 31 moves the scanner unit 40 along the lower surface of the document placement table 35 while sequentially placing the document to be read on the document placement table 35 by operations related to the RADF 36 and the scanner unit 40. The document image is configured to be read.
[0055]
In particular, the first scanning unit 40a travels along the document placement table 35 from the left to the right in the drawing at a constant traveling speed V, and the second scanning unit 40b includes the first scanning unit 40a. The scanning control is performed in parallel with the first scanning unit 40a in the same direction as the first scanning unit 40a at a speed of half the traveling speed V, that is, V / 2.
[0056]
As a result, the image of the document placed on the document placement table 35 is sequentially formed on the CCD element 44 for each line, and the image is read.
[0057]
Image data obtained by reading a document image with the scanner unit 40 is sent to an image processing unit to be described later, subjected to various processes, temporarily stored in the memory of the image processing unit, and according to an output instruction. The image in the memory is read out and transferred to the laser recording unit 32 to form an image on the recording sheet.
[0058]
The laser recording unit 32 includes a sheet conveyance system that is a recording material for forming an image, a laser writing unit (LSU) 46, and an electrophotographic process unit 47 for forming an image.
[0059]
The LSU 46 includes a semiconductor laser light source that emits laser light in accordance with image data read from the memory after being read by the scanner unit 40 or image data transferred from an external device, and an equiangular velocity of the laser light. A polygon mirror for deflecting, an f-θ lens for correcting the laser light deflected at a constant angular velocity so as to be deflected at a constant angular velocity on the photosensitive drum constituting the electrophotographic process unit 47, and the like are provided.
[0060]
The electrophotographic process unit 47 includes a charging device, a developing device, a transfer device, a peeling device, a cleaning device, and a static eliminator around a known photosensitive drum.
[0061]
A sheet conveying mechanism 50 as a sheet conveying system is disposed below the electrophotographic process unit 47.
[0062]
The sheet conveying mechanism 50 supplies recording paper to the electrophotographic process unit 47, fixes the image transferred on the recording paper, and discharges the sheet to the outside. 51 to 53, a manual paper feeder 54, a fixing device 49, a resupply path 56, a paper discharge roller 57, a duplex copying unit 55, and a post-processing device 34.
[0063]
The transport unit 33 is for transporting the recording paper from the cassette paper feed devices 51 to 53, the manual paper feed device 54, or the refeed path 56 to a predetermined transfer position in the electrophotographic process unit 47. The transfer device is arranged at the transfer position.
[0064]
The cassette paper feeding devices 51 to 53 are for storing recording paper for transfer and for feeding the recording paper to the transport unit 33 during transfer.
[0065]
The manual paper feeding device 54 is a device for supplying recording paper of a type not stored in the cassette paper feeding devices 51 to 53 to the transport unit 33.
[0066]
The double-sided copying unit 55 is for re-supplying the recording paper to the transport unit 33 in order to form an image on the back surface of the recording paper after the toner image is fixed.
[0067]
The resupply path 56 is a path for transporting the recording paper after image formation to the duplex copying unit 55.
[0068]
The paper discharge roller 57 is a transport roller for supplying the recording paper discharged from the fixing device 49 to either the post-processing device 34 or the resupply path 56.
[0069]
The post-processing device 34 is for performing post-processing such as stapling on the discharged recording paper. Since the post-processing device 34 has a well-known configuration, detailed description thereof is omitted.
[0070]
Here, the control system of the digital copying machine 30 having the above configuration will be described below with reference to the block of FIG.
[0071]
As shown in FIG. 3, the digital copying machine 30 includes an operation panel board 100, a machine control board 200, a CCD board 300, and a main image processing board as boards constituting the control system in addition to the members shown in FIG. 400, a sub image processing board 500, and an expansion board group (printer board 601, function expansion board 602, FAX board 603) 600. These boards are used for controlling each member in the digital copying machine 30 and processing an image read by the scanner unit 31.
[0072]
Each board will be described below.
[0073]
(Operation panel board 100)
The operation panel board 100 located at the upper right in the figure is basically controlled by a sub central processing unit (CPU) 101 and relates to the display surface of the LCD display unit 104 arranged on the operation panel 103 and various modes. It manages operation inputs from the operation key group 105 for inputting instructions.
[0074]
A memory 102 is provided for storing various control information on the operation panel 103 such as data input from the operation key group 105 and information to be displayed on the LCD screen of the LCD display unit 104.
[0075]
In the above-described configuration, in the operation panel board 100, the sub CPU 101 performs control data communication with the main central processing unit (CPU) 401 to instruct operation of the digital copying machine 30.
[0076]
Further, the main CPU 401 transfers a control signal indicating the operation state of the digital copying machine 30 to the sub CPU 101, so that the apparatus is currently in the state through the screen of the LCD display unit 104 of the operation panel 103. The operator is informed of whether or not.
[0077]
(Machine control board 200)
The machine control board 200 is entirely controlled by a sub central processing unit (CPU) 201, and includes an automatic document feeder 203 such as ADF / RADF (corresponding to RADF 36 in FIG. 2), a reading scanner unit for reading a document image. 204 (corresponding to the scanner unit 31 in FIG. 2), a process unit 205 for reproducing image information as an image (corresponding to the electrophotographic process unit 47 in FIG. 2), and a sheet on which an image is recorded from the storage unit to the process unit 205. A sheet feeding / conveying section 206 (corresponding to the sheet conveying mechanism 50 in FIG. 2), and a duplex unit that reversely conveys the sheet so that the sheet on which the image is recorded is reversed to form an image on both sides of the sheet. 207 (corresponding to the duplex copying unit 55 in FIG. 2), a finisher for performing post-processing such as stapling on a sheet on which an image is recorded. Sha 208 manages the like (corresponding to the post-processing apparatus 34 in FIG. 2).
[0078]
(CCD board 300)
The CCD board 300 includes a CCD 301 for electrically reading a document image (corresponding to the CCD element 44 in FIG. 2), a circuit (CCD gate array) 302 for driving the CCD 301, and gain adjustment of analog data output from the CCD 301. An analog circuit 303 to be performed, an AD converter 304 that converts the analog output of the CCD 301 into a digital signal and outputs it as electronic data, and the like, are controlled by the main CPU 401.
[0079]
(Main image processing board 400)
The main image processing board 400 is controlled by the main CPU 401, and based on the electronic data of the original image sent from the CCD board 300, the shading correction is performed so that the gradation of the image can be expressed in a desired state. A multivalued image processing unit 402 that performs processing in the state of multivalued image data such as density correction, region separation, filter processing, MTF correction, resolution conversion, electronic zoom (magnification processing), and gamma correction. A memory 403 for storing various control information such as image data or process procedure management, and a laser controller 404 for controlling data transfer to the LSU 46 side in order to reproduce the image with the processed image information. Is done.
[0080]
(Sub image processing board 500)
The sub image processing board 500 is connected to the main image processing board 400 by a connector, and the binary image processing unit 501 controlled by the main CPU 401 on the main image processing board 400, binary image information subjected to image processing, Alternatively, a memory for storing and managing processing control information and a gate array 502 for controlling the memory, and a plurality of document image information are stored and managed, and a plurality of document images are repeatedly read out in a desired number of copies. A hard disk for generating a copy, a gate array 503 for controlling the hard disk, a SCSI as an external interface, a gate array 504 for controlling the SCSI, and the like.
[0081]
The binary image processing unit 501 described above is a processing unit that converts multi-valued image information into a binary image, a processing unit that rotates an image, and a binary scaling (zoom) process that performs scaling processing of a binary image. A fax interface (FAX I / F) is also provided so that FAX images can be transmitted and received via communication means.
[0082]
Next, the processing of image data and the flow of image data as a copy mode in the digital copying machine 30 configured as described above will be described in detail below.
[0083]
(Copy mode)
Documents set at predetermined positions on the RADF 36 of the digital copying machine 30 are sequentially supplied one by one onto the document placement table 35 of the scanner unit 40, and images of the documents are sequentially read by the configuration of the scanner unit 40 described above. And transferred to the main image processing board 400 as 8-bit electronic data.
[0084]
The 8-bit electronic data transferred to the main image processing board 400 is subjected to predetermined processing on the multi-value image processing unit 402 as 8-bit electronic image data.
[0085]
The 8-bit electronic image data is subjected to processing such as gamma correction, and sent to the LSU 46 via the laser controller 404.
[0086]
As a result, the document image read by the scanner unit 31 of the digital copying machine 30 is output from the laser recording unit 32 as a copy image having gradation.
[0087]
(Electronic RDH function in copy mode)
Similarly, the originals set at predetermined positions of the RADF 36 of the digital copying machine 30 are sequentially supplied one by one onto the original placement table 35 of the scanner unit 40, and the images of the originals are sequentially supplied according to the configuration of the scanner unit 40 described above. It is read and transferred to the main image processing board 400 as 8-bit electronic data.
[0088]
The 8-bit electronic data transferred to the main image processing board 400 is subjected to predetermined processing on the multi-value image processing unit 402 as 8-bit electronic image data.
[0089]
Then, this 8-bit electronic image data is sent from the connector connecting portion 405 on the main image processing board 400 side to the sub image processing board 500 side via the connector connecting portion 505 on the sub image processing board 500 side. The multi-value binary conversion unit of the value image processing unit 501 converts 8-bit electronic image data into 2-bit electronic image data together with processing such as error diffusion.
[0090]
The reason why 8-bit electronic image data is converted into 2-bit electronic image data including processing such as error diffusion is that a problem in terms of image quality occurs only by performing multi-level binary conversion. .
[0091]
The reason why the 8-bit electronic image data is converted into 2-bit electronic image data is to consider the storage capacity of the image.
[0092]
The 2-bit electronic image data converted in this way is transferred to a disk memory such as a hard disk for each document and temporarily stored and managed.
[0093]
When all the originals set on the RADF 36 of the digital copying machine 30 are read and processed, the 2-bit electronic image data temporarily stored in the hard disk is repeated for the number of copies designated by the control of the gate array. The read 2-bit electronic image data is sent again to the main image processing board 400 via the connector connection portions 405 and 505, and is subjected to processing such as gamma correction to the LSU 46 via the laser controller 404. Sent.
[0094]
In the present embodiment, an example is described in which all the original group images are read and then the image group is repeatedly read by a desired number of copies. However, the present invention is not limited to this. The image output may be configured to be sequentially output when a predetermined number of images are prepared.
[0095]
In this case, the original image read by the scanner unit 31 of the digital copying machine 30 can be output from the laser recording unit 32 as a copy image having gradation.
[0096]
Here, the block diagram of the digital copying machine is shown in FIG. 1 and will be described in detail below so that the characteristic part of the present invention becomes clear.
[0097]
As shown in FIG. 1, the digital copying machine converts image data read by a CCD 301 into a digital signal by an AD converter 304, and stores a line memory 1 for storing image data for one line of the digital image data. A line memory read / write control unit 2 as image data writing / reading control means for controlling writing and reading of image data to and from the line memory 1 and a horizontal synchronization signal indicating a base point of the line image data Based on the counter 3, which is an invalid pixel counting means for counting invalid pixels that become invalid image areas, and the invalid pixels counted by the counter 3 as invalid image areas, the image data stored in the line memory 1 And an invalid pixel cutting unit 4 which is an invalid image cutting means for cutting out an invalid image region.
[0098]
The line memory 1 is a first-in first-out type FIFO memory that stores images in the line direction, and exchanges image data with the main image processing board 400 or the sub image processing board 500, which is the image processing unit. It has become.
[0099]
The line memory read / write control unit 2 generates a control signal for controlling writing and reading of image data to and from the line memory 1 based on the count value of the counter 3.
[0100]
The invalid pixel cutting unit 4 masks (deletes) invalid pixels from the image data from the line memory 1 and outputs the masked data to the LSU 46 described above. A laser controller 404 as shown in FIG. 3 exists between the invalid pixel cutting unit 4 and the LSU 46, but is omitted in FIG. 1 for convenience of explanation.
[0101]
Details of the configuration of the image processing apparatus will be described below. Before that, the relationship between the line memory 1 and the invalid pixel data will be described with reference to FIGS. 4 and 5. FIG.
[0102]
In the digital copying machine, a horizontal synchronizing signal that is a base point of one line of image data is created by the LSU 46. The generated horizontal synchronizing signal is used for resetting the counter 3 serving as a pixel position counter. The pixel position counter reset by the input of the horizontal synchronization signal counts up by one every time a clock is input. A mask processing unit (not shown) determines invalid pixels based on the counted up value (hereinafter referred to as a count value), and as a result, masks pixels determined to be invalid pixels at a constant density. In this case, if the mask process is not performed, a non-image portion composed of invalid pixels is output, causing a problem such as black streaks.
[0103]
In general, one line data includes dust data (invalid image data) at both sides of the effective image data, that is, at the beginning and end of the main scanning direction. Therefore, only effective image data obtained by removing dust data from one line data must be written to the line memory (fifo) 1.
[0104]
Specifically, as shown in FIG. 4, pixel counter values (dust removal counter values) for one line data are 1, 2, 3,..., N, n + 1, n + 2, n + 3, and n + 4. That is, one line data is counted n + 4 times. The dust data indicates pixels corresponding to the beginning (dust removal counter values 1 and 2) and the end (dust removal counter values n + 3 and n + 4) in the main scanning direction, and these pixels are invalid pixels.
[0105]
Therefore, the effective image data is stored in the line memory 1 based on the fifo control counter value (1, 2, 3,..., N) and the fifo write (WE) signal.
[0106]
On the other hand, the line memory 1 is a storage element that stores image data for one line (one line data) as described above. When the write signal / WE is input, the line memory 1 stores one pixel at the address 1 and When one write signal / WE is input, one pixel is stored at address 2. Similarly, every time a read signal / RE is inputted, it is outputted pixel by pixel.
[0107]
Here, the control signals of the write signal / WE and the read signal / RE input to the line memory 1 are detected by the CPU (or a dedicated counter circuit) that the conventional valid area is entered, and pass through the address control unit. Thus, a control signal (line memory write / read control signal in the block diagram) is output.
[0108]
The first image processing apparatus of the present invention will be described below with reference to the block diagram of FIG. 5 and the timing chart of FIG.
[0109]
FIG. 5 is a control block diagram specifically showing the line memory read / write control unit 2 and the invalid pixel cutting unit 4 shown in FIG. Here, the invalid pixel cutting unit 4 shown in FIG. 5 is similar to the image processing apparatus shown in FIG. 11 in that the effective pixel start position storage unit 141, the effective pixel end position storage unit 142, the comparator C, the comparator D, A NOR gate 143 and a selector 145 are provided, and each operation is the same as that of the image processing apparatus shown in FIG.
[0110]
The line memory read / write control unit 2 includes a reset circuit 121, a memory write start storage unit (write start information storage unit) 122, a memory read start storage unit (read visible information storage unit) 123, a line memory address control unit ( Address corrector means) 124, subtractor (subtractor means) A, subtractor (subtractor means) B, comparator (write control signal generating means) A, and comparator (read control signal generating means) B. ing.
[0111]
First, image data writing control in the line memory 1 will be described.
[0112]
The memory write start storage unit 122 has a horizontal synchronization signal h. The number of clocks at the write start position of the effective pixel counted from sync is stored and output to the reset circuit 121 as necessary.
[0113]
The reset circuit 121 receives a horizontal synchronization signal h input to the counter 3. The same signal as sync is input, and the horizontal sync signal h The reset signal RST1 is output to the subsequent line memory address control unit 124 until the number of clocks stored in the memory write start storage unit 122 is reached after the sync is input.
[0114]
In the timing chart of FIG. 6, the reset signal RST1 is at a low level for 8 clocks so that the line memory address control unit 124 is in a reset state.
[0115]
Then, at the ninth clock, the reset signal RST1 becomes high level and the reset of the line memory address control unit 124 is released. At this timing, the line memory address control unit 124 starts calculating an address to be written in the line memory 1. Here, since the length of the reset signal can be adjusted by changing the number of clocks stored in the memory write start storage unit 122, the address calculation start position in the line memory address control unit 124 is set. It can be increased or decreased.
[0116]
In the line memory address control unit 124, the address signal WR obtained from the address calculation result. addr is output to the comparator A at the subsequent stage.
[0117]
Further, the memory write start storage unit 122 has a write start position WR. strt is output to the subtracter A.
[0118]
The subtracter A has an invalid pixel counter value CNT from the counter 3 that counts invalid pixels used in the invalid pixel cutting unit 4. C is input, and the input start position WR strt is reduced. That is, as described above, the horizontal synchronization signal h stored in the memory write start storage unit 122. Since the write start clock number of the line memory 1 is stored from sync, the write start position WR strt is the number of clocks. Therefore, what is subtracted by the subtracter A is the number of clocks.
[0119]
The subtracter A can substitute the function of the counter circuit that has been necessary for conventional control. That is, the function of starting the count-up in the line memory address control unit 124 is performed by the subtracter A by using the invalid pixel counter value CNT from the counter 3. Write start position WR based on C It can be substituted by reducing the number of clocks of strt.
[0120]
The subtracter A is a subtraction value SUB1 obtained by subtracting the number of clocks. It is output to the comparator A as out.
[0121]
The comparator A receives the address signal WR from the line memory address control unit 124. addr and the subtraction value SUB1 from the subtracter A Compared with out, the write signal / WE is output to the line memory 1 if they are equal.
[0122]
In the comparator A, the address signal WR addr and subtraction value SUB1 If only the lower bits are compared with out, the circuit scale can be reduced. For example, in the case of 50% reduction, pixel writing is performed at addresses 1, 3, 5, 7, 9, 11,. Here, if the comparison is limited to the lower 3 bits, the subtraction value SUB1 The lower bits of out, that is, the lower bits of the counter, are repeated operations of 1, 3, 5, 7, 1, 3, 5, 7,. Therefore, the comparator A may be composed of a total of four comparators. That is, the comparator A has one internal comparator that detects count values 1, 3, 5, and 7 (four in total), and one logic gate circuit that takes the logical sum of the outputs of the internal comparators. Can be configured.
[0123]
Although the image data writing control in the line memory 1 has been described above, the image data reading control in the line memory 1 can be described in the same manner.
[0124]
Next, image data read control in the line memory 1 will be described.
[0125]
The memory read start storage unit 123 has a horizontal synchronization signal h. The number of clocks at the reading start position of effective pixels counted from sync is stored, and is output to the reset circuit 121 as necessary.
[0126]
The reset circuit 121 receives a horizontal synchronization signal h input to the counter 3. The same signal as sync is input, and the horizontal sync signal h The reset signal RST2 is output to the subsequent line memory address control unit 124 until the number of clocks stored in the memory read start storage unit 123 is reached after the sync is input.
[0127]
In the timing chart of FIG. 6, the reset signal RST2 is at a low level for 3 clocks so that the line memory address control unit 124 is reset.
[0128]
Then, at the fourth clock, the reset signal RST2 becomes high level, and the reset of the line memory address control unit 124 is released. At this timing, the line memory address control unit 124 starts calculating an address to be written in the line memory 1. Here, since the length of the reset signal can be adjusted by changing the number of clocks stored in the memory read start storage unit 123, the address calculation start position in the line memory address control unit 124 is set. It can be increased or decreased.
[0129]
In the line memory address control unit 124, the address signal RD obtained from the calculation result of the address. addr is output to the comparator B at the subsequent stage.
[0130]
In addition, the memory read start storage unit 123 has a read start position RD. strt is output to the subtractor B.
[0131]
The subtractor B receives an invalid pixel counter value CNT from the counter 3 that counts invalid pixels used in the invalid pixel cutting unit 4. C is input, and the input read start position RD strt is reduced. That is, as described above, the horizontal synchronization signal h stored in the memory read start storage unit 123. Since the number of clocks from sync to the start of reading of the line memory 1 is stored, the read start position RD strt is the number of clocks. Therefore, it is the number of clocks that is reduced in the subtracter B.
[0132]
The subtractor B can substitute the function of the counter circuit that has been necessary for conventional control. That is, the function of starting the count-up in the line memory address control unit 124 is performed by the subtracter B by using the invalid pixel counter value CNT from the counter 3. Read start position RD based on C It can be substituted by reducing the number of clocks of strt.
[0133]
The subtractor B subtracts the number of clocks, resulting in a subtraction value SUB2. It is output to the comparator B as out.
[0134]
The comparator B receives the address signal RD from the line memory address control unit 124. addr and the subtraction value SUB2 from the subtractor B Compared with out, if they are equal, the read signal / RE is output to the line memory 1.
[0135]
When the processing for the image data is a reduction processing, the read signal / RE is not thinned out. Further, when the process for the image data is an enlargement process, the write signal / WE is not thinned out.
[0136]
As described above, image data is written to the line memory 1 based on the write signal / WE that is a control signal generated by the line memory read / write control unit 2, and based on the read signal / RE that is a control signal. The image data written in the line memory 1 is read out.
[0137]
The read image data is output image data OUT. data is input to the selector 145 in the invalid pixel cutting unit 4 and, based on the image valid area signal SEL from the NOR gate 143, if the input image data is an invalid pixel area, the image mask data MSK data is the print data V If the input image data is not an invalid pixel area, the input image data is output as print data V Output as data.
[0138]
According to the image processing apparatus having the above configuration, it is conventionally necessary to separately generate a write signal / WE and a read signal / RE, which are control signals for controlling writing / reading of an image to / from the line memory 1. This counter is realized by the subtracters A and B.
[0139]
As a result, since a subtracter having a smaller scale than that of the circuit constituting the counter is used, the circuit scale of the image processing apparatus having the above configuration can be reduced.
[0140]
The second image processing apparatus of the present invention will be described below with reference to the block diagram shown in FIG. 7 and the timing chart shown in FIG.
[0141]
As shown in FIG. 7, the second image processing apparatus includes a line memory read / write control unit 12 instead of the line memory read / write control unit 2 of the first image processing apparatus shown in FIG. . The line memory 1, the counter 3, and the invalid pixel cutout unit 4 are the same as those in the first image processing apparatus, and thus detailed description thereof is omitted. Further, members having the same functions as those of the first image processing apparatus are denoted by the same reference numerals, and description thereof is omitted. Note that the comparator E and the comparator F included in the invalid pixel cutting unit 4 of the second image processing apparatus according to the present embodiment are the comparisons included in the invalid pixel cutting unit 4 of the first image processing apparatus described above. Corresponding to the comparator C and the comparator D.
[0142]
The line memory read / write control unit 12 includes a memory write start storage unit 122, a memory write interval storage unit (write interval storage unit) 221, a memory read start storage unit 123, and a memory read interval storage unit (read interval storage unit). 222, comparators (first to fourth control signal generating means) A to D, a gate A, and a gate B.
[0143]
First, image data writing control in the line memory 1 will be described. In this control, the counter 3, the memory write start storage unit 122, the memory write interval storage unit 221, the comparator A, the comparator B, and the gate A are used.
[0144]
That is, the comparator A outputs the invalid pixel counter value CNT output from the counter 3. C and the write start position WR from the memory write start storage unit 122 Compare with strt. Here, the horizontal write signal h is stored in the memory write start storage unit 122. The number of clocks from sync is stored.
[0145]
In the comparator A, if the comparison results are equal, the write start position signal WR that is a passing signal is sent to the gate A in the subsequent stage. The area is output as 0, and the comparison result DSP from the comparator B wr is output as the write signal / WE of the line memory 1. On the other hand, if the comparison results are not equal, the comparator A sends a write start position signal WR as a passing signal to the gate A in the subsequent stage. The area is output as 1, and this 1 is output as the write signal / WE of the line memory 1.
[0146]
For example, if 3 is stored in the memory write start storage unit 122, the comparator A outputs 0 at the third clock, and the output of the comparator B passes through the gate A and is output to the line memory 1. .
[0147]
The gate A is not a logic gate such as an AND gate or an OR gate, but is a gate circuit having an input A and a control terminal B and outputting the input A when 0 is entered in the control terminal B. That is, either “0” or “1” is output from the gate A.
[0148]
The comparator B receives the invalid pixel counter value CNT from the counter 3. C and the set value WR from the memory write interval storage unit 221 ctcle is entered. The memory writing interval storage unit 221 stores the writing interval of image data to the line memory 1. Here, the horizontal synchronization signal h The number of clocks based on sync is stored.
[0149]
Therefore, the comparator B has the set value WR from the memory write interval storage unit 221. ctcle and invalid pixel counter value CNT from counter 3 If the lower bits of C and the same value are compared, intermittent comparison result DSP Generate wr.
[0150]
For example, the number stored in the memory write interval storage unit 221 is 1, and the invalid pixel counter value CNT Consider a case where only one bit is extracted as the lower bits of C. In this case, the comparator B compares the register value 1 with the least significant bit of the counter, and if the least significant bit of the counter is 1, the comparison result DSP Output wr as 0.
[0151]
In other words, the waveform is such that 0 is output once for every two count-ups, so that the control is performed at the time of 50% reduction. Note that the reduction rate increases as the number of bits of the counter increases with respect to the number stored in the memory write interval storage unit 221. For example, if the number of storage units is 4, the reduction rate is 25% or less, and if the number of storage units is 8, the reduction rate is 12.5% or less.
[0152]
However, if it remains as it is, it is possible to control only one factorial of 2. However, the reduction ratio can be made variable by selecting a plurality of lower bits of the counter and taking the logical sum and logical product.
[0153]
Further, by adding control to change the combination of the counter selection bit, logical sum, and logical product on the operation panel, it is possible to provide an image processing apparatus that can freely set a variable magnification instead of a fixed magnification.
[0154]
The line memory 1 writes image data when the write signal / WE output from the gate A is 0, and does not write image data when the write signal / WE is 1. That is, the line memory 1 is controlled to write image data by either “0” or “1” signal output from the gate A.
[0155]
Next, image data read control in the line memory 1 will be described. The image data reading control is almost the same as the image data writing control described above. That is, this control is performed using the memory read start storage unit 123, the memory read interval storage unit 222, the comparator C, the comparator D, and the gate B.
[0156]
That is, the comparator C outputs the invalid pixel counter value CNT output from the counter 3. C and the read start position RD from the memory read start storage unit 123 Compare with strt. Here, the horizontal readout signal h is stored in the memory read start storage unit 123. The number of clocks from sync is stored.
[0157]
  In the comparator C, if the comparison results are equal, the readout start position signal RD_area, which is a passing signal, is output as 0 to the gate B in the subsequent stage, and the comparatorDComparison results fromDSP _rdOf line memory 1Readsignal/REOutput as. On the other hand, if the comparison results are not equal, the comparator C outputs the read start position signal RD_area, which is a passing signal, to the gate B at the subsequent stage as 1, and outputs this 1 as the read signal / RE of the line memory 1.
[0158]
For example, if 3 is stored in the memory read start storage unit 123, the comparator C outputs 0 at the third clock, and the output of the comparator C passes through the gate B and is output to the line memory 1. .
[0159]
The gate B is not a logic gate such as an AND gate or an OR gate, but has an input A and a control terminal B. When the control terminal B is 0, the input A is output. This is a gate circuit. That is, either “0” or “1” is output from the gate B.
[0160]
The comparator D receives the invalid pixel counter value CNT from the counter 3. C and the set value RD from the memory read interval storage unit 222 cycle is entered. The memory read interval storage unit 222 stores the read interval of image data to the line memory 1. Here, the horizontal synchronization signal h The number of clocks based on sync is stored.
[0161]
Therefore, the comparator D has the set value RD from the memory read interval storage unit 222. cycle and invalid pixel counter value CNT from counter 3 If the lower bits of C and the same value are compared, intermittent comparison result DSP Generate rd.
[0162]
  The line memory 1 reads image data if the read signal / RE output from the gate B is 0, and does not read image data if the read signal / RE is 1. Yes. In other words, the line memory 1 receives the image data by the signal “0” or “1” output from the gate B.readingControl is being done
[0163]
Instead of using the comparator B and the comparator C of the line memory read / write control unit 12, a 0 signal may be generated at a constant cycle. As an example including this configuration, there is a third image processing apparatus shown in FIG. The third image processing apparatus will be described below with reference to the block diagram shown in FIG. 9 and the timing chart shown in FIG.
[0164]
The third image processing apparatus includes a line memory read / write control unit 22 as shown in FIG. 9 instead of the line memory read / write control unit 12 of the second image processing apparatus shown in FIG. Other configurations are the same as those of the second image processing apparatus.
[0165]
As shown in FIG. 9, the line memory read / write control unit 22 includes a periodic signal generation circuit 223 in place of the comparator B and the comparator C of the line memory read / write control unit 12 shown in FIG. Yes.
[0166]
The periodic signal generation circuit 223 is a circuit that generates a 0 signal at a constant period, and it can be considered to be configured by one flip-flop, for example. This flip-flop outputs a signal that becomes 0 level at a constant period when a clock is input. The output of this flip-flop is input to gate A or gate B.
[0167]
Here, in the case of controlling the writing of image data to the line memory 1, the gate A outputs a 0 signal whose signal level is “0” every other clock as shown in the timing chart of FIG. The signal is generated. By creating a small-scale counter using a plurality of such flip-flops and combining the logical sum and logical product of outputs, the scaling factor can be changed not only for writing to one pixel twice. When changing the magnification, it is necessary to store the bit output information of the counter in the periodic signal generation circuit 223 (selection setting information indicating which bit is output) in the memory write interval storage unit 221. Set value WR accordingly It outputs to the periodic signal generation circuit 223 as ctcle. Here, the size of the counter to be created does not need to be a size for counting one line, so the circuit scale does not become larger than that of the conventional control.
[0168]
Here, as shown in the timing chart of FIG. 10, the output signal DSP from the periodic signal generation circuit 223. wr is the same as the write signal / WE (timing chart of FIG. 8) which is the output of the gate A. That is, the output signal DSP from the periodic signal generation circuit 223 wr is an effective area of the image (write start position signal WR from the comparator A) by the gate A. The section is controlled so as to pass only in the area where area is 0 level, and is output to the line memory 1 as the write signal / WE.
[0169]
Next, in the case of the read control of the image data from the line memory 1, the comparator D first outputs the invalid pixel counter value CNT output from the counter 3 as in the case of the write control described above. C and read start position RD from memory read start storage unit 123 Compare with strt. Next, in the comparison by the comparator D, if a result that both values are equal is obtained, a read start position signal RD that is a passing signal is supplied to the gate B. Output area.
[0170]
The gate B has the above read start position signal RD. In addition to area, the output signal DSP from the periodic signal generation circuit 223 rd is entered. This output signal DSP rd is a signal having the same waveform as that of the read signal / RE. That is, the output signal DSP from the periodic signal generation circuit 223 rd is an effective image area (read start position signal RD from the comparator D) by the gate D. Only when the area is 0 level), the signal is controlled to pass through and is output to the line memory 1 as a read signal / RE.
[0171]
As described above, according to the image processing apparatus of the present invention, by using a common counter circuit for the line memory address counter and the pixel position counter, an increase in the circuit scale accompanying an increase in the number of line memories is suppressed. The circuit can be simplified and the control can be simplified.
[0172]
The image processing apparatus according to the present invention includes a line memory for storing image data for one line, a horizontal synchronization signal indicating the base point of the line image data, and a line memory address control means for controlling an address of the line memory. Write start storage means for storing the write start of the line memory, read start storage means for storing the read start of the line memory, and dust removal counting means used for masking unnecessary images in the line memory. In the image processing apparatus, as a control for writing image data in the line memory, a means for outputting a reset signal to the line memory address control means based on the horizontal synchronization signal and the value of the storage means, and the dust removal count value based on the dust removal count value. The difference between the write memory and the line memory address system Part image processing apparatus, characterized in that to allow the writing of the line memory address from the result of comparing the value to be output.
[0173]
According to the above configuration, conventionally, the write control is performed using the write-only counter of the line memory. However, instead of the dedicated counter, the counter value used for removing the line memory is referred to. Further, by using a subtracter having a small circuit scale, the circuit scale can be reduced and simplified.
[0174]
The image processing apparatus according to the present invention includes a line memory for storing image data for one line, a horizontal synchronization signal indicating the base point of the line image data, and a line memory address control means for controlling an address of the line memory. Write start storage means for storing the write start of the line memory, read start storage means for storing the read start of the line memory, and dust removal counting means used for masking unnecessary images in the line memory. In the image processing apparatus, as control for reading image data from the line memory, a means for outputting a reset signal to the line memory address control means based on the horizontal synchronization signal and the value of the storage means, and the dust removal count value based on the dust removal count value. The value obtained by taking the difference of the read memory and the line memory address The image processing apparatus characterized in that the control unit is permitted to read the line memory address from the result of comparing the value to be output.
[0175]
According to the above configuration, the read control is conventionally performed using the read-only counter of the line memory. However, instead of the dedicated counter, the counter value used for removing the line memory is referred to. Further, by using a subtracter having a small circuit scale, the circuit scale can be reduced and simplified.
[0176]
The image processing apparatus according to the present invention includes a line memory for storing image data for one line, a horizontal synchronization signal indicating the base point of the line image data, and a line memory address control means for controlling an address of the line memory. Write start storage means for storing the write start of the line memory, read start storage means for storing the read start of the line memory, write interval storage means for storing the write address of the line memory, and the line memory In the image processing apparatus having a read interval storage means for storing a read address and a dust removal count means used for masking unnecessary images in the line memory, the write address storage is used as a control for writing image data to the line memory. The result of comparing the counter and counter values Properly, and, if a line memory write start position after the image processing apparatus and permits the writing of the line memory address.
[0177]
According to the above configuration, conventionally, the write control is performed using the write-only counter of the line memory. However, instead of the dedicated counter, the counter value used for removing the line memory is referred to. In addition, by using a comparator having a small circuit scale, the circuit scale can be reduced and simplified.
[0178]
Further, the image processing apparatus of the present invention includes a line memory for storing image data for one line, a horizontal synchronization signal indicating the base point of the line image data, and a line memory address control means for controlling the address of the line memory. Write start storage means for storing the write start of the line memory, read start storage means for storing the read start of the line memory, write interval storage means for storing the write address of the line memory, and the line memory In the image processing apparatus having a read interval storage means for storing a read address and a dust removal count means used for masking unnecessary images in the line memory, the write address storage is used as a control for reading image data from the line memory. The result of comparing the counter and counter values Equal, and, if a line memory read starting position after the image processing apparatus and permits the reading of the line memory address.
[0179]
According to the above configuration, the read control is conventionally performed using the read-only counter of the line memory. However, instead of the dedicated counter, the counter value used for removing the line memory is referred to. In addition, by using a comparator having a small circuit scale, the circuit scale can be reduced and simplified.
[0180]
【The invention's effect】
  As described above, the image processing apparatus of the present invention includes a line memory that stores image data for one line, an image data writing / reading control unit that controls writing and reading of image data to and from the line memory, Based on the horizontal synchronization signal indicating the base point of the line image data, the invalid pixel counting means for counting invalid pixels that become invalid image areas in the image data for one line, and the invalid pixel counting means An invalid image as an invalid image area, and an invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory, and the image data writing / reading control means includes:Write start information storage means for storing, as write start information, the number of clocks from the horizontal synchronization signal to the start of image data writing to the line memory, and the number of clocks stored in the write start information storage means. Subtracting means for subtracting based on the value counted by the invalid pixel counting means, the output value of the subtracting meansBased onAboveWriting image data to the line memorySeeIt is the structure which produces | generates the control signal to control.
[0181]
Therefore, conventionally, the image data writing / reading control means generates a control signal for controlling the writing and reading of the image data to and from the line memory based on the count value by the invalid pixel counting means. In addition to the means, there is no need to provide the counting means (line memory address counter) which is necessary for generating the control signals for controlling the writing and reading of the image data to and from the line memory.
[0182]
As a result, the line memory address counter and the pixel position counter (invalid pixel counting means) can be shared, so that the increase in the circuit scale accompanying the increase in the number of line memories is suppressed, the circuit is simplified, and the control is simplified. There is an effect that it can be realized.
[0183]
Specifically, it is conceivable to use a subtracter having a circuit scale smaller than that of the counter circuit in order to count the address of the line memory. By using this subtractor, the circuit scale in the image processing apparatus can be further reduced and simplified.
[0184]
  Other image processing apparatuses of the present invention are as described above.A line memory for storing image data for one line; image data writing / reading control means for controlling writing and reading of image data to and from the line memory; and a horizontal synchronization signal indicating a base point of the line image data And invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data, and invalid pixels counted by the invalid pixel counting means as invalid image areas and stored in the line memory. An invalid image cutting means for cutting out the invalid image area from the image data,The image data writing / reading control means includes a writing start information storage means for storing the number of clocks from the horizontal synchronization signal to the start of writing of the image data to the line memory as writing start information; A reset circuit that generates a reset signal based on the number of clocks stored in the loading start information storage means, and a timing at which the reset signal generated by the reset circuit is input and the reset signal is released, Address control means for outputting an address control signal for controlling the write address of the image data to the line memory, and a value obtained by counting the number of clocks stored in the write start information storage means by the invalid pixel counting means Subtracting means subtracting based on the address control signal output from the address control means, and the subtractor And a write control signal generating means for generating a write control signal for controlling the writing of the image data to the line memory based on the comparison result. Yes.
[0185]
  Also,Still another image processing apparatus of the present invention includes a line memory for storing image data for one line, image data writing / reading control means for controlling writing and reading of image data to and from the line memory, and a line image. An invalid pixel counting unit that counts invalid pixels that are invalid image areas in one line of image data based on a horizontal synchronization signal indicating a data base point, and invalid pixels counted by the invalid pixel counting unit An invalid image cutting means for cutting the invalid image area from the image data stored in the line memory as an invalid image area,The image data writing / reading control means stores a read start information storage means for storing the number of clocks from the horizontal synchronization signal to the start of reading of the image data from the line memory as read start information, the horizontal synchronization signal, and the read start. A reset circuit that generates a reset signal based on the number of clocks stored in the information storage means, and the reset signal generated by the reset circuit is input and at the timing when the reset signal is released, the line Address control means for outputting an address control signal for controlling the read address of the image data from the memory, and the number of clocks stored in the read start information storage means is reduced based on the value counted by the invalid pixel counting means. A subtracting means; an address control signal output from the address control means; and It comprises a read control signal generating means for comparing the value subtracted by the arithmetic means and generating a read control signal for controlling the reading of the image data from the line memory based on the comparison result. ing.
[0186]
Therefore, for example, an 8-bit counter as a counter circuit requires 96 gates, whereas an 8-bit subtractor requires 40 gates. Therefore, the write control counter (write address counter) and the read control counter (read address counter) are changed to subtracters, respectively, so that (96-40) × 2 = 112 gates per line memory. Will be reduced.
[0187]
In addition, since a plurality of line memories are required, a writing and reading circuit is required for one line memory. Therefore, when the line memory has 50 lines, for example, 112 × 50 = 5600 gates. As a result, the circuit can be simplified and the cost can be reduced.
[0188]
  Still another image processing apparatus according to the present invention provides:A line memory for storing image data for one line; image data writing / reading control means for controlling writing and reading of image data to and from the line memory; and a horizontal synchronization signal indicating a base point of the line image data And invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data, and invalid pixels counted by the invalid pixel counting means as invalid image areas and stored in the line memory. An invalid image cutting means for cutting out the invalid image area from the image data,When image data writing control is performed, the image data writing / reading control means stores the number of clocks from the horizontal synchronization signal to the start of writing image data to the line memory as writing start information. Start information storage means, write interval storage means for storing the write interval of image data to the line memory, the number of clocks stored in the write start information storage means and the count from the invalid pixel count means A first control signal generating means for outputting a first control signal when the number of clocks and the count value are equal, and comparing the write interval and the count value from the invalid pixel count means And a second control signal generating means for outputting a second control signal for controlling the writing of image data to the line memory when the writing interval is equal to the count value. Based on the timing of the output of the first control signal from the first control signal generating means, a configuration for outputting a second control signal outputted from said second control signal generating means to the line memory.
[0189]
  In addition, as described above, still another image processing apparatus of the present invention can be used.A line memory for storing image data for one line; image data writing / reading control means for controlling writing and reading of image data to and from the line memory; and a horizontal synchronization signal indicating a base point of the line image data And invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data, and invalid pixels counted by the invalid pixel counting means as invalid image areas and stored in the line memory. An invalid image cutting means for cutting out the invalid image area from the image data,When image data reading control is performed, the image data writing / reading control means stores reading start information that stores the number of clocks from the horizontal synchronization signal to the start of reading image data from the line memory as reading start information. The storage means, the read interval storage means for storing the read interval of the image data to the line memory, the number of clocks stored in the read start information storage means and the count value from the invalid pixel count means are compared. The third control signal is output when the number of clocks and the count value are equalstartA third control signal generating means for comparing the readout interval with the count value from the invalid pixel counting means, and controlling the readout from the image data to the line memory when the readout interval is equal to the count value. And a fourth control signal generating means for outputting a fourth control signal to be output, and the fourth control signal generating means outputs the third control signal based on the output timing of the third control signal from the third control signal generating means. The fourth control signal is output to the line memory.
[0190]
Therefore, each of the first to fourth control signal generation means compares the input signals and outputs the control signal based on the comparison result, and there is no need to perform the reset operation by the reset signal. In other words, the above configuration does not require a reset circuit that generates a reset signal based on the horizontal synchronization signal, and thus it is possible to simplify the circuit as a total of the image processing apparatus and reduce the cost. .
[Brief description of the drawings]
FIG. 1 is a schematic block diagram of an image processing apparatus according to the present invention.
FIG. 2 is a schematic configuration diagram of a digital copying machine to which the image processing apparatus shown in FIG. 1 is applied.
FIG. 3 is a control block diagram of the digital copying machine shown in FIG. 2;
FIG. 4 is an explanatory diagram showing a relationship between a line memory and dust data (invalid pixel data).
5 is a control block diagram illustrating an example of a control unit that performs writing and reading control of the line memory illustrated in FIG. 1;
6 is a timing chart of various signals in the control block diagram shown in FIG. 5. FIG.
7 is a control block diagram illustrating another example of a control unit that performs writing and reading control of the line memory illustrated in FIG. 1; FIG.
8 is a timing chart of various signals in the control block diagram shown in FIG. 7. FIG.
FIG. 9 is a control block diagram illustrating still another example of a control unit that performs writing and reading control of the line memory illustrated in FIG. 1;
10 is a timing chart of various signals in the control block diagram shown in FIG.
FIG. 11 is a control block diagram of a control unit that performs writing and reading control of a conventional line memory.
12 is a timing chart of various signals in the control block diagram shown in FIG. 11. FIG.
[Explanation of symbols]
1 line memory
2-line memory read / write control unit (image data writing / reading control means)
3 Counter (Invalid pixel counting means)
4 Invalid pixel cutout part (Invalid image cutout means)
12 line memory read / write controller (image data writing / reading control means)
22 Line memory read / write controller (image data writing / reading control means)
121 Reset circuit
122 Memory write start storage unit (write start information storage means)
123 Memory read start storage unit (read start information storage means)
124 Line memory address control unit (address control means)
221 Memory writing interval storage unit (writing interval storage means)
222 Memory read interval storage unit (read interval storage means)
223 Periodic signal generation circuit
A Subtractor (subtraction means)
B Subtractor (subtraction means)
A comparator (write control signal generating means)
B comparator (reading control signal generating means)
A comparator (first control signal generating means)
B comparator (second control signal generating means)
C comparator (third control signal generating means)
D comparator (fourth control signal generating means)

Claims (12)

A line memory for storing image data for one line;
Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
An invalid image cutting means that cuts the invalid image area from the image data stored in the line memory with the invalid pixel counted by the invalid pixel counting means as an invalid image area;
The image data writing / reading control means generates a control signal for controlling writing and reading of the image data to and from the line memory based on the count value by the invalid pixel counting means,
The image data writing / reading control means includes:
Write start information storage means for storing, as write start information, the number of clocks from the horizontal synchronization signal to the start of image data writing to the line memory;
Subtracting means for subtracting the number of clocks stored in the writing start information storage means based on the value counted by the invalid pixel counting means,
An image processing apparatus for generating a control signal for controlling writing among control signals for controlling writing and reading of image data to and from the line memory based on an output value of the subtracting means. A line memory for storing image data for one line;
Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
An invalid image cutting means that cuts the invalid image area from the image data stored in the line memory with the invalid pixel counted by the invalid pixel counting means as an invalid image area;
The image data writing / reading control means generates a control signal for controlling writing and reading of the image data to and from the line memory based on the count value by the invalid pixel counting means,
The image data writing / reading control means includes:
Write start information storage means for storing, as write start information, the number of clocks from the horizontal synchronization signal to the start of image data writing to the line memory;
A reset circuit for generating a reset signal based on the horizontal synchronization signal and the number of clocks stored in the write start information storage means;
An address control means for outputting an address control signal for controlling a write address of the image data to the line memory at a timing when the reset signal generated by the reset circuit is input and the reset signal is released;
Subtracting means for subtracting the number of clocks stored in the writing start information storage means based on the value counted by the invalid pixel counting means;
A control signal for comparing the address control signal output from the address control means with the value subtracted by the subtractor means, and controlling writing and reading of image data to the line memory based on the comparison result An image processing apparatus comprising: a writing control signal generating unit that generates a writing control signal as a control signal for controlling writing. A line memory for storing image data for one line;
Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
An invalid image cutting means that cuts the invalid image area from the image data stored in the line memory with the invalid pixel counted by the invalid pixel counting means as an invalid image area;
The image data writing / reading control means generates a control signal for controlling writing and reading of the image data to and from the line memory based on the count value by the invalid pixel counting means,
The image data writing / reading control means includes:
Read start information storage means for storing, as read start information, the number of clocks from the horizontal synchronization signal to the start of reading image data from the line memory;
A reset circuit for generating a reset signal based on the horizontal synchronization signal and the number of clocks stored in the readout start information storage means;
Address control means for outputting an address control signal for controlling the read address of the image data from the line memory at the timing when the reset signal generated by the reset circuit is input and the reset signal is released;
Subtracting means for subtracting the number of clocks stored in the readout start information storage means based on the value counted by the invalid pixel counting means;
A control signal for comparing the address control signal output from the address control means with the value subtracted by the subtractor means, and controlling writing and reading of image data from the line memory based on the comparison result An image processing apparatus comprising: a read control signal generating means for generating a read control signal as a control signal for controlling reading of the image processing apparatus. A line memory for storing image data for one line;
Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
An invalid image cutting means that cuts the invalid image area from the image data stored in the line memory with the invalid pixel counted by the invalid pixel counting means as an invalid image area;
The image data writing / reading control means generates a control signal for controlling writing and reading of the image data to and from the line memory based on the count value by the invalid pixel counting means,
The image data writing / reading control means includes:
Write start information storage means for storing, as write start information, the number of clocks from the horizontal synchronization signal to the start of image data writing to the line memory;
Writing interval storage means for storing the writing interval of the image data to the line memory;
The number of clocks stored in the write start information storage means is compared with the count value from the invalid pixel count means, and when the number of clocks is equal to the count value, output of the first control signal is started. 1 control signal generating means;
Among the control signals for comparing the writing interval and the count value from the invalid pixel counting means and controlling writing and reading of image data to the line memory when the writing interval and the count value are equal Second control signal generating means for outputting a second control signal as a control signal for controlling writing of
An image processing apparatus for outputting a second control signal output from the second control signal generating means to a line memory based on the output timing of the first control signal from the first control signal generating means. . A line memory for storing image data for one line;
Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
An invalid image cutting means that cuts the invalid image area from the image data stored in the line memory with the invalid pixel counted by the invalid pixel counting means as an invalid image area;
The image data writing / reading control means generates a control signal for controlling writing and reading of the image data to and from the line memory based on the count value by the invalid pixel counting means,
The image data writing / reading control means includes:
Read start information storage means for storing, as read start information, the number of clocks from the horizontal synchronization signal to the start of reading image data from the line memory;
Reading interval storage means for storing the reading interval of the image data to the line memory;
A clock number stored in the readout start information storage means is compared with a count value from the invalid pixel count means, and a third control signal starts to be output when the clock number is equal to the count value. Control signal generating means;
The reading interval is compared with the count value from the invalid pixel counting means, and when the reading interval is equal to the count value, reading out of control signals for controlling writing and reading of image data to the line memory is performed. A fourth control signal generating means for outputting a fourth control signal as a control signal to be controlled ,
An image processing apparatus for outputting a fourth control signal output from the fourth control signal generating means to a line memory based on the output timing of the third control signal from the third control signal generating means. . A line memory for storing image data for one line;
Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
An invalid image cutting means that cuts the invalid image area from the image data stored in the line memory with the invalid pixel counted by the invalid pixel counting means as an invalid image area;
The image data writing / reading control means generates a control signal for controlling writing and reading of the image data to and from the line memory based on the count value by the invalid pixel counting means,
The image data writing / reading control means includes:
Read start information storage means for storing, as read start information, the number of clocks from the horizontal synchronization signal to the start of reading image data to the line memory;
Subtracting means for subtracting the number of clocks stored in the readout start information storage means based on the value counted by the invalid pixel counting means,
An image processing apparatus for generating a control signal for controlling reading out of control signals for controlling writing and reading of image data to and from the line memory based on an output value of the subtracting means. A line memory for storing image data for one line;
Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
An invalid image cutting means that cuts the invalid image area from the image data stored in the line memory with the invalid pixel counted by the invalid pixel counting means as an invalid image area;
The image data writing / reading control means generates a control signal for controlling writing and reading of the image data to and from the line memory based on the count value by the invalid pixel counting means,
The image data writing / reading control means includes:
Write start information storage means for storing, as write start information, the number of clocks from the horizontal synchronization signal to the start of image data writing to the line memory;
The number of clocks stored in the write start information storage means is compared with the count value from the invalid pixel count means, and when the number of clocks is equal to the count value, output of the first control signal is started. 1 control signal generating means,
Image processing apparatus and generates a control signal for controlling the writing of the control signal for controlling the writing and reading of image data to said first control signal said line memory based on. A line memory for storing image data for one line;
Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
An invalid image cutting means that cuts the invalid image area from the image data stored in the line memory with the invalid pixel counted by the invalid pixel counting means as an invalid image area;
The image data writing / reading control means generates a control signal for controlling writing and reading of the image data to and from the line memory based on the count value by the invalid pixel counting means,
The image data writing / reading control means includes:
Read start information storage means for storing, as read start information, the number of clocks from the horizontal synchronization signal to the start of reading image data from the line memory;
A clock number stored in the readout start information storage means is compared with a count value from the invalid pixel counting means, and a third control signal starts to be output when the clock number is equal to the count value. Control signal generating means,
An image processing apparatus for generating a control signal for controlling reading out of control signals for controlling writing and reading of image data to and from the line memory based on the third control signal. A line memory for storing image data for one line;
  Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
  Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
  An invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory as an invalid image area counted by the invalid pixel counting means,
  The image data writing / reading control means includes:
Number of clocks from the horizontal synchronization signal to the start of image data writing to the line memory Write start information storage means for storing as write start information;
Subtracting means for subtracting the number of clocks stored in the writing start information storage means based on the value counted by the invalid pixel counting means,
  Based on the output value of the subtracting means, generating a control signal for controlling the writing of the image data to the line memory,
  Read start information storage means for storing, as read start information, the number of clocks from the horizontal synchronization signal to the start of reading image data to the line memory;
  Subtracting means for subtracting the number of clocks stored in the readout start information storage means based on the value counted by the invalid pixel counting means,
An image processing apparatus for generating a control signal for controlling reading of image data to the line memory based on an output value of the subtracting means.   A line memory for storing image data for one line;
  Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
  Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
  An invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory as an invalid image area counted by the invalid pixel counting means,
  The image data writing / reading control means includes:
  Write start information storage means for storing, as write start information, the number of clocks from the horizontal synchronization signal to the start of image data writing to the line memory;
  A reset circuit that generates a reset signal based on the horizontal synchronization signal and the number of clocks stored in the write start information storage means;
  Address control means for outputting an address control signal for controlling a write address of image data to the line memory at a timing when the reset signal generated by the reset circuit is input and the reset signal is released;
  Subtracting means for subtracting the number of clocks stored in the writing start information storage means based on the value counted by the invalid pixel counting means;
  A write control signal for comparing the address control signal output from the address control means with the value subtracted by the subtractor means and controlling the writing of image data to the line memory based on the comparison result And a write control signal generating means for generating
  Read start information storage means for storing, as read start information, the number of clocks from the horizontal synchronization signal to the start of reading image data from the line memory;
  A reset circuit for generating a reset signal based on the horizontal synchronization signal and the number of clocks stored in the readout start information storage means;
  An address control means for outputting an address control signal for controlling a read address of the image data from the line memory at a timing when the reset signal generated by the reset circuit is input and the reset signal is released;
  Subtracting means for subtracting the number of clocks stored in the readout start information storage means based on the value counted by the invalid pixel counting means;
  The address control signal output from the address control means is compared with the value subtracted by the subtractor means, and based on the comparison result, a read control signal for controlling the reading of the image data from the line memory is provided. An image processing apparatus comprising: a read control signal generating means for generating.   A line memory for storing image data for one line;
  Image data writing for controlling writing and reading of image data to the line memory / Reading control means;
  Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
  An invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory as an invalid image area counted by the invalid pixel counting means,
  The image data writing / reading control means includes:
  Write start information storage means for storing, as write start information, the number of clocks from the horizontal synchronization signal to the start of image data writing to the line memory;
  Write interval storage means for storing an interval of writing image data to the line memory;
  The number of clocks stored in the write start information storage means is compared with the count value from the invalid pixel count means, and when the number of clocks is equal to the count value, output of the first control signal is started. 1 control signal generating means;
  A comparison is made between the writing interval and the count value from the invalid pixel counting means, and when the writing interval and the count value are equal, a second control signal for controlling writing of image data to the line memory is provided. Second control signal generating means for outputting,
  Based on the output timing of the first control signal from the first control signal generating means, the second control signal output from the second control signal generating means is output to the line memory,
  Read start information storage means for storing, as read start information, the number of clocks from the horizontal synchronization signal to the start of reading image data from the line memory;
  Reading interval storage means for storing the reading interval of image data to the line memory;
  A clock number stored in the readout start information storage means is compared with a count value from the invalid pixel count means, and a third control signal starts to be output when the clock number is equal to the count value. Control signal generating means;
  A comparison is made between the readout interval and the count value from the invalid pixel counting means, and when the readout interval is equal to the count value, a fourth control signal is output to control readout from the image data to the line memory. 4 control signal generating means,
  An image processing apparatus for outputting a fourth control signal output from the fourth control signal generating means to a line memory based on the output timing of the third control signal from the third control signal generating means. . A line memory for storing image data for one line;
  Image data writing / reading control means for controlling writing and reading of image data to and from the line memory;
  Invalid pixel counting means for counting invalid pixels that become invalid image areas in one line of image data based on a horizontal synchronization signal indicating a base point of line image data;
  An invalid image cutting means for cutting out the invalid image area from the image data stored in the line memory as an invalid image area counted by the invalid pixel counting means,
  The image data writing / reading control means includes:
  Write start information storage means for storing, as write start information, the number of clocks from the horizontal synchronization signal to the start of image data writing to the line memory;
  The number of clocks stored in the write start information storage means is compared with the count value from the invalid pixel count means, and when the number of clocks is equal to the count value, output of the first control signal is started. 1 control signal generating means,
  Generating a control signal for controlling writing of the image data to the line memory based on the first control signal;
  Read start information storage means for storing, as read start information, the number of clocks from the horizontal synchronization signal to the start of reading image data from the line memory;
  The number of clocks stored in the reading start information storage means and the invalid pixel counting means And a third control signal generating means for starting to output a third control signal when the number of clocks is equal to the count value.
  An image processing apparatus for generating a control signal for controlling reading of image data to the line memory based on the third control signal.

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