JP2000069257A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an image processor of high reliability at a low cost. SOLUTION: A storage part has an image input/output part which outputs the number of processing lines for writing an input image from a reading part into a semiconductor memory, a compression/expansion part which reads the input image stored in the semiconductor memory from the semiconductor memory and transfers it to a secondary storage device, an input/output image address counter 131 and a transferred image address counter 132, which output a memory address so that the memory address after the semiconductor memory becomes full is returned to an initial address of a first accessed party of a page, when the semiconductor memory has not a memory equivalent to image data of one page inputted from the reading part, and an access control circuit 136 for executing writing and reading with respect to the semiconductor memory, in parallel with time division, which are controlled so that reading processing of the image data stored in the semiconductor memory is permitted, only when the counted value by the compression/expansion part is smaller than the counted value by the image input/output part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to the use of a memory of an image processing apparatus such as a digital copier, a scanner, a printer, and a facsimile for digitally processing image information.

[0002]

2. Description of the Related Art In recent years, digitalization of copiers has been progressing, and processing and editing using an image memory have become active. Among them, there is a function called an electronic sort in which image data for a plurality of documents is stored in a memory so that a designated number of copies are collectively copied to eliminate the sorting operation. Because a large memory cost is required to store multiple image data using only a semiconductor memory, the configuration is a combination of a semiconductor memory and a storage memory, and the storage memory is cheaper than the semiconductor memory. Generally, a secondary storage device such as a hard disk is used.

The necessity of the aforementioned semiconductor memory is as follows.
The reason is that the buffer memory for absorbing the speed difference between the transfer speed of the next storage device and the input / output image transfer speed, and the realization of the image rotation function by the address operation at the time of reading the memory are mentioned. In a system that does not require image rotation, if the transfer speed of the secondary storage device is sufficiently higher than the input / output image transfer speed, the input / output images may be directly stored in the secondary storage device, and no semiconductor memory is required. . In the secondary storage device, data stored sequentially is read out as sequential data in the same arrangement. On the other hand, when data is read out randomly in a rotated arrangement, the access speed is extremely reduced, and the The required image output speed cannot be satisfied.

For the above reasons, digital copiers that implement electronic sorting often employ a configuration in which a semiconductor memory and a secondary storage device are used in combination. It is customary for the semiconductor memory to have a capacity corresponding to the maximum transfer paper size that can be output.

[0005]

However, there are few cases in which the image is rotated at the maximum transfer paper size that can be output, even if the memory capacity is as large as the maximum transfer paper size. Further, when the access speed of the secondary storage device is extremely close to the image transfer speed corresponding to the copy speed of the copying machine, the function of absorbing the speed difference is also achieved with a memory amount smaller than that, and it can be said that it is an extra semiconductor memory. Further, when only a semiconductor memory is used to cope with a special size such as a long one, an excessive increase in cost is caused.

The present invention has been made to solve these problems, and has as its object to provide a low-cost and highly reliable image processing apparatus.

[0007]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method of reading an original and converting the read image data into a line synchronization signal indicating a head of a line in a raster format and a pixel synchronization signal synchronized with pixels. A reading unit for sequentially outputting,
A storage unit that stores image data from the reading unit, reads out the stored image data, outputs a line synchronization signal different from the line synchronization signal in the reading unit, and includes a semiconductor memory and a secondary storage device; In an image processing apparatus having an image forming unit that forms a visible image based on image data from the image processing unit, and a reading unit, a storage unit, and a system control unit that controls the image forming unit, the storage unit stores an input image from the reading unit. Write processing line number counting means for counting the number of processing lines for writing to the semiconductor memory, and read processing for counting the number of processing lines for processing for reading an input image stored in the semiconductor memory from the semiconductor memory and transferring the read image to the secondary storage device When there is no line number counting means and semiconductor memory corresponding to one page of image data input from the reading unit, the semiconductor memory becomes full. Memory address generating means for outputting a memory address so as to return the read memory address to the initial address which is the first access destination of the page, and reading processing of image data stored in the semiconductor memory, and reading processing line number counting means And a memory access control unit that performs writing and reading of the semiconductor memory in parallel in a time-division manner, which is controlled so as to be permitted only when the count value is smaller than the count value by the write processing line number counting unit. There is a feature. Therefore, the image data read from the reading unit and written to the semiconductor memory is managed by counting and comparing the processing lines so that the image data read and transferred to the secondary storage device is the same without overtaking. In addition, since the memory addresses used are duplicated, an image processing apparatus which is low in cost and highly reliable can be provided even when the semiconductor memory has a memory amount of less than one page.

According to another aspect of the present invention, the storage unit includes a write processing line number counting unit that counts the number of processing lines for processing of transferring image data stored in the secondary storage device and writing the image data to the semiconductor memory. A read-out processing line number counting unit for counting the number of processing lines in a read-out process for reading out image data transferred from the apparatus and written in the semiconductor memory and sending the read out image data to the image forming unit; and an image for one page to be output to the image forming unit A memory address generating means for outputting a memory address so as to return a memory address after the semiconductor memory is full to an initial address which is a first access destination of a page when the semiconductor memory corresponding to the data is not provided; Write processing to the memory is permitted until the semiconductor memory becomes full, and after that, the write processing line number counting means Only when the numerical value is smaller than the count value by the read processing line number counting means, the writing and reading of the semiconductor memory are controlled so that the reading process from the semiconductor memory is started after the semiconductor memory is full. Memory access control means for performing reading in parallel in a time-division manner.
Therefore, the processing lines are counted and compared with the image data transferred to the secondary storage device and written to the semiconductor memory so that the image data read from the semiconductor memory and sent to the image forming unit is the same without overtaking. In addition, since the memory addresses used are duplicated, an image processing apparatus that is low in cost and highly reliable can be provided even when the semiconductor memory has a memory amount of less than one page. .

Further, the memory address at which the semiconductor memory becomes full is arbitrarily set in accordance with the amount of memory to be mounted, so that the maximum value of the memory address is given to the address counter to return to 0 if they are equal. In addition, it can flexibly cope with a change in the amount of mounted memory.

[0010] Further, image data compression means for compressing image data is provided, and the compressed data is stored in a secondary storage device, so that the data amount can be reduced and the access load on the hard disk can be reduced.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A storage section has an image input / output section for outputting the number of processing lines for a process of writing an input image from a reading section to a semiconductor memory, and a storage section for reading an input image stored in the semiconductor memory from the semiconductor memory. When the semiconductor memory is full when there is no compression / expansion unit that outputs the number of processing lines of the process to be transferred to the next storage device and the semiconductor memory corresponding to one page of image data input from the reading unit An input / output image address counter and a transfer image address counter that output a memory address so as to return the memory address of the page to the initial address that is the first access destination of the page; Of a semiconductor memory that is controlled so as to be permitted only when the count value of the image input / output unit is smaller than the count value of the image input / output unit. And a access control circuit write and read are performed in parallel by time division.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention. In FIG. 1, the image processing apparatus according to the present embodiment includes a reading unit 10, an image forming unit 20, a system control unit 40, an operation unit 50, a FAX unit 60, a selector unit 70, and a storage unit 80. . The reading unit 10 includes an exposure lamp 11 and an image sensor (hereinafter referred to as a CCD).
12), an image processing unit (hereinafter abbreviated as IPU) 13 and a scanner control unit 14. The image forming unit 20 includes a charging charger 21, a photosensitive member 2
2, writing unit 23, developing device 24, paper feed roller 25, paper feed tray 26, registration roller 27, transfer charger 28,
It includes a separation charger 29, a fixing device 30, a paper discharge roller 31, a paper discharge tray 32, a cleaning device 33, a static elimination charger 34, and a plotter control unit 35.

First, the reading process of the reading unit 10 and the image forming process of the image forming unit 20 will be briefly described. First, a document is scanned and exposed by a movable exposure lamp 11 along a document table, and the reflected light is subjected to photoelectric conversion by a CCD 12 to be an electric signal corresponding to the intensity of the light. The IPU 13 subjects the electric signal to processing such as shading correction and the like, performs A / D conversion, converts the electric signal into an 8-bit digital signal, performs image processing such as scaling processing and dither processing, and forms an image signal together with an image synchronization signal. Send to section 20. Here, FIG. 2 is a diagram of the document table viewed from above. The scanner control unit 14 detects various sensors, controls a drive motor and the like, and sets various parameters in the IPU 13 in order to execute the above process.

In the image forming section 20, a photoreceptor 22 which is uniformly charged by a charging charger 21 and is rotated at a constant speed is provided.
Is exposed by a laser beam modulated by image data from the writing unit 23. Then, an electrostatic latent image is formed on the photoreceptor 22, and is developed into a toner image by developing it with toner by the developing device 24. Then, the transfer paper, which has been fed in advance from the paper feed tray 26 by the paper feed roller 25 and waited at the registration roller 27, is transported in a timely manner with the photoconductor 22, and the toner on the photoconductor 22 is transferred by the transfer charger 28. Is electrostatically transferred to a transfer sheet, and the transfer sheet is separated from the photoconductor 22 by the separation charger 29. Then, the toner image on the transfer paper is fixed to the fixing device 3.
0, the sheet is heated and fixed.
2 is discharged. On the other hand, the cleaning device 34 presses and removes the toner image remaining on the photoconductor 22 after the electrostatic transfer, and the photoconductor 22 is discharged by the discharging charger 34. The plotter control unit 35 detects various sensors and controls a drive motor and the like in order to execute the above process.

Here, the state of the image synchronization signal output from the IPU 13 of the reading section 20 will be described with reference to FIG. The frame gate signal (/ FGATE) is a signal representing an image effective range for an image area in the sub-scanning direction, and image data is valid while this signal is at a low level (low active). This / FGATE is a line synchronization signal (/
LSYNC) is asserted or negated at the falling edge. / LSYNC is a pixel synchronization signal (PCL
At the rising edge of K), the signal is asserted only by a predetermined number of clocks. After the rising of this signal, the image data in the main scanning direction becomes valid after a predetermined clock. The transmitted image data is one for one period of PCLK,
It is divided into 400 DPI equivalent from the arrow part in FIG. The image data is sent out as raster format data starting from the arrow. The effective sub-scanning range of image data is usually determined by the size of the transfer paper.

The system control unit 40 detects the input state of the operator to the operation unit 50, and sets various parameters in the reading unit 10, the image forming unit 20, the FAX unit 60, and the storage unit 80, and instructs execution of a process. , Communication. The state of the entire system is displayed on the operation unit 50. An instruction to the system control unit 40 is made by a key input to the operation unit 50 by the operator.

The facsimile unit 60 transmits the transmitted image data to the G3 or G3 according to an instruction from the system control unit 40.
4. Performs binary compression based on the FAX data transfer rules
Transfer to a telephone line not shown. The data transferred from the telephone line to the FAX unit 60 is restored to binary image data, sent to the writing unit 23 of the image forming unit 20, and visualized.

In the selector section 70, the system control section 40
The selector changes the state of the selector in accordance with the instruction from the scanner 10 and the source of the image data for forming the image is read by the reading unit 10 and the facsimile unit 6.
0, any one of the storage units 80.

The storage unit 80 normally stores image data of a document input from the IPU 13 and is used for copy applications such as repeat copy and rotation copy. It is also used as a buffer memory for temporarily storing the binary image data from the FAX unit 60. These data storage instructions are given by the system control unit 40.

FIG. 4 is a block diagram showing the configuration of the storage section 80 of FIG. The storage unit 80 of the present embodiment includes an image input / output unit 110, a compression / expansion unit 120, a memory control unit 130, a hard disk (hereinafter abbreviated as HD) 140, and a semiconductor memory 150.

The image input / output unit 110 is composed of a CPU and logic, communicates with the memory control unit 130 to receive a command, sets an operation according to the command, and changes the state of the image input / output unit 110. Sent as status information to inform. When an image input command is received, the input image data is output to the memory control unit 130 as memory data in units of 8 pixels together with a memory access signal as needed in accordance with the input image synchronization signal. When an image output command is received, image data from the memory control unit 130 is output in synchronization with an output image synchronization signal.

The compression / expansion unit 120 is composed of a CPU and a logic, communicates with the memory control unit 130, receives a command, sets an operation according to the command, and notifies the state of the compression / expansion processing. Therefore, it is transmitted as status information. When receiving a compression command,
A memory access request signal is output to the memory control unit 130, and when the memory access permission signal is active, the image data is received, compressed, and stored in the hard disk 140 as compressed data. When a decompression command is received, the compressed data stored in the hard disk 140 is read, decompressed, and output to the memory control unit 130 using the same access method as used for compression.

Further, the memory control unit 130 is constituted by a CPU and logic, communicates with the system control unit 40 of FIG. 1, receives a command, sets an operation according to the command, and changes the state of the storage unit. Sent as status information to inform. The operation commands from the system control unit 40 in FIG. 1 include image input, image output, compression, decompression, and the like. It is transmitted to the unit 120.

FIG. 5 is a block diagram showing the configuration of the memory control unit 130 of FIG. In the figure, an input / output image address counter 131 is an address counter that counts up according to an input / output memory access signal, and outputs a 22-bit memory address indicating a storage location where input image data is stored. The address is initialized at the start of memory access and by an initialization signal from an address comparator 138 described later.

The transfer image address counter 132
Is an address counter that counts up in response to a memory access request signal, and outputs a 22-bit memory address indicating a storage location where transfer image data is stored. The address is initialized at the start of memory access and by an initialization signal from an address comparator 137 described later.

Further, the processing line number comparator 133 compares the number of input / output processing lines output by the image input / output unit with the number of transfer processing lines output by the compression / expansion unit when an image is input from the outside, and performs transfer processing. If the number of lines is small, the processing line number comparison signal of the comparison result output to the arbiter 135 described later is activated. When the input / output image is not in operation, active is output.

The address selector 134 is a selector selected by the arbiter 135, and selects either an input / output image or a transfer image address.

Further, the arbiter 135 outputs a memory access permission signal for accessing the compression / decompression unit. The memory access permission signal is output under the condition that the address comparison signal is active and the input / output memory access signal is inactive.

The access control circuit 136 divides the input physical address into a row address and a column address corresponding to a DRAM which is a semiconductor memory by a signal from the access control circuit, and outputs the divided address to an 11-bit address bus. Also, according to the access start signal from the arbiter 135, the DRAM control signals (RAS, CAS, W
E) is output.

The address comparators 137 and 138
Address values output by the two image address counters and C
The address is compared with the maximum address set by the PU, and an address initialization signal is output. At the time of image output, the transfer image address counter outputs an image output start signal serving as an output trigger and a transfer processing line number initialization signal to the image input / output unit in synchronization with the address initialization signal of the first page.

Next, the semiconductor memory of this embodiment is for storing image data, and is composed of a semiconductor storage element such as a DRAM, and the total amount of memory is 400 DPI, 2
It is 2 Mbytes for the A4 size of the value image data.
Reading and writing are controlled from the memory control unit.
Further, the secondary storage device of the present embodiment is a hard disk.

The whole operation of the storage unit of the present embodiment is as follows. In response to an instruction from the system control unit, the input image data is stored in the semiconductor memory, and the image data already input during the storage operation is stored. Then, the data is converted into compressed data and stored in the hard disk of the storage memory.

FIG. 6 is a diagram showing a state during image input.
The figure shows the image data amount when writing as input image data to the image memory (shaded lower right), the memory address to be accessed, and the image data amount when read and output as transferred image data (shaded upper right). The relationship between the memory addresses to be accessed is shown. Since the memory control unit compares the two processing line numbers and controls the memory access permission signal so as not to overtake the address, the image data is correctly transferred.

FIG. 7 is a diagram showing a state during image output. The figure shows the image data amount when writing as transfer image data in the semiconductor memory (shaded lower right), the memory address to be accessed, and the image data amount when read and output as output image data (shaded upper right). The relationship between the memory addresses to be accessed is shown. When outputting image data to the outside, the operation of writing image data from the secondary storage device to the semiconductor memory is started in advance, and when the transfer address reaches a predetermined address, the number of transfer processing lines is once returned to 0, and the image output is started. Since the processing is started, the memory control unit controls the memory access permission signal so as to prevent the address from being overtaken by comparing the two processing line numbers, so that the image data is correctly transferred.

As described above, the address output to the semiconductor memory overlaps with the number of processing lines, and the overtaking management of the address is performed, so that the memory amount of the semiconductor memory is less than one page. It is possible to provide a low-cost and highly reliable digital copying machine.

Further, as shown in FIG. 5, since the maximum address is compared with the output value of the address counter and returned to 0 when they are equal, it is possible to flexibly cope with a change in the amount of mounted memory. Further, as shown in FIG. 4, by providing an image compression section between the hard disk and the semiconductor memory, the data amount is reduced, and the access load of the hard disk is reduced.

The present invention is not limited to the above embodiment, and needless to say, various modifications and substitutions can be made within the scope of the claims.

[0038]

As described above, according to the present invention,
A reading unit that reads a document and sequentially outputs a line synchronization signal indicating a head of a line and a pixel synchronization signal synchronized with pixels in a raster format in the read image data, and stores the image data from the reading unit and stores the stored image data. Read data,
A storage unit that outputs a line synchronization signal different from the line synchronization signal in the reading unit, includes a semiconductor memory and a secondary storage device, an image forming unit that forms a visible image based on image data from the storage unit, and a reading unit An image processing apparatus having a storage unit and a system control unit for controlling an image forming unit, wherein the storage unit counts the number of processing lines of a process of writing an input image from the reading unit to the semiconductor memory. Reading line number counting means for counting the number of processing lines for processing of reading an input image stored in the semiconductor memory from the semiconductor memory and transferring the read image to the secondary storage device;
When the semiconductor memory corresponding to one page of image data input from the reading unit is not provided, the memory address after the semiconductor memory is full is returned to the initial address which is the first access destination of the page. Memory address generating means for outputting an address and reading of image data stored in the semiconductor memory are permitted only when the count value of the read processing line number counting means is smaller than the count value of the writing processing line number counting means. And a memory access control means for executing writing and reading of the semiconductor memory controlled in a time-division manner in parallel. Therefore, the image data read from the reading unit and written to the semiconductor memory is managed by counting and comparing the processing lines so that the image data read and transferred to the secondary storage device is the same without overtaking. In addition, since the memory addresses used are duplicated, an image processing apparatus which is low in cost and highly reliable can be provided even when the semiconductor memory has a memory amount of less than one page.

According to another aspect of the present invention, the storage unit includes a write processing line number counting unit for counting the number of processing lines for processing of transferring image data stored in the secondary storage device and writing the image data in the semiconductor memory. A read-out processing line number counting unit for counting the number of processing lines in a read-out process for reading out image data transferred from the apparatus and written in the semiconductor memory and sending the read out image data to the image forming unit; and an image for one page to be output to the image forming unit A memory address generating means for outputting a memory address so as to return a memory address after the semiconductor memory is full to an initial address which is a first access destination of a page when the semiconductor memory corresponding to the data is not provided; Write processing to the memory is permitted until the semiconductor memory becomes full, and after that, the write processing line number counting means Only when the numerical value is smaller than the count value by the read processing line number counting means, the writing and reading of the semiconductor memory are controlled so that the reading process from the semiconductor memory is started after the semiconductor memory is full. Memory access control means for performing reading in parallel in a time-division manner.
Therefore, the processing lines are counted and compared with the image data transferred to the secondary storage device and written to the semiconductor memory so that the image data read from the semiconductor memory and sent to the image forming unit is the same without overtaking. In addition, since the memory addresses used are duplicated, an image processing apparatus that is low in cost and highly reliable can be provided even when the semiconductor memory has a memory amount of less than one page. .

Further, the memory address at which the semiconductor memory becomes full is arbitrarily set in accordance with the amount of mounted memory, so that the maximum value of the memory address is given to the address counter portion and returned to 0 if they are equal. In addition, it can flexibly cope with a change in the amount of mounted memory.

Further, image data compression means for compressing image data is provided and stored in a secondary storage device in a compressed state, so that the data amount can be reduced and the access load on the hard disk can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram of the document table viewed from above.

FIG. 3 is a diagram illustrating a state of an image synchronization signal output from an IPU of a reading unit.

FIG. 4 is a block diagram illustrating a configuration of a storage unit in FIG. 1;

FIG. 5 is a block diagram illustrating a configuration of a memory control unit in FIG. 4;

FIG. 6 is a diagram showing a state during image input.

FIG. 7 is a diagram showing a state during image output.

[Explanation of symbols]

 131 Input / output image address counter 132 Transfer image address counter 133 Processing line number comparator 134 Address selector 135 Arbiter 136 Access control circuit 137, 138 Address comparator

Claims (6)

[Claims] A reading unit for reading a document and sequentially outputting a line synchronization signal indicating a head of a line in a raster format and a pixel synchronization signal synchronized with a pixel in the read image data;
A storage unit that stores image data from the reading unit, reads out the stored image data, outputs a line synchronization signal different from the line synchronization signal in the reading unit, and includes a semiconductor memory and a secondary storage device; An image forming unit that forms a visible image based on image data from the unit, and an image processing apparatus that includes the reading unit, the storage unit, and a system control unit that controls the image forming unit. Write processing line number counting means for counting the number of processing lines of a process of writing an input image from the unit to the semiconductor memory; and reading the input image stored in the semiconductor memory from the semiconductor memory and transferring it to the secondary storage device Reading line number counting means for counting the number of processing lines of the processing; and the one corresponding to one page of image data input from the reading unit. A memory address generating means for outputting a memory address so as to return a memory address after the semiconductor memory is full to an initial address which is a first access destination of a page when the semiconductor memory is not provided; The read and write operations of the semiconductor memory are controlled such that the read processing of the stored image data is permitted only when the count value of the read processing line number counting means is smaller than the count value of the write processing line number counting means. And a memory access control unit that executes in parallel in a time-division manner. 2. The image processing apparatus according to claim 1, wherein a memory address at which the semiconductor memory becomes full is arbitrarily set according to an amount of mounted memory. 3. The image processing apparatus according to claim 1, further comprising image data compression means for compressing the image data, and storing the compressed image data in the secondary storage device. A reading unit for reading a document and sequentially outputting a line synchronization signal indicating a head of a line in a raster format and a pixel synchronization signal synchronized with a pixel in the read image data;
A storage unit that stores image data from the reading unit, reads out the stored image data, outputs a line synchronization signal different from the line synchronization signal in the reading unit, and includes a semiconductor memory and a secondary storage device; An image forming unit that forms a visible image based on image data from the unit, and an image processing apparatus that includes the reading unit, the storage unit, and a system control unit that controls the image forming unit. Write processing line number counting means for counting the number of processing lines for transferring image data stored in the secondary storage device and writing the image data in the semiconductor memory; image data transferred from the secondary storage device and written in the semiconductor memory Read-out line number counting means for counting the number of processing lines of a read-out process for reading out and sending out to the image forming unit; When the semiconductor memory corresponding to one page of image data is not provided, the memory address is output so that the memory address after the semiconductor memory is full is returned to the initial address which is the first access destination of the page. A memory address generating unit that performs write processing to the semiconductor memory until the semiconductor memory is full, and after the semiconductor memory is full, the count value of the write processing line number counting unit is changed by the read processing line number counting unit. Only when the value is smaller than the count value is permitted, and the reading process from the semiconductor memory is controlled to be started after the semiconductor memory is full. An image processing apparatus comprising: 5. The image processing apparatus according to claim 4, wherein a memory address at which the semiconductor memory becomes full is arbitrarily set according to an amount of mounted memory. 6. The image processing apparatus according to claim 4, further comprising image data compression means for compressing the image data, and storing the compressed image data in the secondary storage device.