JP3932275B2 - Image input / output device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image reading means or a digital image input means, and a large capacity such as a semiconductor memory and a hard disk drive for storing image data obtained by converting the read image signal into a digital signal or image data input from the digital image input means. Management and control of data transfer start timing and resource occupation timing of semiconductor memory and mass storage device Image input / output device It is about.
[0002]
[Prior art]
In recent years, with the progress of digitization of copying machines, processing and editing using image memory has become popular. Among them, there is a function called electronic sorting, in which image data for a plurality of originals is stored in a memory, so that a designated number of copies are collectively output and the sorting work is eliminated. In order to store a plurality of image data, in order to store the same image data in the semiconductor memory, a memory corresponding to the amount of data corresponding to the number of stored images is required, and the memory cost becomes enormous. The method is commonly used.
[0003]
First, a semiconductor memory + storage memory is used, and a secondary storage device such as a hard disk that is cheaper than the semiconductor memory is used as the storage memory.
Second, a semiconductor memory is used as an accumulation memory, and image data is compressed using a compression process to reduce the amount of data per sheet, thereby reducing the total amount of memory.
Third, a plurality of image input / output means (image scanner, printer controller, file server, FAX controller, etc.) share the same image memory.
[0004]
In order to execute input / output of image data to / from the image memory, a memory control controller (hereinafter referred to as DMA controller) using a DMA (Direct Memory Access) data transfer method is often used. The DMA controller transfers data to a specific area of the image memory based on information indicating a data transfer method called a descriptor. It is also possible to perform data transfer by dividing a memory area in which one image is stored into a plurality of descriptors. For example, by using an image memory in the form of a ring buffer, the memory capacity can be smaller than the capacity of image data. In some cases, input / output of image data is executed.
[0005]
In the memory control using the DMA controller, the data transfer progress status (start and end) specified by each descriptor, the data transfer execution timing control (data transfer is interrupted or resumed in the middle of the image memory area, or Since the end interrupt notification of each descriptor is also possible, the degree of freedom in controlling the data transfer timing of the semiconductor memory connected to the DMA controller and the large-capacity secondary storage device is high, and the application range is wide.
[0006]
As described above, when a secondary storage device such as a hard disk, which is cheaper than a semiconductor memory, is used as the storage memory, a plurality of data transfers (data writing and reading operations) cannot normally be performed on a single storage device. By dividing the data transfer unit to the secondary storage device using the descriptor of the DMA controller and executing this in time division, a plurality of data transfer operations may be executed in parallel. It is common.
[0007]
However, when such a time-sharing process is used, the time required for data transfer is not shortened, so that the time required for inputting / outputting image data as in an image forming apparatus is minimized. In the case of influence, the time-sharing process may cause a decrease in productivity. Therefore, the image data is compressed, the data transfer amount is reduced, or a secondary storage device having a high data transfer speed is installed to shorten the time required for data transfer to the secondary storage device. (For example, see Patent Document 1). Conventionally, the memory control is occupied as a resource of the secondary storage device substantially in synchronism with the image data input / output operation using the image input / output means without actively performing time division transfer for the purpose of simplifying the memory control. Thus, a means for transferring data has been used.
[0008]
In the conventional secondary storage device, the image data transfer rate to the secondary storage device is lower than the image input / output means and the image data transfer rate to the semiconductor memory. Even if the data processing capacity of the secondary storage device is reduced by performing the above, there is no difference in the data processing speed between the image input / output means and the semiconductor memory, so the data transfer processing between the semiconductor memory and the secondary storage device ( The degree of improvement in productivity of the image forming apparatus by controlling the transfer timing independently (including data conversion processing such as data compression) is not so high.
[0009]
However, the transfer processing speed of the secondary storage device has been improved year by year as in the case of the hard disk, and the degree of improvement in productivity has been increased by optimal control. Models that can read and improve the processing capability of the image input / output means, and in order to achieve productivity, models with mechanical constraints that cannot be realized unless the document input processing of the image input device is operated at non-intervals. In addition to memory timing control after data transfer from the image input means, an advance prediction notification means for the image input means is provided to the image input means based on conditions such as the current state of memory control and characteristics of the storage device. The document input non-interval control enable / disable judgment is notified, and the image input device side switches the document transfer interval and non-interval control. Noh has become necessary.
[0010]
[Patent Document 1]
JP-A-6-103225
[0011]
[Problems to be solved by the invention]
Along with the advancement of technology in recent years, the data transfer rate of a large-capacity storage device such as a hard disk has been improved, and the data compression rate and processing speed of the data compression means have been significantly improved. In a storage device such as the present invention in which such a large-capacity storage device can be connected as a secondary storage device, the secondary storage device is compared with the data input and output speed of the connected image input / output means. It is conceivable that the data transfer speed for is high. For this reason, in a case where a configuration capable of simultaneously executing input / output of a plurality of image signals in parallel is performed, how efficiently image signal data input (save) and output (read) processes are performed with respect to the secondary storage device. However, this is an issue for improving the productivity of the image forming apparatus. In a situation where image input / output means connected to the image forming apparatus are extremely diverse, it is difficult to ensure productivity by making maximum use of the capacity of the storage device and data compression means with conventional memory control. Yes.
[0012]
In view of such a situation, the present invention applies a memory control method using DMA, and manages resource acquisition, release management, and data transfer operation for obtaining the maximum use efficiency according to the processing capacity of the storage device. A means for efficiently controlling the processing is used.
[0013]
In the present invention, the image input / output means connected to the image forming apparatus and the peripheral control apparatus and the image signal transfer speed between the image input / output means and the storage device determined by the configuration of the peripheral device and the productivity of the image forming apparatus are realized. To determine whether or not the control according to the processing time condition is possible and prevent the malfunction of the apparatus without changing the configuration of the apparatus Eyes It has been the target. For example, in FAX transmission processing, there is a rule for data transfer time in a data transfer protocol using a telephone line, so if the data transmission is not performed within a certain time, the telephone line is disconnected and the data transfer is abnormal. Become. Further, when the color image forming apparatus has a configuration in which a color image is obtained by outputting and superimposing a plurality of color image data at regular intervals, the image data stored in the secondary storage device is determined. If the image is not read and output within a predetermined time, a color image cannot be formed or productivity is significantly reduced.
[0014]
In particular, Means for specifying the time until completion of image signal input / output processing when an image signal input / output operation execution request is provided in advance, means for determining whether the requested operation can be executed, and other currently executed In order to improve the control of the requested operation and the image signal processing efficiency of the entire image forming apparatus by providing means for controlling the prohibition of the requested operation or postponing the start of execution according to the status of the image signal transfer process. It aims at providing the means of.
[0015]
Also ,Up Means for determining whether or not to execute the control as described above is provided, and automatically according to the configuration of the image input / output means and the storage device connected to the image forming apparatus and the function of the image forming apparatus It is an object of the present invention to provide means for realizing control of an image signal transfer operation.
[0016]
[Means for Solving the Problems]
In order to achieve such an object, an aspect of the present invention includes a storage unit that stores an image signal input from the image input unit, Storage means In the image input / output device for outputting the image signal stored in the image output means, Image input means − Storage means Between and Image output means − Storage means Data transfer capacity storage means for measuring and storing data transfer capacity between, Accepts multiple data transfer requests including the amount of data related to data transfer and the data transfer completion time of the data, and stores it as a queue Request execution management means, and when there is a data transfer request, Data volume and data transfer capacity Calculate the data transfer time based on Data transfer time When Expected completion time of the data transfer request previously stored by the request execution management means On the basis of the Data transfer request When the forecast is completed while And Expected completion time But Fits within the data transfer completion time Sometimes Holds data transfer requests and anticipates completion time But Does not fit in the data transfer completion time Sometimes Delete a data transfer request from the queue And a control means.
here, the above The storage means the above A primary storage unit for storing an image signal input from the image input means; this And a secondary storage unit that stores an image signal stored in the primary storage unit.
[0017]
Also, In the image input / output device, the request execution managing means stores at least a queue of data transfer requests on the input side and a queue of data transfer requests on the output side. It is a means.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0019]
An example in which the image data output apparatus of the present invention is used in a digital copying machine is shown in FIG. Based on this, the reading process of the reading unit and the image forming process of the image forming unit will be briefly described. The original is scanned and exposed by an exposure lamp movable along the original table, and the reflected light is subjected to photoelectric conversion by a CCD (image sensor) to obtain an electric signal corresponding to the intensity of the light. The IPU (image processing unit) performs processing such as shading correction on the electrical signal to A / D conversion to obtain an 8-bit digital signal, and further performs image processing such as scaling and dithering, along with the image synchronization signal. An image signal is sent to the image forming unit.
[0020]
FIG. 2 is a view of the document table viewed from above. In order to execute the above process, the scanner control unit detects various sensors, controls a drive motor, and the like, and sets various parameters in the IPU. The above is the reading process.
[0021]
In the image forming unit, a constant rotating photoconductor uniformly charged by the charging charger is exposed by a laser beam modulated by image data from the writing unit. An electrostatic latent image is formed on the photoconductor, and a developed toner image is developed by developing the toner with toner using a developing device. The transfer paper that has been fed from the paper feed tray in advance by the paper feed roller and waited by the registration roller is transported in time with the photoconductor, and the transfer charger electrostatically transfers the toner on the photoconductor to the transfer paper. Then, the transfer paper is separated from the photosensitive member by the separation charger. Thereafter, the toner image on the transfer paper is heated and fixed by a fixing device, and is discharged onto a discharge tray by a discharge roller. On the other hand, the toner image remaining on the photosensitive member after electrostatic transfer is pressed against and removed from the photosensitive member by the cleaning device, and the photosensitive member is discharged by the discharging charger. The plotter control unit performs detection of various sensors and control of the drive motor and the like in order to execute the above process. The above is the image forming process.
[0022]
Here, the state of the image synchronization signal output from the IPU of the reading unit will be described with reference to FIG. The frame gate signal (/ FGATE) represents a valid image range for the image area in the sub-scanning direction, and image data during which this signal is at a low level (low active) is valid. This / FGATE is asserted or negated at the falling edge of the line synchronization signal (/ LSYNC). / LSYNC is asserted for a predetermined number of clocks at the rising edge of the pixel synchronization signal (PCLK), and image data in the main scanning direction is validated after a predetermined clock after the rising of this signal. The sent image data is one for one cycle of PCLK, and is divided into 400 DPI equivalents from the arrow portion of FIG. The image data is sent out as raster format data starting from the arrow. Further, the sub-scanning effective range of image data is usually determined by the transfer paper size.
[0023]
The system control unit detects an input state to the operation unit by the operator, and performs setting of various parameters to the reading unit, the storage unit, the image forming unit, the FAX unit, a process execution instruction, and the like by communication. In addition, the state of the entire system is displayed on the operation unit. An instruction to the system control unit is made by key input to the operation unit of the operator.
[0024]
In response to an instruction from the control unit, the FAX unit performs binary compression on the transmitted image data based on the G3 and G4 FAX data transfer rules and transfers the image data to the telephone line. The data transferred from the telephone line to the FAX unit is restored to binary image data, which is sent to the writing unit of the image forming unit to be visualized.
[0025]
The selector unit changes the state of the selector according to an instruction from the system control unit, and selects the source of image data for image formation from one of the reading unit, the storage unit, and the FAX unit.
[0026]
The storage unit normally stores image data of a document input from the IPU, and is used for a copy application such as repeat copy or rotation copy. It is also used as a buffer memory for temporarily storing binary image data from the FAX section. These data storage instructions are given by the control unit.
[0027]
FIG. 4 is a configuration diagram of the storage unit. Hereinafter, the function will be described for each block.
[0028]
<Description of 4-1 (Image Input / Output DMAC)>
The image input / output DMAC 4-1 includes a CPU and logic, communicates with the memory control unit 4-3, receives a command, performs operation settings in accordance with the command, and states the image input / output DMAC 4-1 Is sent as status information. When an image input command is received, the input image data is packed as memory data in units of 8 pixels according to the input image synchronization signal, and is output to the memory control unit 4-3 as needed together with the memory access signal. When an image output command is received, the image data from the memory control unit 4-3 is output in synchronization with the output image synchronization signal.
[0029]
<Description of 4-2 (Image Memory)>
The image memory 4-2 stores image data, and is composed of a semiconductor storage element such as a DRAM. The total amount of memory is 400 DPI, 4 Mbytes of A3 size of binary image data, and memory 4M for storing electronic sorts. The total number of bytes is 8 MB. Reading and writing are controlled from the memory control unit 4-3.
[0030]
<Description of 4-3 (Memory Control Unit)>
The memory control unit 4-3 includes a CPU and logic, communicates with the system control unit, receives commands, performs operation settings according to the commands, and transmits status information to notify the state of the storage unit. To do.
The operation commands from the system control unit include image input, image output, compression, decompression, etc. The image input and image output commands are the image input / output DMAC 4-1, the compression related commands are the image transfer DMAC 4-4, The data is transmitted to the code transfer DMAC 4-5 and the compression / decompression unit 4-6.
[0031]
FIG. 5 shows the configuration of the address generation unit and the comparison unit of the memory control unit 4-3, and the function will be described for each block.
[0032]
<Description of 5-1 (Input / Output Image Address Counter)>
An address counter that counts up in response to an input / output memory access request signal outputs a 22-bit memory address indicating a storage location where input / output image data is stored. The address is initialized once at the start of memory access.
[0033]
<Explanation of 5-2 (Transfer Image Address Counter)>
An address counter that counts up in response to the transfer memory access permission signal outputs a 22-bit memory address indicating the storage location where the transfer image data is stored. The address is initialized once at the start of memory access.
[0034]
<Description of 5-3 (Line Setting Unit)>
When a semiconductor memory is used as a buffer at the time of image input, a value to be compared with the difference result between the input processing line and the transfer line output from the difference calculation unit 5-4 by the difference comparison unit 5-5 is set from the system control unit To do. An arbitrary value can be set.
[0035]
<Description of 5-4 (difference calculation unit)>
At the time of image input, the number of input / output processing lines output by the image input / output unit is subtracted from the number of transfer processing lines output by the compression / decompression unit, and the result is output to the difference comparison unit 5-5.
[0036]
<Description of 5-5 (difference comparison unit)>
At the time of image input, the number of difference lines output from the difference calculation unit 5-4 and the setting value output from the line setting unit 5-3 are compared, and if “difference line number = setting value” is satisfied, an error signal is output. If the number of differential lines becomes 0, the comparison request transfer request mask signal to be output to the arbiter 5-7 is made active. Otherwise, active is not output in the state where the input / output image is not in operation.
[0037]
<Description of 5-6 (Address Selector)>
The selector selected by the arbiter 5-7 selects either the input image or the transfer image address.
[0038]
<Description of 5-7 (Arbiter)>
A memory access permission signal for accessing the compression / decompression unit is output. A memory access permission signal is output under the condition that the address comparison signal is active and the input / output memory access signal is inactive.
[0039]
<Description of 5-8 (Request Mask)>
The transfer memory access request signal for accessing the compression / decompression unit is masked (to be disabled) by the comparison result from the processing line number comparator, and the transfer process is stopped.
[0040]
<Description of 5-9 (Access Control Circuit)>
The input physical address is divided into a row address and a column address corresponding to a DRAM which is a semiconductor memory by a signal from the access control circuit 5-9, and is output to an 11-bit address bus. Further, in accordance with an access start signal from the arbiter 5-7, a DRAM control signal (RAS, CAS, WE) is output.
[0041]
In response to an image input instruction from the system control unit, the memory control unit 4-3 is initialized and enters a standby state for image data, and image data is input to the storage unit when the scanner operates. The input image data is once written in the semiconductor memory. The number of processing lines of the written image data is counted by the image input / output DMAC 4-1, and is input to the memory control unit 4-3. The compression / decompression unit 4-6 receives the image transfer command and outputs a transfer memory access request signal. However, the request signal is masked by the request mask unit 5-8 of the memory control unit, and the actual memory access is performed. I have not been told. When one line of input data from the image input / output unit ends, the mask of the transfer memory access request signal is released, the semiconductor memory is read, and the transfer operation of the image data to the compression / decompression unit is started. Further, the difference calculation unit 5-4 calculates the difference between the two processing lines even during the operation, and when it becomes 0, the transfer memory access request signal is masked so that the address is not overtaken.
The above is the description of the configuration of the memory control unit 4-3.
[0042]
<Description of 4-4 (Image Transfer DMAC)>
The image transfer DMAC 4-4 is composed of a CPU and logic, communicates with the memory control unit 4-3, receives a command, performs operation settings according to the command, and transmits it as status information to inform the state. . When a compression command is received, a memory access request signal is output to the memory control unit 4-3, and when the memory access permission signal is active, image data is received and transferred to the compression / decompression unit 4-6. In addition, an address counter that counts up in response to a memory access request signal is built in, and a 22-bit memory address indicating a storage location where image data is stored is output.
[0043]
<Description of 4-5 (Code Transfer DMAC)>
The code transfer DMAC 4-5 is composed of a CPU and a logic, communicates with the memory control unit 4-3, receives a command, sets an operation according to the command, and transmits it as status information to inform the state. . When an expansion command is received, a memory access request signal is output to the memory control unit 4-3. When the memory access permission signal is active, image data is received and transferred to the compression / expansion unit 4-6. In addition, an address counter that counts up in response to a memory access request signal is built in, and a 22-bit memory address indicating a storage location where image data is stored is output. The descriptor access operation of the DMAC will be described later.
[0044]
<Description of 4-6 (Compression / Expansion Device)>
It is composed of a CPU and a logic, communicates with the memory control unit 4-3, receives a command, performs operation setting according to the command, and transmits it as status information to inform the state. Binary data is processed by the MH encoding method.
[0045]
<Description of 4-7 (HDD controller)>
It is composed of a CPU and a logic, communicates with the memory control unit 4-3, receives a command, performs operation setting according to the command, and transmits it as status information to inform the state. Read HD4-8 status and transfer data.
[0046]
<Description of 4-8 (HD)>
A secondary storage device, which is a hard disk.
The above is the description of the configuration of the storage unit.
[0047]
As an overall operation of the storage unit, image data is written in or read out from a predetermined image area of the image memory by the image transfer DMAC 4-4 according to an instruction from the system control unit when inputting an image and accumulating data. At this time, the image transfer DMAC 4-4 counts the number of image lines.
[0048]
FIG. 6 is a diagram for explaining the descriptor access operation and the data transfer operation of the video input DMAC. The image data in the figure is divided into four bands, and the image data of the number of lines set in each band is transferred.
[0049]
A procedure for adding the total number of transfer lines in one image will be described below. First, when the video input DMAC receives a transfer command, the DMA is activated, the descriptor 1 is read-accessed to the chain destination address (a) set in advance by the CPU in the internal descriptor storage register, and the contents of the descriptor 1 in the memory are read. Load the descriptor storage register. The loaded contents are composed of 4 words, the chain destination address indicating the storage address of the next descriptor, the data storage destination address indicating the head address of the data to be stored, and the data amount of the data to be transferred in the number of lines There is format information indicating whether or not a CPU interrupt is to be generated when the number of data transfer lines shown in FIG. In the least significant bit of the format information, a bit indicating whether or not to generate a CPU interrupt when the set line number transfer is completed is arranged. 0 generates a CPU interrupt, 1 masks the CPU interrupt.
[0050]
In the example of FIG. 6, the image is divided into four bands, and the least significant 1 bit of the format information of each descriptor is 0, 0, 0, 0 in order from 1 to 4. When the transfer of the image data of each band is completed, a CPU interrupt is generated, and transfer is possible while detecting the transfer end timing and the number of lines by adding the number of lines set in each descriptor.
[0051]
Similarly, when data is transferred from the image memory 4-2 to the HD 4-8 through the compression / decompression unit 4-6 (primary storage device → secondary storage device), the descriptor setting of the image transfer DMAC 4-4 is 1 band. Therefore, the number of descriptor lines is set as the number of image lines. At that time, the transfer destination of the code transfer DMAC 4-5 is set in the HDD controller 4-7. A storage address is set in the HDD controller 4-7, and image data can be transferred through a path of image memory → image transfer DMAC → compressor / decompressor → code transfer DMAC → HDD controller → HD. After the data transfer is completed, the HDD controller 4-7 notifies the used data amount when it is stored in the HD 4-8, and the HDD management that secures the address stored in the HD 4-8 and the used data amount in the primary storage device Store in the area. The memory control unit 4-3 masks the transfer memory access request so that the transfer of the image data to the compression / decompression unit 4-6 does not overtake the transfer from the image input DMAC 4-1. The data transfer to the copy is controlled so as not to overtake the image input data transfer).
[0052]
Conversely, when data is transferred from the HD 4-8 to the image memory 4-2 through the compression / decompression unit 4-6 (secondary storage device → primary storage device), the data is stored in the HDD management area secured in the primary storage device. The storage address and the amount of data used when accumulating in the HD 4-8 are acquired, the storage address is set in the HDD controller 4-7, the amount of data used is stored in the code transfer DMAC 4-5, and the image transfer DMAC 4-4. The number of lines after expansion is set, and image data can be transferred through a path of HD → HDD controller → code transfer DMAC → compressor / decompressor → image transfer DMAC → image memory.
[0053]
[Embodiment 1]
The first embodiment of the present invention will be described. First, a means for measuring the transfer rate capability of an input / output device will be described.
[0054]
This measurement operation is executed in advance before actually performing data input / output and transfer processing. The execution timing is determined when the input / output device is connected to the image processing apparatus for the first time, and may be automatically performed by the system or arbitrarily executed by an operator.
[0055]
When the connected device is an input device, the data transfer capability from the input device to the primary storage device is measured.
Let rx_data1 be the amount of measurement data. Reset timer at start of input.
The timer value at the time when the data storage completion interrupt of the primary storage device occurs is set as the transfer time rx_time1.
The transfer speed rx_speed1 per unit time is
rx_speed1 = rx_data1 / rx_time1
Given in. This transfer speed rx_speed1 is stored in the nonvolatile memory of the system after measurement so that it can be referred to whenever an input request is generated from this input device.
[0056]
When the connected device is an output device, the data transfer capability from the primary storage device to the output device is measured.
Let tx_data1 be the amount of measurement data. The timer is reset at the start of data transfer to the primary storage device.
The timer value at the time when the data transfer completion interrupt of the primary storage device occurs is set as the transfer time tx_time1.
The transfer rate tx_rate1 per unit time is
tx_rate1 = tx_data1 / tx_time1
Given in. This transfer speed tx_speed1 is stored in the nonvolatile memory of the system after measurement so that it can be referred to whenever an output request to the output device occurs.
[0057]
The data transfer from the primary storage device to the secondary storage device is considered to be constant regardless of the type of input / output device. Let rx_data2 be the amount of data for measurement.
The timer is reset when data transfer from the primary storage device is started.
The timer value at the time when the data transfer completion interrupt of the primary storage device occurs is set as the transfer time rx_time2.
The transfer speed rx_speed2 per unit time is
rx_speed2 = rx_data2 / rx_time2
Given in. This transfer speed rx_speed1 is stored in the nonvolatile memory of the system after measurement so that it can be referred to whenever a transfer request is issued from the primary storage device.
[0058]
Data transfer from the secondary storage device to the primary storage device is considered to be constant regardless of the type of input / output device. Let tx_data2 be the amount of measurement data.
The timer is reset at the start of data transfer to the primary storage device.
A timer value at the time when an interrupt of data transfer completion to the primary storage device occurs is set as a transfer time tx_time2.
Transfer rate tx_rate2 per unit time is
tx_rate2 = tx_data2 / tx_time2
Given in. This transfer speed tx_speed2 is stored in the nonvolatile memory of the system after measurement so that it can be referred to whenever a transfer request from the secondary storage device is generated.
[0059]
The expected transfer completion time depends on the data volume data1 and the transfer rate of each input / output.
When entering,
expect_time = data1 / rx_speed1 + data1 / rx_speed2 + wait_time
If output,
expect_time = data1 / tx_speed1 + data1 / tx_speed2 + wait_time
Can be calculated.
wait_time is a time required other than the data transfer for this I / O request, and changes depending on the operation state at that time.
wait_time = WAIT_DRAM + WAIT_HDD + α
WAIT_DRAM is the time until the DRAM is released and can be used for that request if the DRAM is occupied first by another request, and the expected completion time of the currently executing I / O transfer request, It can be obtained from other waiting transfer requests.
WAIT_HDD is the time until the HDD is released and can be used for that request if the HDD is occupied first by another request, and the expected completion time of the currently executing I / O transfer request, It can be obtained from other waiting transfer requests.
These can be acquired sequentially from the operating state of each device.
α uses the worst value as a fixed value for other overhead.
[0060]
When a data transfer is requested, a time complete_time for completing the data transfer can be specified in advance, and the expected completion time expect_time is compared with the specified completion time complete_time to determine whether or not the expected time falls within the specified completion time.
In addition, the system can accept a plurality of data transfer requests from the connected input / output device. These I / O requests are managed in a queue.
[0061]
FIG. 7 shows an image of the queue. Register necessary information such as ID to distinguish requests, input / output request source, transfer status, amount of data, specified transfer completion time, etc. in the queue for each input / output request, and transfer requests sequentially Will continue. Each time the status changes such as when the transfer actually starts or the transfer ends, the request source is notified of the transfer status for the request together with the request ID.
The order of input / output can be changed by arbitrarily changing the order of transfer requests registered in the queue.
It is also possible to prohibit the operation of the transfer request by deleting the request from the queue.
Here, when it is deleted from the queue, the request source is notified of the cancellation status together with the request ID.
By having a plurality of queues (such as the input side and the output side), a plurality of inputs / outputs can be realized simultaneously.
[0062]
[Embodiment 2]
A second embodiment of the present invention will be described.
In the first embodiment, when a new input / output request is received and the completion time complete_time is specified, the expected completion time expect_time is calculated from the current operation state.
The expected completion time expect_time is compared with the requested completion time complete_time to determine whether the expected time falls within the completion time.
If it is determined that it does not fit, the requested action is prohibited and the request is deleted from the queue.
[0063]
【The invention's effect】
As is apparent from the above description, according to the present invention, designation of the processing time related to the productivity of the image forming apparatus according to the configuration of the storage device and the image input / output means, and execution of the operation within the requested processing time. Therefore, it is possible to determine the storage device that constitutes the image forming apparatus, the configuration of the image output means, and the means for realizing and managing the optimal and detailed productivity according to the performance. It becomes possible.
[0064]
In particular, A configuration in which a plurality of image input / output means (for example, an interface capable of connecting a scanner, a printer, and a computer capable of data distribution (input / output)) is connected to the image forming apparatus, and a plurality of image signals can be input / output simultaneously. If so, means for prohibiting (including postponing) execution of the requested operation according to the requested image input / output operation according to the operation state of the storage device at the time of the request and the specified content of the requested processing time Set up By doing so, it is possible to perform processing as specified according to the specified contents of the processing time of all the requested operations during operation execution.
[0065]
Also Especially, by prohibiting the requested action, the requested action cannot be executed, but the processing time does not change for the running action (if multiple actions are executed, it can be executed within the specified time. However, the processing time may be long), and the image forming apparatus can be controlled so as to suppress fluctuations in the operation time.
[Brief description of the drawings]
FIG. 1 is an example in which an image data output apparatus of the present invention is used in a digital copying machine.
FIG. 2 is a view of a document table viewed from above.
FIG. 3 is a diagram illustrating a state of an image synchronization signal output from an IPU of a reading unit.
FIG. 4 is a configuration diagram of a storage unit.
FIG. 5 is a diagram illustrating a configuration of an address generation unit and a comparison unit of the memory control unit 4-3.
FIG. 6 is a diagram illustrating a descriptor access operation and a data transfer operation of a video input DMAC.
FIG. 7 is an image of a queue for managing input / output requests.
[Explanation of symbols]
4-1 Image I / O DMAC
4-2 Image memory
4-3 Memory controller
4-4 Image transfer DMAC
4-5 Code transfer DMAC
4-6 Compression and decompression device
4-7 HDD controller
4-8 HD
5-1 Input / output image address counter
5-2 Transfer image address counter
5-3 Line setting section
5-4 Difference calculation unit
5-5 Difference comparison unit
5-6 Address selector
5-7 Arbiter
5-8 Request mask
5-9 Access control circuit

Claims (3)

In an image input / output device having a storage means for storing an image signal input from the image input means, and outputting the image signal stored in the storage means to the image output means,
A data transfer capability storage unit that measures and stores data transfer capability between the image input unit and the storage unit and between the image output unit and the storage unit;
A request execution management means for receiving a plurality of data transfer requests including a data amount of data relating to data transfer and a data transfer completion time of the data, and storing the request as a queue ;
When there is a data transfer request, the data transfer request time is calculated based on the data amount and the data transfer capability, and the data transfer request stored in advance by the request execution management means calculated between the time anticipated completion of the data transfer request on the basis of the expected completion time, between the time of the expected completion holds sometimes the data transfer request falls within the data transfer completion time, the is between the time of the expected completion Control means for deleting the data transfer request from the queue when it does not fall within the data transfer completion time ;
An image input / output device comprising:   The storage means includes a primary storage unit that stores an image signal input from the image input unit, and a secondary storage unit that stores an image signal stored in the primary storage unit. The image input / output device according to claim 1, wherein: 3. The image input / output apparatus according to claim 1, wherein said request execution management means is means for storing at least a queue of data transfer requests on the input side and a queue of data transfer requests on the output side. .

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