JP4197916B2 - Data processing apparatus, data processing method, data processing program, and recording medium - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data processing apparatus comprising a plurality of data processing means for accessing and processing a memory shared for data storage, and Data processing method About.
[0002]
[Prior art]
In recent years, for example, copying machines (image forming apparatuses) have been digitized. Along with this, various functions have been installed in addition to image processing functions for processing and editing images.
As one of the functions that have been installed, there is a function called electronic sorting that stores image data for a plurality of originals in a memory so that a designated number of copies can be copied and output together to eliminate sorting work. If a plurality of pieces of image data can be stored in the semiconductor memory, the amount of image data is large and the cost is enormous. Therefore, in order to reduce the cost, the following configuration is generally used.
1. A secondary memory device such as a hard disk device having a configuration of a semiconductor memory + storage memory and a lower cost per unit memory capacity than the semiconductor memory is used as the storage memory (hereinafter referred to as “first configuration”).
2. Using a semiconductor memory as the storage memory, compressing image data using compression processing, and reducing the amount of data per sheet reduces the required storage capacity (hereinafter referred to as “second configuration”).
3. Multiple image input / output means (image scanner, printer controller, file server, FAX controller, etc.) share the same memory (hereinafter referred to as “third configuration”)
[0003]
In order to execute input / output of image data to / from a memory, a memory control controller (hereinafter referred to as a DMA controller) using a DMA (Direct Memory Access) data transfer method is often used. The DMA controller accesses a specific area of the memory based on information indicating a data transfer method called a descriptor. It is also possible to divide a memory area in which one image is stored by a plurality of descriptors and perform data transfer. For example, by using a memory in the form of a ring buffer, the memory capacity can be smaller than the capacity of image data. Image data input / output can also be executed. Patent document 1 is mentioned as reference technical literature.
In memory access control using a DMA controller, it is possible to grasp the progress (start, end) of data transfer specified by each descriptor, and control the execution timing of data transfer (interruption, start, (It is also possible to notify the end interrupt of each descriptor, etc.), so that there is a high degree of freedom in controlling the timing of access to a semiconductor memory connected to the DMA controller and a large-capacity secondary storage device, and the application range is wide. is there.
[0004]
As described above, in the first configuration in which the secondary storage device such as the hard disk device is used as the storage memory in addition to the semiconductor memory, usually, a plurality of data transfers (data writing and reading operations) to a single storage device. Can not do. For this reason, the data transfer (access) unit to the secondary storage device is divided using the descriptor of the DMA controller, and this is executed in time division, so that a plurality of data transfer operations are executed in parallel. It is common to do so.
Naturally, when such a time division process is used, the total time required for data transfer is not shortened. For this reason, when the time required for input / output of image data further affects the productivity of the apparatus as in an image forming apparatus, the time-sharing process conversely causes a decrease in productivity. Sometimes. Therefore, the time required for data transfer to the secondary storage device by further adopting the second configuration in which the image data is compressed to reduce the data transfer amount or the secondary storage device having a high data transfer speed is installed. Was made shorter. For the purpose of simplifying memory access control, time-division transfer is not actively performed, and the secondary storage device occupies resources as resources substantially in synchronization with image data input / output operations by the image input / output means. The technique is usually used.
Usually, the data transfer speed between the semiconductor memory and the secondary storage device is smaller than the data transfer speed between the image input / output means and the semiconductor memory. Even if the amount of data accessed to the secondary storage device is reduced by compressing the image data, there is little change in the data transfer speed between the image input / output means and the semiconductor memory. Even if the transfer timing control of the data transfer process (including data conversion process such as data compression) between the apparatuses is performed independently and optimally, the productivity of the image forming apparatus has not been improved so much.
[0005]
The transfer speed of a secondary storage device such as a hard disk device has been improved year by year, and the productivity is improved by improving the transfer speed. However, in recent high-speed copiers, it is possible to read both sides of the document simultaneously, the processing capability (speed) of the image input / output means is improved, or in order to achieve productivity, There are also models that require a higher transfer rate because there is a mechanical restriction that transport is performed in non-intervals. For this reason, recently, the current access status to the secondary storage device, its characteristics (performance), etc. are used for switching control for determining whether or not the image input means transports the document for reading an image at non-intervals. There is a growing need to consider.
[Patent Document 1]
JP 2000-158724 A
[0006]
[Problems to be solved by the invention]
As described above, with the recent advancement of technology, the data transfer speed accompanying access to a large-capacity secondary storage device such as a hard disk device can be used for image input / output even if the data amount is reduced by data compression. It is not always a sufficient speed for the data transfer speed of the means. For example, if the image output means outputs a color image from multiple color image data, can the color image be output properly unless the image data stored in the secondary storage device is input within a predetermined time? Or, the time required for the output becomes longer and the productivity is remarkably lowered. For this reason, it is considered that the image forming apparatus needs to be able to cope with this.
For example, in FAX transmission, there is a rule concerning data transfer time in a data transfer protocol using a telephone line. According to the convention, if data transmission is not performed within a certain time, the connection is disconnected and data cannot be transmitted. The FAX transmission function is a general function for the data processing apparatus. For this reason, in other data processing devices in which there is a restriction on access time in at least one of a plurality of data processing means that may access the secondary storage device for processing, the secondary storage device It can be said that it is necessary to be able to cope with the fact that the access speed is not fast enough.
In the present invention, when a time limit required for data transfer exists in at least one of a plurality of data processing means that may access a memory including a shared secondary storage device, the memory is always satisfied so as to satisfy the constraint. It is an object of the present invention to provide a data processing apparatus that accesses the network.
[0007]
[Means for Solving the Problems]
The data processing apparatus of the present invention is premised on having at least data processing means capable of accessing and processing a memory shared for data storage, and accesses the memory for processing performed by the data processing means. The transfer completion time specifying means for specifying the transfer completion time to complete the data transfer accompanying the access as necessary, and when accessing the memory for processing performed by the data processing means, at that time In consideration of the access status to the memory, an expected transfer completion time calculation means for calculating an expected transfer completion time expected to be required for completion of data transfer accompanying the access, and a transfer designated by the transfer completion time designation means Based on the completion time and the expected transfer completion time calculated by the expected transfer completion time calculation means, the memory processing is performed by the data processing means. Comprising the access management means for managing the processes, the.
Note that the above configuration includes another memory that is used to save data stored in the memory and has a lower transfer speed than the data transfer speed associated with accessing the memory. When data transfer is performed between the memories, it is desirable that the expected transfer completion time calculation means calculates the expected transfer completion time in consideration of the data transfer.
Further, when the access management means newly accesses the memory for processing performed by the data processing means, the expected transfer completion time calculated by the expected transfer completion time calculation means is determined from the transfer completion time designated by the transfer completion time designation means. If it is too long, it is desirable to prohibit or postpone new access to the memory. Image forming apparatus In the image forming apparatus, the image input means for inputting the image data stored in the memory is the first data processing means, and the image output means for outputting the image data stored in the memory is the second data processing means. It is desirable that
The program of the present invention is based on the premise that a data processing device having at least data processing means capable of accessing and processing a memory shared for data storage is executed, and for processing performed by the data processing means. When accessing the memory, specify the transfer completion time to complete the data transfer associated with the access as necessary. Transfer completion time specification step When the memory is accessed for processing performed by the data processing means, the expected transfer completion expected to be required for completion of the data transfer accompanying the access in consideration of the access status to the memory at that time Calculate time Expected transfer completion time calculation step And, based on the transfer completion time specified by the specified function and the expected transfer completion time calculated by the function to be calculated, access to the memory for processing performed by the data processing means is managed. Access control steps And realize.
In the present invention, when a shared memory is accessed for processing performed by at least the mounted data processing means, a transfer completion time for completing the data transfer accompanying the access is designated as necessary, and at that time The expected transfer completion time expected to be required to complete the data transfer associated with the access is calculated in consideration of the access status of the memory, and based on the specified transfer completion time and the calculated expected transfer completion time, It manages access to the memory for processing performed by the data processing means. As a result, even if there is a time limit required for data transfer, access to the memory and data transfer associated with the access can be performed while always satisfying the constraint. As a result, each data processing means can optimally perform the processing to be performed without substantially reducing the processing speed, and the data processing apparatus can always maintain high productivity.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a configuration diagram of a data processing apparatus (digital multifunction peripheral) according to this embodiment.
The digital multi-function peripheral can function as a copying machine or a facsimile machine. As shown in FIG. 1, a reading unit 101 that reads an image of a document and an image forming unit 102 that forms (prints) an image on a transfer sheet. A FAX unit 103 that transmits and receives data via a telephone line, an operation unit 104 in which various keys and a display unit are arranged, a storage unit 105 that stores image data, and a selector unit that switches a destination of image data 106 and a system control unit 107 that controls the entire multifunction peripheral.
The reading unit 101 performs scan exposure by moving the exposure lamp 113 in the sub-scanning direction in FIG. 2 along the document table 111 and moves the reflected light from the document 112 placed on the document table 111. This is reflected to the CCD image sensor 114 by the reflection mirror, and photoelectric conversion is performed by the sensor 114 to obtain an electric signal corresponding to the intensity of light. An IPU (image processing unit) 115 performs processing such as shading correction on the electrical signal and then A / D converts it into 8-bit digital image data, and further performs image processing such as scaling processing and dither processing. I do. When the image data after the image processing is output immediately, it is sent to the image forming unit 102 together with the image synchronization signal.
In order to realize the above-described process, the scanner control unit 116 performs detection processing by various sensors, controls a drive motor for moving the exposure lamp 113, and the like, and sets various parameters for the IPU 115. Thereby, the entire reading unit 101 is controlled.
[0009]
Here, the output of image data by the IPU 105 of the reading unit 101 will be described with reference to FIG.
A frame gate signal / FGATE in FIG. 3 represents a valid image range for the image area in the sub-scanning direction, and image data while this signal / FGATE is at a low level (low active) is validated. . This signal / FGATE is asserted or negated at the falling edge of the line synchronization signal / LSYNC. The signal / LSYNC is asserted for a predetermined number of clocks at the rising edge of the pixel synchronization signal PCLK, and image data in the main scanning direction is validated after a predetermined number of clocks after the rising of this signal. The transmitted image data is one for one cycle of the pixel synchronization signal PCLK, and is divided in the main scanning direction of FIG. 2 into 157.5 DPC (= 400 DPI). The image data is sent in a raster format for sending data in the main scanning direction while changing the position in the sub-scanning direction. The sub-scanning effective range of image data is usually determined by the transfer paper size.
In the image forming unit 102, the photosensitive member 122 that is uniformly charged by the charging charger 121 and rotates at a constant speed is exposed with a laser beam modulated by the image data from the writing unit 123. An electrostatic latent image is formed on the photosensitive member 122 by the exposure, and a developed toner image is formed by developing the electrostatic latent image with the developing device 124. The transfer paper in the paper feed tray 125 is fed out by the paper feed roller 126 and conveyed to the registration roller 127, and is started to be conveyed by the roller 127 at a timing overlapping with the toner image on the photoconductor 122. The toner image is electrostatically transferred onto the transfer paper. The portion of the transfer paper to which the toner image is transferred is separated from the photoreceptor 122 by the separation charger 129. The toner image on the transfer paper is heated and fixed by the fixing device 130, and then discharged to the discharge tray 132 by the discharge roller 131.
The toner remaining on the photoreceptor 122 after the electrostatic transfer is removed by the cleaning device 133. After the removal, the photoreceptor 122 is neutralized by the neutralization charger 134. In order to realize the above processes, the plotter control unit 135 performs detection processing by various sensors, and controls various driving motors for driving the photosensitive member 122, the paper feeding roller 126, the registration roller 127, the fixing device 130, and the like. Do.
[0010]
The system control unit 107 communicates various parameter settings, process execution instructions, and the like to the reading unit 101, the storage unit 105, the image forming unit 102, or the FAX unit 103 in accordance with an operation on the operation unit 104 by an operator. Do. The state of the entire system is displayed on the display unit of the operation unit 104. Thereby, the system control unit 107 performs control in a manner corresponding to the operation of the operator on the operation unit 104.
In response to an instruction from the system control unit 107, the FAX unit 103 compresses the binary image data of the image data sent from the increment program 115 or the storage unit 105 based on the G3 and G4 FAX data transfer rules, and the telephone line Forward to. The data received from the telephone line is restored and sent to the writing unit 123 of the image forming unit 102. Thereby, the received data is visualized.
In response to an instruction from the system control unit 107, the selector unit 106 changes the connection state of the selectors that configure the selector unit 106, and sets the output destination of image data to be subjected to image formation by the image forming unit 102 as the reading unit 101 and storage unit. 105 and the FAX unit 103 are selected.
The storage unit 105 normally stores image data of a document input from the IPU 115, and is used for a copy application such as repeat copy or rotation copy. Further, it is also used as a buffer memory for temporarily storing binary image data from the FAX unit 103. These data are stored in accordance with instructions from the system control unit 107.
[0011]
FIG. 4 is a configuration diagram of the storage unit. Next, the storage unit 105 will be described in detail with reference to FIG.
The image input / output DMAC 401 includes a CPU and a logic circuit, communicates with the memory control unit 403, receives a command, and sets an operation according to the command. Status information indicating the current state is transmitted to the memory control unit 403.
When an image input command is received from the memory control unit 403, the image data input through the selector unit 106 is packed into memory data in units of 8 pixels according to the image synchronization signal / FGATE, and the memory control unit 403 is accessed by the memory. Output with the signal at any time. When an image output command is received, the image data received from the memory control unit 403 is output in synchronization with the image synchronization signal / FGATE.
The image memory 402 stores image data and is composed of a semiconductor storage element such as a DRAM. The memory capacity is, for example, 157.5 DPC (= 400 DPI), 4 MB for A3 size in binary image data, and 8 MB in total for 4 M bytes for electronic sort storage. The memory control unit 403 accesses.
The memory control unit 403 includes a CPU and a logic circuit, communicates with the system control unit 107, receives a command, performs operation settings according to the command, and notifies the current state of the storage unit 105 Information is transmitted to the control unit 107.
Some commands from the system control unit 107 are for instructing image input, image output, compression, decompression, and the like. Image input and image output commands are transmitted to the image input / output DMAC 401, and compression-related commands are image transfer. The data is transmitted to the DMAC 404, the code transfer DMAC 405, and the compression / decompression unit 406.
[0012]
FIG. 5 is a diagram illustrating an internal configuration of the memory control unit 403. Here, the internal configuration of the control unit 403 and the operation of each unit will be described in detail.
The input / output image address counter 501 is an address counter that counts up in response to an input / output memory access request signal received from the image input / output DMAC 401. The input / output image address counter 501 stores image data to be input or output. 22-bit memory address data is output. The address is initialized once when the memory access is started.
The transfer image address counter 502 is an address counter that counts up in response to a transfer memory access permission signal output from the arbiter 507, and outputs 22-bit memory address data indicating a storage location where the transfer image data is stored. The address is initialized once at the start of memory access.
When the image memory 402 is used as a buffer at the time of image data input, the line setting unit 503 is a target that the difference comparison unit 505 compares with the difference between the input processing line number output from the difference calculation unit 504 and the transfer line number. Is received from the system control unit 107 and held. Arbitrary values can be held (set).
When image data is input, the difference calculation unit 504 subtracts the number of input / output processing lines output from the image input / output DMAC 401 from the number of transfer processing lines output from the compression / decompression unit 406 and sets the subtraction result as the number of difference lines as a difference comparison unit 505. Output to.
When image data is input, the difference comparison unit 505 compares the number of difference lines output from the difference calculation unit 504 with the set value output from the line setting unit 503. If the number of difference lines = the set value, the difference is inactive. If they do not match, an active transfer request mask signal is output to the request mask 508. Otherwise, the signal is not activated if no image data is being input / output.
The address selector 506 selects one of the address data output from the address counters 501 and 502 by the arbiter 507.
[0013]
The arbiter 507 outputs a memory access permission signal for notifying that the compression / decompression unit 406 is permitted to access the hard disk device (HDD) 408. The permission signal is activated under the condition that the transfer request mask signal input via the request mask unit 508 is active and the input / output memory access request signal is inactive. The address selector 506 outputs a signal for switching address data to be selected / output as necessary.
The request mask unit 508 masks the transfer memory access request signal for the compression / decompression unit 406 to access the HDD 408 via the HDD controller (HDDC) 407 based on the transfer request mask signal input from the difference comparator 505 (disenabled state). Then, the data transfer process is stopped.
The access control circuit 509 divides the address data input via the address selector 506 into a row address part and a column address part, and outputs them to an 11-bit address bus. Further, in accordance with an access start signal from the arbiter 507, control signals (RAS, CAS, WE) for the image memory 402 which is, for example, a DRAM are output.
In response to an image input instruction from the system control unit 107, the memory control unit 403 is initialized and waits for image data, and the image data can be stored in the storage unit 105 by the operation of the reading unit 101. The image data input to the storage unit 105 is once written in the image memory 402. The number of processing lines of the written image data is counted by the image input / output DMAC 401 and transmitted to the memory control unit 403 as the number of input / output processing lines. The compression / decompression unit 406 receives an image transfer command from the memory control unit 403 and outputs a transfer memory access request signal to the request. The request signal is masked by the request mask unit 508 of the memory control unit 403 and accessed accordingly. Is not done. When the image data from the image input / output DMAC 401 is completed for one line, the mask of the transfer memory access request signal is released, the image data is read from the image memory 402, and the transfer operation to the compression / decompression unit 406 is started. . During the operation, the difference calculation unit calculates the difference between the two processing lines, and if the difference becomes 0, the transfer memory access request signal is masked so that the address is not overtaken.
[0014]
Returning to the description of the storage unit 105 shown in FIG.
The image transfer DMAC 404 includes a CPU and a logic circuit, communicates with the memory control unit 403, receives a command, performs operation setting according to the command, and transmits status information for notifying the current state. When a compression command is received, a memory access request signal is output to the memory control unit 403, and when the memory access permission signal is active, image data is received and transferred to the compression / decompression unit 406. A built-in address counter that counts up in response to a memory access request signal is generated. The 22-bit memory address data indicating the storage location where the image data is read out or stored is generated using the count value. Output.
The code transfer DMAC 405 includes a CPU and a logic circuit, communicates with the memory control unit 403, receives a command, performs operation setting according to the command, and transmits status information for notifying the current state. When a decompression command is received, a memory access request signal is output to the memory control unit 403. When the memory access permission signal output by the control unit 403 becomes active, image data is received and transferred to the compression / decompression unit 406. . A built-in address counter that counts up in response to a memory access request signal is generated. The 22-bit memory address data indicating the storage location where the image data is read out or stored is generated using the count value. Output. The access operation by the descriptor of the DMAC 405 will be described later.
The compression / decompression unit 406 includes a CPU and a logic circuit, communicates with the memory control unit 403, receives a command, performs operation setting according to the command, and transmits status information for notifying the current state. . Binary image data is compressed by the MH encoding method.
The HDC controller (HDDC) 407 includes a CPU and a logic circuit, communicates with the memory control unit 403, receives a command, performs operation settings according to the command, and outputs status information for notifying the current state. Send. Read or access (data transfer) the status information of the HDD 408. The HD 408 is a secondary storage device.
The storage unit 105 configured as described above writes image data in the storage area secured in the image memory 402 by the image input / output DMAC 401 or inputs the image data and stores data according to instructions from the system control unit 107. Read the image data stored in the storage area. At this time, the image input / output DMAC 401 counts the number of lines of image data, and outputs the number of lines to the memory control unit 403 as the number of input / output processing lines.
[0015]
FIG. 6 is a diagram for explaining an access operation (data transfer operation) by the descriptor of the code transfer DMAC 405. Here, a case where image data is divided into four bands and the data transfer is performed will be described as an example. The operation is the same in the other DMACs 401 and 404.
First, a procedure for adding the total number of transfer lines in one image data will be described.
The code transfer DMAC 405 is activated by receiving a transfer command from the memory control unit 403, and the descriptor received from the control unit 403 is an area secured on the descriptor storage register 601 for the store, which is data having a CPU. Stores in order from the chain destination address (here, a address) set by the transfer control unit 602 (here, descriptor 1 is the head).
The descriptor loaded in the register 601 has a chain destination address indicating the storage area (the start address) of the next descriptor, a data transfer destination address indicating the start address of the data to be transferred, and the data amount of the data to be transferred in the number of lines. This is a 4-word configuration consisting of format information that can specify whether or not to generate a CPU interrupt when the number of data transfer lines shown and the data transfer of the set number of lines are completed. In the least significant bit of the format information, a bit for designating whether or not to generate a CPU interrupt when data transfer for the set number of lines is completed is arranged. If the value is 0, a CPU interrupt is generated, and if it is 1, the occurrence is masked.
In the example shown in FIG. 6, the image data is divided into four bands, and the value of the least significant 1 bit of the format information of each descriptor is all zero. When the transfer of image data for each band is completed, a CPU interrupt is generated. By the generation of the interrupt, the number of lines set in each descriptor is added so that data transfer can be performed while detecting the transfer end timing and the number of lines. It has become.
[0016]
When data is transferred from the image memory 402 to the HDD 408 through the compression / decompression unit 406 (primary storage device → secondary storage device), the descriptor setting of the memory control unit 403 is for data transfer for one band. The number of lines is set as the number of image lines. The number of lines is stored, and a descriptor whose storage destination address indicates the code transfer DMAC 405 is output to the image transfer DMAC 404. In the descriptor output to the code transfer DMAC 405, the data storage destination address is set to indicate the HDDC 407. As a result, image data is transferred through a path of image memory 402 → memory control unit 403 → image transfer DMAC 404 → code transfer DMAC 405 → compressor / decompressor 406 → HDDC 407 → HDD 408. After the data transfer is completed, the used capacity when the data is stored in the HDD 408 is notified from the HDDC 407, and the address (for example, the head address) where the image data is stored in the HDD 408 and the used capacity are secured in the image memory (primary storage device) 402. Stored in the HDD management area. During the data transfer, the memory control unit 403 masks the transfer memory access request so that the transfer of the image data to the compression / decompression unit 406 does not overtake the transfer from the code transfer DMAC 405. Thereby, control is performed so that the data transfer to the HDD 408 does not overtake the data transfer therefor.
Conversely, when data is transferred from the HDD 408 to the image memory 402 through the compression / decompression unit 406 (secondary storage device → primary storage device), the data is transferred to the HDD 408 stored in the HDD management area secured in the image memory 402. The storage address and the used capacity at the time of accumulation are acquired, the storage destination address is designated in the HDDC 407, the used capacity is set in the code transfer DMAC 405, and the number of lines after decompression is set in the image transfer DMAC 404, and the HDD 408 → HDDC 407. → Compression / decompression unit 406 → Code transfer DMAC 405 → Image transfer DMAC 404 → Memory control unit 403 → Image memory 402 is transferred through a path. In the case of performing data transfer through other paths, the memory control unit 403 outputs the descriptor created by the same method to the DMAC to be output, thereby realizing data transfer through the path.
As described above, the image memory 402 and the HDD 408 are shared for storing data to be processed. In the present embodiment, due to a decrease in the data transfer rate caused by the sharing, each unit 101 to 103 cannot properly process or the processing time becomes very long as follows. I am trying to avoid it.
[0017]
The data transfer rate varies depending on the system configuration and the devices used. In this embodiment, as the data transfer speed, the data transfer speed rx_speed1 between the reading unit 101 (FAX unit 103) → the image memory 402, the data transfer speed rx_speed2 between the image memory 402 → the HDD 408 (when data is input), The data transfer speed tx_speed1 between the HDD 408 and the image memory 402, the data transfer speed tx_speed2 between the image memory 402 and the image forming unit 102 (FAX unit 103), and the like are set as specific characteristic values, for example, not shown in the system control unit 107 Is stored in advance in a non-volatile memory.
The expected transfer completion time expected to complete the data transfer is calculated in consideration of the data amount data1 and the data transfer path, the data transfer speed determined by the path, and the like. For example, when the image data output by the reading unit 101 is stored in the HDD 408, the expected transfer completion time expect_time is:
expect_time = data1 / rx_speed1 + data1 / rx_speed2 + wait_time
For example, when outputting the image data stored in the HDD 408 to the image forming unit 102, the expected transfer completion time expect_time is:
expect_time = data1 / tx_speed1 + data1 / tx_speed2 + wait_time
Calculate more. Here, wait_time is a waiting time required other than actually performing data transfer. It varies depending on the operating state at that time as follows.
wait_time = WAIT_DRAM + WAIT_HDD + α
Here, WAIT_DRAM is a time until the image memory 402 is released and can be used for the request when the image memory 402 has been previously occupied by another request. The calculation is performed in consideration of the remaining time of the expected transfer completion time, the presence / absence of other transfer requests that are currently waiting, and the expected transfer completion time, if any. WAIT_HDD is a time until the HDD 408 is released and can be used for the request when it is previously occupied by another transfer request. Calculate in the same way as the time WAIT_DRAM. α is the time required for other overhead, and the worst value (longest time) is used as a fixed value.
For example, the memory control unit 403 calculates the waiting time wait_time by calculating the times WAIT_DRAM and WAIT_HDD as necessary, and notifies the system control unit 107 of it. The expected transfer completion time expect_time is calculated by the system control unit 107 using the wait time wait_time notified from the memory control unit 403. The data amount data1 necessary for calculating it is acquired from the request source that requested the data transfer.
[0018]
When requesting data transfer, the system control unit 107 designates a transfer completion time complete_time, which is a time to complete the data transfer, as necessary. The time complete_time is a time calculated based on the amount of data and the minimum data transfer speed obtained at the data transfer destination or transfer source. By comparing the time complete_time with the expected transfer completion time expect_time, it is determined whether or not the actual data transfer is completed within the transfer completion time.
When the data transfer is performed by time division processing, the expected transfer completion time in another transfer request may change due to the requested data transfer. Therefore, if it is determined that the transfer is completed within that time, the expected transfer completion time when the transfer request is received is calculated again, and the data transfer is completed within the transfer completion time even if the transfer request is received. When it is confirmed that there is no transfer request to be eliminated, a new transfer request is accepted. Such determination / confirmation is performed each time a transfer request is newly made, and if it can be determined that data transfer is completed with all transfer requests within the transfer completion time, the transfer request is accepted. . The received transfer request is managed in a queue as shown in FIG. If the transfer request is not accepted, the request source that made the request is notified of the fact.
When accepting a new transfer request in this way, the units 101 to 103 to which data is transferred or to which the data is transferred can optimally perform the processing to be performed without substantially reducing the processing speed. Become. For this reason, high productivity can always be maintained.
[0019]
As shown in FIG. 7, the queue includes information such as an ID for distinguishing the transfer request, the request source that made the request, the current state, the amount of data to be transferred, and the transfer completion time. Every time a transfer request is received, it is registered. As a result, the transfer requests are sequentially processed according to the order. In the queue, the transfer completion time is represented by the time at which the data transfer should be completed. Each time the status changes such as the start of transfer or the end of transfer, the request status is notified to the request source together with the ID.
The order of transfer requests registered in the queue can be changed arbitrarily. It is also possible to prohibit the operation of the transfer request by deleting the request from the queue. When deleted from the queue, the requester is notified of the cancellation together with the ID. In this embodiment, a plurality of queues such as the input side (data is transferred to the storage unit 105) and the output side are prepared so that a plurality of input / output data transfers can be realized simultaneously. .
In this embodiment, a new transfer request is accepted only when it can be determined that the data transfer is completed for all transfer requests within the transfer completion time. However, on the condition that such a determination can be made. Alternatively, the timing for starting the data transfer may be determined and accepted. Alternatively, considering the importance of the transfer request, that is, considering a response in which the transfer request that can be deleted or deferred to start the data transfer is deleted from the queue or the start of the data transfer is delayed. Then, the reception may be performed.
In the present embodiment, each of the units 101 to 103 corresponds to the data processing means, but the number and type of the data processing means are not limited to the present embodiment. The present invention can be widely applied to data processing devices equipped with a plurality of various types of data processing means.
An image forming apparatus (data processing apparatus) as described above, or a program that realizes the operation of the modified example may be recorded and distributed on a recording medium such as a CD-ROM, DVD, or magneto-optical disk. Alternatively, part or all of the program may be distributed via a transmission medium used in a public network or the like. In such a case, the user can apply the present invention to the apparatus by acquiring the program and loading it into an existing data processing apparatus. Therefore, the recording medium may be accessible by a device that distributes the program.
[0020]
【The invention's effect】
As described above, in the present invention, when a shared memory is accessed for processing performed by at least the first or second mounted data processing means, data transfer associated with the access should be completed. Specify the time as required, and calculate the expected transfer completion time that is expected to be required to complete the data transfer associated with the access, taking into account the access status to the memory at that time. And the access to the memory for processing performed by the first or second data processing means is managed based on the calculated expected transfer completion time. As a result, even if there is a time limit required for data transfer, access to the memory and data transfer associated with the access can be performed while always satisfying the constraint. For this reason, each data processing means can always perform the process to be performed optimally without substantially reducing the processing speed, and the data processing apparatus can always maintain high productivity.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a data processing apparatus (digital multifunction peripheral) according to an embodiment.
FIG. 2 is a diagram illustrating how to read an image of a document placed on a document table.
FIG. 3 is a timing chart illustrating a method for outputting image data by an IPU of a reading unit.
FIG. 4 is a diagram illustrating a configuration of a storage unit.
FIG. 5 is a diagram illustrating a configuration of a memory control unit of a storage unit.
FIG. 6 is a diagram for explaining an access operation (data transfer operation) by a descriptor of a code transfer DMAC that constitutes a storage unit;
FIG. 7 is a diagram illustrating a queue managed by a system control unit.
[Explanation of symbols]
101 Reading unit
102 Image forming unit
103 FAX section
105 Storage unit
106 Selector section
107 System control unit
401 Image input / output DMAC
402 Image memory
403 Memory control unit
404 Image transfer DMAC
405 Code transfer DMAC
406 Compression / decompression machine
407 HDDC
408 HDD

Claims (8)

In a data processing apparatus comprising at least data processing means capable of performing processing by accessing a memory shared for data storage,
When accessing the memory for processing performed by the data processing means, transfer completion time designating means for designating, as necessary, a transfer completion time to complete data transfer accompanying the access;
When accessing the memory for processing performed by the data processing means, the expected transfer completion expected to be required for completion of data transfer accompanying the access in consideration of the access status to the memory at that time An expected transfer completion time calculation means for calculating the time;
Based on the transfer completion time designated by the transfer completion time designation means and the expected transfer completion time calculated by the expected transfer completion time calculation means, the access to the memory for processing performed by the data processing means is managed. Access control means;
A data processing apparatus comprising: Used to save data stored in the memory, comprising another memory having a lower transfer rate compared to the transfer rate of data accompanying access to the memory,
When data transfer is performed between the memory and the other memory, the expected transfer completion time calculating means calculates the expected transfer completion time in consideration of the data transfer.
The data processing apparatus according to claim 1. When the access management means newly accesses the memory for processing performed by the data processing means, the expected transfer completion time calculated by the expected transfer completion time calculation means is designated by the transfer completion time designation means. If it is longer than the completion time, new access to the memory is prohibited or postponed.
The data processing apparatus according to claim 1 or 2, characterized by the above. In a data processing method including at least data processing means capable of performing processing by accessing a memory shared for data storage,
A transfer completion time designation step for designating, as necessary, a transfer completion time at which data transfer associated with the access is to be completed when accessing the memory for processing performed by the data processing means;
When accessing the memory for processing performed by the data processing means, the expected transfer completion expected to be required for completion of data transfer accompanying the access in consideration of the access status to the memory at that time An expected transfer completion time calculation step to calculate the time;
Based on the transfer completion time designated in the transfer completion time designation step and the expected transfer completion time calculated in the expected transfer completion time calculation step, access to the memory for processing performed by the data processing means is managed. Access management steps;
A data processing method comprising: Used to save data stored in the memory, comprising another memory having a lower transfer rate compared to the transfer rate of data accompanying access to the memory,
When data transfer is performed between the memory and the other memory, the expected transfer completion time calculation step calculates the expected transfer completion time in consideration of the data transfer.
5. A data processing method according to claim 4, wherein: In the access management step, when a new access is made to the memory for processing performed by the data processing means, the expected transfer completion time calculated by the expected transfer completion time calculation step is designated by the transfer completion time designation step. If it is longer than the completion time, new access to the memory is prohibited or postponed.
6. The data processing method according to claim 4 or 5 , wherein: A data processing program, wherein the data processing method according to any one of claims 4 to 6 is programmed so as to be controlled by a computer. 8. A recording medium in which the data processing program according to claim 7 is recorded in a computer-readable format.

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