JP3798553B2 - Image processing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image forming apparatus such as a copying machine, a printer, a facsimile, or the like, an image display apparatus that processes input data in response to a control signal, and an image processing apparatus in the image output apparatus.
[0002]
[Prior art]
In an image processing apparatus, with an increase in processing capability in recent years and an increase in copy speed of a copying machine, an increase in clock speed that is a reference time for processing has become severe. Along with this, the image data format in image processing and the relationship between the image data synchronization signal and the image data are improved, and the quantization number of the image data is reduced so that a plurality of pixels are bundled (packed). Increases image processing speed by processing multiple pixels at once, processing multiple image lines in parallel, or dividing one line into multiples for parallel processing Is being done.
[0003]
[Problems to be solved by the invention]
In view of the above, Japanese Patent Laid-Open No. 10-13626 discloses image processing by performing parallel processing on a plurality of lines at a time separately from a method of processing at a high frequency in order to increase the processing speed of data. However, in parallel processing, when performing parallel processing, the number of line memories such as FIFO that temporarily holds image data is increased in proportion to the number of parallel processing, together with necessary processing circuits. The circuit scale becomes large.
[0004]
Therefore, the present invention provides an image processing apparatus that can increase the speed of image processing while suppressing an increase in memory area by supporting a method in which one main scanning line is divided into a plurality of parts, and is further complicated. An object of the present invention is to provide an image processing apparatus capable of further improving the gradation expression by simplifying the memory access method to become and corresponding to the phase control.
[0005]
[Means for Solving the Problems]
In order to achieve the above object, an invention according to claim 1 is an image processing apparatus based on multi-level error diffusion, wherein one main scanning line is divided into a plurality of blocks and inputted in parallel for each block. A plurality of parallel processing blocks for simultaneously processing the image data, each of the plurality of parallel processing blocks each converting the received image data into image data having a bit number smaller than the data bit number; Calculation means for calculating an error generated when the quantization means re-quantizes, storage means for temporarily storing error data, and calculation of peripheral error data of image data to be processed with reference to a predetermined matrix and an arithmetic means for adding an error correction on the error data stored by the storage means, the image data to be processed is located at the boundary between the divided blocks error data It is characterized in further comprising means for passing between the parallel processing blocks computation information for calculating a.
[0006]
In order to achieve the above object, the invention according to claim 2 is the data according to claim 1, wherein the data between the parallel processing blocks at the time of the image data processing at the boundary between the divided blocks in the error diffusion processing. A flip-flop is used for delivery.
[0007]
In order to achieve the above object, the invention according to claim 3 is the invention according to claim 1,
The phase processing is performed after the error diffusion processing.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
First, an outline of a digital copying machine will be described as an example to which the present invention is applied.
FIG. 1 shows the appearance of a digital copying machine, and FIG. 2 shows a reading optical system of the digital copying machine.
[0009]
1 and 2, the document is set on the document table 1 so that the reading surface faces downward, and is illuminated by the light source 2, and the reflected light is sequentially converged and reflected through the mirror 3, the lens, and the relay mirror group 4. The image is read by an image line sensor (hereinafter, CCD) 5. Here, in order to increase the reading speed of the copying machine, it is possible to stack a plurality of CCDs 5 and to read as many lines as the number of CCDs 5 at a time. In FIG. 1, reference numeral 6 denotes an operation unit, and 7 denotes a paper cassette.
[0010]
In order to control input image data, a synchronization signal indicating an image range in the sub-scanning direction and the main scanning direction (hereinafter referred to as a sub-scanning range signal and a main scanning range signal) and a synchronization signal indicating a start point in the main scanning direction (Hereinafter, the main scanning synchronization signal) is used.
[0011]
3 and 4 show the relationship between the data read on the document table and the image control signal in a conventional general digital copying machine . In FIG. 3, a sub-scanning range signal (FGATE) is a signal indicating an image range in the scanning direction of the light source 2 and the mirror 3 in FIG. 2, that is, the sub-scanning direction, and a main scanning synchronization signal (LSYNC) is shown in FIG. The main scanning synchronization signal indicates the starting point of the line in the CCD 5 reading direction, that is, the main scanning direction, and the main scanning range signal (LGATE) is a signal indicating the image range in the main scanning direction. As shown in FIG. 4, the reading of the document in the main scanning direction is performed by scanning the line 1, the line 2, and the line 3 in the main scanning direction by the CCD 5.
[0012]
FIG. 5 shows a temporal relationship between these FGATE, LSYNC, and LGATE. Thus, the processing is performed by replacing the data of the two-dimensional original image with the image data on the time axis. In the present embodiment, processing similar to that described above is performed, and details thereof will be described later with reference to FIGS.
[0013]
FIG. 6 shows an example of the entire block configuration of the digital copying machine.
An instruction unit (hereinafter referred to as “CPU”) 10 that gives instructions for overall processing sends processing and setting instructions to each block. The image data read by the CCD 5 is first sent to the scanner 11, subjected to A / D conversion, subjected to scanner characteristic correction, and subjected to predetermined image quality processing such as dithering and error diffusion in the image processing unit 12. Thereafter, the image is output according to the image format of the lower block and sent to the image storage unit 13.
[0014]
The image storage unit 13 has a temporary memory area for image editing for at least one copy output paper (transfer paper) and a large-capacity storage medium such as HD, so that a large number of image data can be stored. Therefore, the image data compression / decompression function is provided to further increase the storage amount of the image information.
The printer 14 receives the image data from the image storage unit 13 and outputs it to transfer paper.
[0015]
FIG. 7 shows a known configuration example for error diffusion processing in the image quality processing unit that performs gradation processing (the error diffusion processing according to the present invention will be described in detail later with reference to FIG. 12 and the like) . Error addition unit 100 receives the input image data DFij to be processed pixel, the peripheral error information to the input image data DFij received from the error calculating unit 104, taking their sum, the input of after the error correction Pixel data SFij is output. Quantization unit 101, based on the input pixel data Sij after error correction, a combined quantization thresholds on the number of quantization for obtaining received from CPU 10 (N bits for M-bit input image data, where M> N) Then, gradation processing is performed, and output image data GFij is output.
[0016]
The error calculation unit 102 receives the input pixel data S F ij after error correction and the output image data G F ij and obtains a quantization error E F ij when the input image data D F ij is quantized. The quantization error E F iJ is written / read to / from a storage element such as a line memory in the error matrix storage unit 103. The error calculation unit 104 generates an error diffusion matrix having a shape as shown in FIG. 8 obtained from the error matrix storage unit 103, and in accordance with each matrix coefficient, the peripheral error of the input image data D F ij serving as the pixel to be processed Calculate information.
[0017]
In the case of an error matrix and its coefficients as shown in FIG. 8, the peripheral error information E for the pixel of interest Dij is
E = (Di-2, j-1 + 2 ^* Di-1, j-1 + 4 ^* Di, j-1 + 2 ^* Di + 1, j-1 + Di + 2, j-1 + 2 ^* Di-2, j + 4 ^* Di-1, j) / 16
Given in.
As shown in Japanese Patent Application Laid-Open No. 9-139847, the phase control unit 105 is arranged before and after the target pixel based on the phase control setting including the data after error diffusion, the phase mode, the image area determination result, and the phase determination threshold value. The phase signal for the target pixel is determined from the relationship between the image density and the image density, and has the effect of removing the texture that is peculiar to error diffusion processing.
[0018]
9 and 10 show the relationship between the data read on the document table and the image control signal in the present embodiment. The figure shows the relationship between the data read on the platen and the image control signal when one line is read in two divided in the main scanning direction. In FIG. 9, a sub-scanning effective area (hereinafter referred to as xfgate) is a signal indicating an image range in the scanning direction of the light source 2 and the mirror 3 in FIG. 2, that is, the sub-scanning direction, and a main scanning effective area 1 (hereinafter referred to as xflgate). The main scanning effective area 2 (hereinafter referred to as xllgate) is a signal indicating an image range in the main scanning direction. Although omitted in FIG. 9, a main scanning synchronization signal 1 (hereinafter referred to as xflsync) and a main scanning synchronization signal 2 (hereinafter referred to as xllsync) are obtained , and the reading direction of the CCD 5, that is, the start of a line in the main scanning direction is obtained. It is a signal indicating a point. However, since this CCD 5 divides one scan line into a plurality of parts, in the example of FIG. 10 showing an example in which the main scan line is divided into two, the first half line (F side) and the second half line (L side) Two pieces of image data are generated simultaneously in parallel (see FIG. 11) .
[0019]
As shown in FIG. 10, the reading of the document in the main scanning direction is performed by the CCD 5 separately scanning the lines A and C and E on the F side and the lines B and D and F on the L side separately. become. In the illustrated example, the scanning directions on the F side and the L side are the same, but the arrangement of the pixels on the F side and the L side can be changed by changing the arrangement of the charge accumulation of the CCD 5. is there.
[0020]
FIG. 11 shows the temporal relationship between these xfgate, xflsync, xllsync, xflgate, and xllgate.
In this case, the F-side and L-side image data and the control signal are shifted by xlsync and enter at the same timing. This is because the charge accumulation timings of the aligned CCDs 5 are the same. By shifting, the timing of the first / rutter side can be moved back and forth. As another method, the timing can be shifted using a line memory or the like at the stage of the interface unit from the scanner 11 to the image processing unit 12 in FIG.
[0021]
FIG. 12 shows a first configuration example of the error diffusion processing unit of the present invention. Since the F-side processing block shown on the upper side and the lower L-side processing block in the figure have the same symmetric configuration, in the following description, overlapping portions will be described by taking the F-side processing block as an example. To do. (F-side processing block) error addition unit 100 receives the input image data D F ij to be processed pixel, the peripheral error information to the input image data D F ij received from the error calculating unit 104, they And the input pixel data S F ij after error correction is output. The quantization unit 101 as the re-quantization means matches the error-corrected input pixel data S F ij and the number of quantizations received from the CPU 10 (N bits for input image data M bits, where M> N). Gradation processing is performed based on the quantized threshold value, and output image data G F ij is output.
[0022]
Error calculation unit 102 obtains an input pixel data S F ij after the error correction, it receives the output image data G F ij, a quantization error E F ij when the input image data D F ij is quantized. The error matrix F accumulation unit 106 or the error matrix L accumulation unit 107 writes / reads the quantization error EFij (or ELij) to / from a storage element such as a line memory while exchanging data in the vicinity of the line division boundary. I do.
[0023]
The error calculation units 104 and 104 generate an error diffusion matrix having the shape shown in FIG. 8 obtained from the previous error matris F or L accumulation unit (106 or 107), and in accordance with each matrix coefficient (F side If the processing block is taken as an example, peripheral error information of the input image data D F ij to be processed pixels is calculated. In the case of an error matrix and its coefficients as shown in FIG. 8, the peripheral error information E for the pixel of interest D F ij is E = (Di−2, j−1 + 2 ^* Di−1, j−1 + 4 ^* Di, j−1 + 2). ^* Di + 1, j-1 + Di + 2, j-1 + 2 ^* Di-2, j + 4 ^* Di-1, j) / 16. Further, the above processing blocks perform the same processing on the divided data.
[0024]
Here, the error matrix F accumulation unit 106 and the error matrix L accumulation unit 107 will be further described.
13 and 14 show a detailed example of the error matrix accumulating unit and the processing timing of the branch point of one line and two divisions in the error matrix accumulating unit.
[0025]
For the boundary in the n-th line in the sub-scanning direction shown in FIG. 14 (the boundary between the first side and the letter side), the error diffusion is performed at the first pixel on the first side and the first pixel on the side of the raster. Consider the formation of a matrix. In this case, in the case of error diffusion of a 5 × 2 reference matrix for main scanning / sub scanning as shown in FIG. 8, the previous line stored in the line memory (122, 123 in FIG. 13) such as FIFO is used . Data on the two pixels before and after the main scanning side and error diffusion data on the two pixels before the current processing line are referred to.
[0026]
In this case, as shown in the delivery data in FIG.
(1) For the first pixel on the first side, it is necessary to refer to the first two pixels (derr1) on the lutter side one line before,
(2) It is necessary to refer to the error diffusion data (dferr1) of the first last two pixels before one line and the error diffusion data (dferr0) of the first last two pixels of the current processing data at the first pixel on the raster side.
The two data will be transferred.
[0027]
As shown in FIG. 14, these timings overlap with each other's FIFO control on the first side / rutter side. As a result, in order to realize this processing, the data is temporarily held at the beginning of the line, and the FIFO is This is realized by writing the data received from the other party and performing the processing start timing sent by the half-cycle on the latter side a little earlier than the first side.
[0028]
Furthermore, the required amount of line memory by this method is a method of dividing one line and processing it simultaneously to reduce the processing time of one line, and the required amount of memory such as FIFO is eventually the same as the original one line. (The amount of memory for one line × the number of parallel processes / the number of divisions), which is not the amount of memory for the number of parallel processes × 1 line as in the case of processing a plurality of lines in parallel. scale increase Ru Tomah only to the arithmetic circuit component in parallel processing.
[0029]
Further, in the case of the above operation, data is exchanged between the processes on the first side / latter side, and read / write control is performed on the line memory such as FIFO, so that the access to the line memory becomes complicated, and as a result Therefore, the configuration of the processing circuit becomes complicated. In order to solve this problem, there is a method in which data is held in an FF (flip-flop) without being stored in the line memory and read out when necessary.
[0030]
this is,
In the case of {circle over (1)}: when dllrr1 is the first processing on the side of the jitter, the rising edge of xlgate is held in the FF as a cue, and is referred to when it is the last pixel on the first side (target pixel L).
In the case of {circle over (2)}: dferr0 and dferr1 are held in the FF as a cue at the rising edge of xflgate at the time of the first-side final processing, and are referred to at the first pixel (the target pixel M) on the raster side.
Thus, it is not necessary to perform read / write access to the FIFO by the processing on the other side (see the ratter side at the first side and the first side at the ratter side), and the circuit can be simplified.
[0031]
FIG. 15 shows a third configuration example of the present invention.
Here, in addition to the configuration of FIG. 12, a phase control unit F108 and a phase control unit L109 are added.
[0032]
When the phase control timing is considered in FIG. 16 with respect to the image data Gij after error diffusion, the target pixel is the nth line in the sub-scanning direction,
(1) Phase determination at the last pixel on the first side,
(2) Phase determination at the first pixel on the Lutter side,
In the two cases, it is necessary to refer to the pixels on the first / rutter partner side.
[0033]
In the case of {circle around (1)}, the phase processing is performed on the target pixel D with reference to the first pixel E on the side of the jitter, but if the pixel D and the pixel E are not processed continuously, the calculation result and the pixel delay are Since they do not coincide with each other, as shown in FIG. 16, it is necessary to perform processing on the first side and the lutter side continuously.
By adding this phase process after the error diffusion process, it is possible to remove the texture that is peculiar to error diffusion.
[0034]
【The invention's effect】
According to the first aspect of the present invention, it is possible to increase the image processing speed without increasing the processing frequency while suppressing an increase in the memory area, corresponding to a method in which one main scanning line is divided into a plurality of parts. Can do.
[0035]
According to the second aspect of the invention, in addition to the above effect, there is an effect that the complicated memory access method can be simplified.
[0036]
According to the third aspect of the invention, in addition to the above-described effect, there is an effect that the gradation expression can be further improved by supporting the phase control.
[Brief description of the drawings]
FIG. 1 is an external view of a digital copying machine.
FIG. 2 is a configuration diagram of a reading optical system.
FIG. 3 is a diagram illustrating an example of a relationship between a document and a control signal.
FIG. 4 is a diagram illustrating a specific example of image scanning of a digital copying machine.
FIG. 5 is a diagram illustrating a timing relationship of a synchronization signal group.
FIG. 6 is an overall block diagram of the digital copying machine.
FIG. 7 is a block diagram of a general error diffusion processing unit.
FIG. 8 is a diagram illustrating an example of an error diffusion matrix.
FIG. 9 is a diagram illustrating a relationship between a document and a control signal.
FIG. 10 is a diagram illustrating a specific example of image scanning.
FIG. 11 is a diagram illustrating a specific example of an image data control signal.
FIG. 12 is a block diagram of an error diffusion processing unit showing the first embodiment of the present invention.
FIG. 13 is a block diagram illustrating a detailed example of an error matrix storage unit.
FIG. 14 is a diagram illustrating the processing timing of a branch point when dividing one line into two.
FIG. 15 is a block configuration diagram of an error diffusion processing unit showing a second embodiment of the present invention;
FIG. 16 is a diagram illustrating a timing example of phase control.
[Explanation of symbols]
1 Document stage 2 Light source 3 Mirror 4 Mirror group 5 CCD
6 Operation section 7 Paper cassette 10 Instruction section (CPU)
11 Scanner 12 Image processing unit 13 Image storage unit 14 Printer 100 Error addition unit 101 Quantization unit 102 Error calculation unit 104 Error calculation unit 106 Error matrix F storage unit 107 Error matrix L storage unit

Claims (3)

A plurality of parallel processing blocks for dividing one main scanning line into a plurality of blocks and simultaneously processing image data input in parallel for each block;
Each of the plurality of parallel processing blocks is
Re-quantization means for converting the received image data into image data having a bit number smaller than the data bit number;
An arithmetic means for calculating an error generated when the requantization means requantizes;
Storage means for temporarily storing error data;
Calculation means for calculating peripheral error data of image data to be processed with reference to a predetermined matrix and adding error correction to the error data stored in the storage means ;
By multi-level error diffusion, characterized in that it includes means for transferring the operation information to calculate the error data of the image data to be processed is located at the boundary between the divided block between said parallel processing block Image processing device. 2. The image processing apparatus according to claim 1, wherein a flip-flop is used for data transfer between parallel processing blocks at the time of image data processing at the boundary between the divided blocks in error diffusion processing.   The image processing apparatus according to claim 1, wherein phase processing is performed after error diffusion processing.

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